专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

61. 发明授权

US06593845B1 Active RF tag with wake-up circuit to prolong battery life 有权
标题翻译：主动RF标签具有唤醒电路，延长电池寿命
公开(公告)号：US06593845B1
公开(公告)日：2003-07-15
申请号：US09407919
申请日：1999-09-29
申请人： Daniel J. Friedman , Thomas Anthony Cofino , Trieu C. Chieu
发明人： Daniel J. Friedman , Thomas Anthony Cofino , Trieu C. Chieu
IPC分类号： H04Q522
CPC分类号： G06K19/0705 , G06K19/0701 , G06K19/0723 , G07C2009/00793
摘要： An active RF transponder is provided with a wake-up circuit that wakes the RF transponder from a sleep state upon detection of an RF interrogating signal. The active RF transponder includes a battery, an antenna adapted to receive RF signals from an interrogator, and electronic circuitry providing the various RF transponder functions of sending/receiving signals and storing data. A first embodiment of the invention includes a wake-up circuit that periodically checks for the presence of an RF signal at the antenna. The wake-up circuit is coupled to the antenna and includes a switch adapted to selectively couple the battery to the electronic circuitry and provide electrical power thereto upon detection of the RF signals by the antenna. The wake-up circuit further comprises an oscillator providing a clock signal having a low duty cycle that defines intervals during which the antenna is sampled for presence of the RF signals (e.g., approximately 20 ns every 100 &mgr;s). A second embodiment of the RF transponder includes a wake-up circuit as in the first embodiment that is further adapted to detect a code sequence modulated in the RF signals. The code sequence is unique for a class of RF transponder, so the wake-up circuit can discriminate between interrogating signals. A third embodiment of the RF transponder includes a wake-up circuit that wakes the RF transponder upon detection of an RF signal that contains data within a desired band of frequencies. This embodiment enables the RF transponder to discriminate between RF signals that likely contain valid data and other RF noise. After the RF transponder has been waked, the wake-up circuit returns the RF transponder to a sleep state if valid data is not detected within a predetermined period of time.
摘要翻译：主动RF转发器具有唤醒电路，该唤醒电路在检测到RF询问信号时将RF应答器从睡眠状态唤醒。主动RF转发器包括电池，适于从询问器接收RF信号的天线以及提供发送/接收信号和存储数据的各种RF应答器功能的电子电路。本发明的第一实施例包括周期性地检查天线处的RF信号的存在的唤醒电路。唤醒电路耦合到天线，并且包括开关，其适于在通过天线检测到RF信号时选择性地将电池耦合到电子电路并提供电力。唤醒电路还包括振荡器，其提供具有低占空比的时钟信号，该时钟信号限定天线被采样以在RF信号的存在期间的间隔（例如，每100微秒大约20ns）。 RF转发器的第二实施例包括如第一实施例中的唤醒电路，其进一步适于检测在RF信号中调制的码序列。代码序列对于一类RF转发器是唯一的，因此唤醒电路可以区分询问信号。 RF转发器的第三实施例包括唤醒电路，其在检测到包含期望频带中的数据的RF信号时唤醒RF应答器。该实施例使得RF应答器能够区分可能包含有效数据的RF信号和其他RF噪声。在RF应答器已经被唤醒之后，如果在预定时间段内没有检测到有效数据，则唤醒电路将RF应答器返回到睡眠状态。

62. 发明授权

US06412086B1 Radio frequency identification transponder integrated circuit having a serially loaded test mode register 失效
标题翻译：射频识别应答器集成电路，具有串行测试模式寄存器
公开(公告)号：US06412086B1
公开(公告)日：2002-06-25
申请号：US09323429
申请日：1999-06-01
申请人： Daniel J. Friedman , David E. Dieska
发明人： Daniel J. Friedman , David E. Dieska
IPC分类号： G01R3128
CPC分类号： G06K7/0095 , G01R31/3025 , G06K19/0723 , G06K19/073
摘要： A radio frequency identification (RFID) transponder (tag) integrated circuit includes “on-chip” test circuitry. The test circuitry includes a serially-loaded test register. The test register controls the execution of on-chip tests. Such tests may include the testing of EEPROM circuitry included within the IC, the testing of analog circuitry, or the testing of digital circuitry included within the IC.
摘要翻译：射频识别（RFID）应答器（标签）集成电路包括“片上”测试电路。测试电路包括一个串行测试寄存器。测试寄存器控制片上测试的执行。这样的测试可以包括对IC内包括的EEPROM电路的测试，模拟电路的测试或IC内包括的数字电路的测试。

63. 发明授权

US6078845A Apparatus for carrying semiconductor devices 失效
标题翻译：用于承载半导体器件的装置
公开(公告)号：US6078845A
公开(公告)日：2000-06-20
申请号：US756296
申请日：1996-11-25
申请人： Daniel J. Friedman
发明人： Daniel J. Friedman
IPC分类号： H01L21/66 , H01L21/00 , H01L21/02 , H01L21/673 , G06F19/00
CPC分类号： H01L21/67288 , H01L21/67282 , H01L21/67326 , H01L21/67333 , H01L2221/68313 , Y10S438/907 , Y10S438/925
摘要： This invention pertains to the embedding of a information storage device within, or attached to, the carriers used to transport work in progress from step to step in the semiconductor manufacturing process. The carrier can be a tray having sites for several semiconductor dies, tubes for carrying several dies together, lead frames, wafer cassettes or individual die sockets. The information storage device can be formed integrally with the carrier or formed separately and attached or secured to the carrier.
摘要翻译：本发明涉及将信息存储装置嵌入或附加到用于在半导体制造过程中逐步运行的工作的载体。载体可以是具有用于多个半导体管芯的位置的托盘，用于将多个管芯携带在一起的管，引线框架，晶片盒或单个管芯插座。信息存储装置可以与载体一体地形成或单独形成并且附接或固定到载体上。

64. 发明授权

US09269042B2 Producing spike-timing dependent plasticity in a neuromorphic network utilizing phase change synaptic devices 有权
标题翻译：使用相变突触装置在神经元网络中产生尖峰时间依赖性可塑性
公开(公告)号：US09269042B2
公开(公告)日：2016-02-23
申请号：US12895791
申请日：2010-09-30
申请人： Daniel J. Friedman , Seongwon Kim , Chung H. Lam , Dharmendra S. Modha , Bipin Rajendran , Jose A. Tierno
发明人： Daniel J. Friedman , Seongwon Kim , Chung H. Lam , Dharmendra S. Modha , Bipin Rajendran , Jose A. Tierno
IPC分类号： G06N3/063 , G06N3/04 , G11C11/54 , G11C13/00
CPC分类号： G06N3/06 , G06N3/049 , G06N3/063 , G06N3/0635 , G06N3/08 , G11C11/54 , G11C13/0004
摘要： Embodiments of the invention relate to a neuromorphic network for producing spike-timing dependent plasticity. The neuromorphic network includes a plurality of electronic neurons and an interconnect circuit coupled for interconnecting the plurality of electronic neurons. The interconnect circuit includes plural synaptic devices for interconnecting the electronic neurons via axon paths, dendrite paths and membrane paths. Each synaptic device includes a variable state resistor and a transistor device with a gate terminal, a source terminal and a drain terminal, wherein the drain terminal is connected in series with a first terminal of the variable state resistor. The source terminal of the transistor device is connected to an axon path, the gate terminal of the transistor device is connected to a membrane path and a second terminal of the variable state resistor is connected to a dendrite path, such that each synaptic device is coupled between a first axon path and a first dendrite path, and between a first membrane path and said first dendrite path.
摘要翻译：本发明的实施例涉及一种用于产生尖峰时序相关可塑性的神经形态网络。神经元网络包括多个电子神经元和耦合用于互连多个电子神经元的互连电路。互连电路包括用于经由轴突路径，枝晶路径和膜路径互连电子神经元的多个突触装置。每个突触装置包括可变状态电阻器和具有栅极端子，源极端子和漏极端子的晶体管器件，其中漏极端子与可变状态电阻器的第一端子串联连接。晶体管器件的源极端子连接到轴突路径，晶体管器件的栅极端子连接到膜路径，并且可变状态电阻器的第二端子连接到树突路径，使得每个突触器件被耦合在第一轴突路径和第一枝晶路径之间以及在第一膜路径和所述第一枝晶路径之间。

65. 发明授权

US08736323B2 Method and apparatus for on-chip phase error measurement to determine jitter in phase-locked loops 有权
标题翻译：用于片内相位误差测量的方法和装置，用于确定锁相环中的抖动
公开(公告)号：US08736323B2
公开(公告)日：2014-05-27
申请号：US11622166
申请日：2007-01-11
申请人： Woogeun Rhee , Daniel J. Friedman
发明人： Woogeun Rhee , Daniel J. Friedman
IPC分类号： H03L7/06
CPC分类号： G01R31/31709
摘要： An apparatus includes a phase-locked loop (PLL) circuit including a phase-frequency detector configured to output phase error signals. A phase error monitor circuit is configured to determine instantaneous peak phase error by logically combining the phase error signals and comparing pulse widths of the logically combined phase error signals to a programmable delay time at each reference clock cycle to determine instantaneous phase error change. A storage element is configured to store the instantaneous phase error change.
摘要翻译：一种装置包括锁相环（PLL）电路，其包括被配置为输出相位误差信号的相位频率检测器。相位误差监视电路被配置为通过逻辑组合相位误差信号并将逻辑组合相位误差信号的脉冲宽度与每个参考时钟周期的可编程延迟时间进行逻辑组合来确定瞬时峰值相位误差，以确定瞬时相位误差变化。存储元件被配置为存储瞬时相位误差变化。

66. 发明申请

US20140070855A1 HYBRID PHASE-LOCKED LOOP ARCHITECTURES 有权
公开(公告)号：US20140070855A1
公开(公告)日：2014-03-13
申请号：US13608277
申请日：2012-09-10
申请人： Herschel A. Ainspan , Mark A. Ferriss , Daniel J. Friedman , Alexander V. Rylyakov , Jose A. Tierno
发明人： Herschel A. Ainspan , Mark A. Ferriss , Daniel J. Friedman , Alexander V. Rylyakov , Jose A. Tierno
IPC分类号： H03L7/107
CPC分类号： H03L7/1072 , H03L7/087 , H03L7/089 , H03L7/093
摘要： Phase locked loop (PLL) architectures are provided such as hybrid PLL architectures having separate digital integrating control paths and analog proportional control paths. An analog proportional control path can be implemented with a charge pump circuit that includes resistors in series with CMOS switches to generate control currents (e.g., Up/Down control currents) which are used to adjust a control voltage applied to a digitally controlled oscillator. A digital integrating control path can be implemented with a series of sigma-delta modulators that operate at different frequencies to convert higher bit data signals to lower bit data signals along the digital integrating control path. A single phase frequency detector may be implemented to generate control signals that separately control the analog proportional and digital integrating control paths.

67. 发明授权

US08665034B2 Varactor tuning control using redundant numbering 失效
标题翻译：变容二极管调谐控制采用冗余编号
公开(公告)号：US08665034B2
公开(公告)日：2014-03-04
申请号：US13245409
申请日：2011-09-26
申请人： Herschel A. Ainspan , Daniel J. Friedman , Alexander V. Rylyakov , Jose A. Tierno
发明人： Herschel A. Ainspan , Daniel J. Friedman , Alexander V. Rylyakov , Jose A. Tierno
IPC分类号： H03B5/08
CPC分类号： H03L7/099 , H03L2207/50
摘要： Techniques for improved tuning control of varactor circuits are disclosed. For example, an apparatus comprises a plurality of varactors for tuning a frequency value. The plurality of varactors comprises approximately sqrt(2N) varactors, where N is a number of tuning steps and the plurality of varactors are respectively sized as 1x, 2x, 3x, 4x, . . . , approximately sqrt(2N)x, and where x is a unit of capacitance. A given one of the N tuning steps may be represented by more than one combination of varactors. This may be referred to as redundant numbering.
摘要翻译：公开了用于改进变容二极管电路调谐控制的技术。例如，一种装置包括用于调谐频率值的多个变容二极管。多个变容二极管包括大约sqrt（2N）变容二极管，其中N是多个调谐步骤，并且多个变容二极管的尺寸分别为1x，2x，3x，4x。。。，约为sqrt（2N）x，其中x为电容单位。 N个调谐步骤中的给定一个可以由多个组合的变容二极管表示。这可以称为冗余编号。

68. 发明授权

US08429107B2 System for address-event-representation network simulation 有权
标题翻译：地址事件表示网络仿真系统
公开(公告)号：US08429107B2
公开(公告)日：2013-04-23
申请号：US12611968
申请日：2009-11-04
申请人： Monty M. Denneau , Daniel J. Friedman , Ralph Linsker , Mark B. Ritter
发明人： Monty M. Denneau , Daniel J. Friedman , Ralph Linsker , Mark B. Ritter
IPC分类号： G06F15/18 , G06N3/08
CPC分类号： H04L47/521
摘要： A system, method, and design structure for address-event-representation network simulation are provided. The system includes a hardware structure with a plurality of interconnected processing modules configured to simulate a plurality of interconnected nodes. To simulate each node, the hardware structure includes a source table configured to receive an input message and identify a weight associated with a source of the input message. The hardware structure also includes state management logic configured to update a node state as a function of the identified weight, and generate an output signal responsive to the updated node state. The hardware structure further includes a target table configured to generate an output message in response to the output signal, identify a target to receive the output message, and transmit the output message. The hardware structure may further include learning logic configured to combine information about input messages and generated output signals, and to update weights.
摘要翻译：提供了一种用于地址事件表示网络仿真的系统，方法和设计结构。该系统包括硬件结构，其具有被配置为模拟多个互连节点的多个互连的处理模块。为了模拟每个节点，硬件结构包括被配置为接收输入消息并且识别与输入消息的源相关联的权重的源表。硬件结构还包括状态管理逻辑，其被配置为根据所识别的权重更新节点状态，并响应于更新的节点状态生成输出信号。硬件结构进一步包括目标表，其被配置为响应于输出信号产生输出消息，识别目标以接收输出消息，并发送输出消息。硬件结构还可以包括被配置为组合关于输入消息和生成的输出信号的信息并且更新权重的学习逻辑。

69. 发明授权

US08222936B2 Phase and frequency detector with output proportional to frequency difference 有权
标题翻译：相位和频率检测器，输出与频率差成比例
公开(公告)号：US08222936B2
公开(公告)日：2012-07-17
申请号：US12813828
申请日：2010-06-11
申请人： Daniel J. Friedman , Alexander V. Rylyakov , José A. Tierno
发明人： Daniel J. Friedman , Alexander V. Rylyakov , José A. Tierno
IPC分类号： H03L7/06
CPC分类号： H03L7/089 , H03L7/093 , H03L7/1077 , H03L7/1976
摘要： Phase and frequency detectors and techniques are disclosed. For example, apparatus comprises a first circuit for receiving first and second clock signals and for generating at least one signal indicative of a phase difference between the first and second clock signals. The apparatus also comprises a second circuit for receiving the at least one signal generated by the first circuit and, in response to the at least one received signal, generating at least one output signal, wherein a frequency associated with the at least one output signal is proportional to a frequency difference between the first and second clock signals.
摘要翻译：公开了相位和频率检测器和技术。例如，装置包括用于接收第一和第二时钟信号的第一电路，以及用于产生指示第一和第二时钟信号之间的相位差的至少一个信号。该装置还包括第二电路，用于接收由第一电路产生的至少一个信号，并响应于该至少一个接收信号，产生至少一个输出信号，其中与该至少一个输出信号相关的频率为与第一和第二时钟信号之间的频率差成比例。

70. 发明申请

US20120153910A1 DUAL-LOOP VOLTAGE REGULATOR ARCHITECTURE WITH HIGH DC ACCURACY AND FAST RESPONSE TIME 有权
标题翻译：具有高直流精度和快速响应时间的双环电压调节器架构
公开(公告)号：US20120153910A1
公开(公告)日：2012-06-21
申请号：US13213578
申请日：2011-08-19
申请人： John F. Bulzacchelli , Carrie E. Cox , Zeynep Toprak-Deniz , Daniel J. Friedman , Joseph A. Iadanza , Todd M. Rasmus
发明人： John F. Bulzacchelli , Carrie E. Cox , Zeynep Toprak-Deniz , Daniel J. Friedman , Joseph A. Iadanza , Todd M. Rasmus
IPC分类号： G05F1/10
CPC分类号： G05F1/575
摘要： Dual-loop voltage regulator circuits and methods in which a dual-loop voltage regulation framework is implemented with a first inner loop having a bang-bang voltage regulator to achieve nearly instantaneous response time, and a second outer loop, which is slower in operating speed than the first inner loop, to controllably adjust a trip point of the bang-bang voltage regulator to achieve high DC accuracy.
摘要翻译：双环路电压调节器电路和方法，其中使用具有爆轰电压调节器的第一内环实现双回路电压调节框架以实现几乎瞬时的响应时间，以及第二外环，其操作速度较慢比第一个内环，可控地调节砰砰电压调节器的跳闸点，以实现高直流精度。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式