专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

61. 发明授权

US07863960B2 Three-dimensional chip-stack synchronization 有权
标题翻译：三维芯片堆栈同步
公开(公告)号：US07863960B2
公开(公告)日：2011-01-04
申请号：US12432801
申请日：2009-04-30
申请人： Ping-Chuan Wang , Anthony R. Bonaccio , Jong-Ru Guo , Louis Lu-Chen Hsu
发明人： Ping-Chuan Wang , Anthony R. Bonaccio , Jong-Ru Guo , Louis Lu-Chen Hsu
IPC分类号： G06F1/04
CPC分类号： H03L7/099 , H03L7/18 , H03L7/22
摘要： A central reference clock is placed in a substantially middle chip of a 3-D chip-stack. The central reference clock is distributed to each child chip of the 3-D chip-stack, so that a plurality of clocks is generated for each individual chip in the 3-D-stack in a synchronous manner. A predetermined number of through-silicon-vias and on-chip wires are employed to form a delay element for each slave clock, ensuring that the clock generated for each child chip is substantially synchronized. Optionally, an on-chip clock trimming circuit is embedded for further precision tuning to eliminate local clock skews.
摘要翻译：中心参考时钟被放置在3-D芯片堆叠的基本上中间的芯片中。中心参考时钟被分配给3-D芯片组的每个子芯片，从而以同步的方式为3-D堆叠中的每个芯片生成多个时钟。采用预定数量的通硅通孔和片上导线来形成每个从时钟的延迟元件，确保为每个子芯片生成的时钟基本上同步。可选地，嵌入式片上时钟微调电路用于进一步精确调谐以消除本地时钟偏移。

62. 发明授权

US07755420B2 Intrinsic RC power distribution for noise filtering of analog supplies 失效
标题翻译：用于模拟电源噪声滤波的本征RC功率分配
公开(公告)号：US07755420B2
公开(公告)日：2010-07-13
申请号：US12196718
申请日：2008-08-22
申请人： Anthony R. Bonaccio , Hayden C. Cranford, Jr. , Joseph A. Iadanza , Sebastian T. Ventrone , Stephen D. Wyatt
发明人： Anthony R. Bonaccio , Hayden C. Cranford, Jr. , Joseph A. Iadanza , Sebastian T. Ventrone , Stephen D. Wyatt
IPC分类号： H03K5/00
CPC分类号： G05F1/46
摘要： Analog supply for an analog circuit and process for supplying an analog signal to an analog circuit. The analog supply includes a noise filter having a variable resistor, and a control device coupled to adjust the variable resistor. The control device is structured and arranged to set the resistance of the variable resistor to maximize noise filtering and optimize performance of the analog circuit.
摘要翻译：用于模拟电路的模拟电源和用于向模拟电路提供模拟信号的过程。模拟电源包括具有可变电阻器的噪声滤波器和耦合以调节可变电阻器的控制装置。控制装置被构造和布置成设置可变电阻器的电阻以最大化噪声滤波并优化模拟电路的性能。

63. 发明授权

US07501880B2 Body-biased enhanced precision current mirror 失效
标题翻译：车身偏置增强型精密电流镜
公开(公告)号：US07501880B2
公开(公告)日：2009-03-10
申请号：US10906628
申请日：2005-02-28
申请人： Anthony R. Bonaccio , Hayden C. Cranford, Jr.
发明人： Anthony R. Bonaccio , Hayden C. Cranford, Jr.
IPC分类号： G05F1/10
CPC分类号： G05F3/262
摘要： A body-biased enhanced current mirror circuit is disclosed wherein the body voltage of a current mirror device is adjusted to compensate for the effect of changes in the output voltage on the output current, increasing the output impedance. For each instance of the current mirror, this approach has the advantage of requiring no additional margin in operating voltage and of consuming no more circuit area than prior art current mirror designs. In addition, the body-biased enhanced current mirror circuit provides a stable reference current to output current ratio over a wide operating range. An auxiliary MOSFET current mirror device with the body connected to ground may be added in parallel with the body-biased current mirror device to eliminate a non-monotonicity of the current output.
摘要翻译：公开了体偏置增强电流镜电路，其中调整电流镜装置的体电压以补偿输出电压对输出电流的变化的影响，增加输出阻抗。对于电流镜的每个实例，这种方法的优点在于不需要额外的工作电压余量，并且消耗的电路面积比现有技术的电流镜设计更多。此外，体偏置增强电流镜电路在宽的工作范围内提供稳定的参考电流至输出电流比。可以将主体连接到地的辅助MOSFET电流镜装置与主体偏置电流镜装置并联，以消除电流输出的非单调性。

64. 发明申请

US20090033395A1 MULTIPLE SOURCE-SINGLE DRAIN FIELD EFFECT SEMICONDUCTOR DEVICE AND CIRCUIT 有权
标题翻译：多源单向漏磁场效应半导体器件与电路
公开(公告)号：US20090033395A1
公开(公告)日：2009-02-05
申请号：US11833538
申请日：2007-08-03
申请人： Wagdi W. Abadeer , Anthony R. Bonaccio , Joseph A. Iadanza
发明人： Wagdi W. Abadeer , Anthony R. Bonaccio , Joseph A. Iadanza
IPC分类号： H03H11/16 , H03H11/26
CPC分类号： H01L27/0705 , H01L21/823418
摘要： Disclosed are embodiments of a variable-delay field effect transistor (FET) having multiple source regions that can be individually and selectively biased to provide an electrical connection to a single drain region. Delay is a function of which of the multiple source regions is/are selectively biased as well as a function of gate resistance and capacitance. Such a variable-delay FET can be incorporated into a phase adjusting circuit, which uses gate propagation delays to selectively phase adjust an input signal. The phase adjusting circuit can be tuned by incorporating non-salicided resistances and additional capacitance at various positions on the gate structure. The phase adjusting circuit can further be modified into a phase adjusting mixer circuit that enables a phase adjusted signal to be combined with an additional signal.
摘要翻译：公开了具有多个源极区域的可变延迟场效应晶体管（FET）的实施例，其可被单独和选择性地偏置以提供到单个漏极区域的电连接。延迟是多个源极区域中的哪一个被选择性偏置以及栅极电阻和电容的函数的函数。这样的可变延迟FET可以并入相位调整电路中，该相位调整电路使用栅极传播延迟来选择性地相位调整输入信号。相位调整电路可以通过在栅极结构上的各个位置并入非水银电阻和附加电容来调节。相位调整电路可以进一步修改为使相位调整信号与附加信号组合的相位调整混频器电路。

65. 发明申请

US20090033389A1 MICRO-PHASE ADJUSTING AND MICRO-PHASE ADJUSTING MIXER CIRCUITS DESIGNED WITH STANDARD FIELD EFFECT TRANSISTOR STRUCTURES 审中-公开
标题翻译：具有标准场效应晶体管结构的微相调节和微相调节混频器电路
公开(公告)号：US20090033389A1
公开(公告)日：2009-02-05
申请号：US11833567
申请日：2007-08-03
申请人： Wagdi W. Abadeer , Anthony R. Bonaccio , Joseph A. Iadanza
发明人： Wagdi W. Abadeer , Anthony R. Bonaccio , Joseph A. Iadanza
IPC分类号： H03L7/00 , G06F17/50
CPC分类号： H03K5/06 , H03K2005/00052 , H03K2005/00058
摘要： Disclosed herein are embodiments of a programmable phase adjusting circuit, a programmable phase adjusting mixer circuit and design structures for these circuits. These circuits comprise a variable delay device connected between input and output nodes. The device includes multiple FETs with input diffusion regions that are connected to a voltage rail via switches so that they can be selectively biased, gates that are connected in series to the input node so that a periodic input signal can be propagated sequentially through each of the gates and output diffusion regions that are connected in parallel to the output node. A current source is connected between the output node and another voltage rail for biasing the output node when the variable delay device is off. The variable delay device enables a circuit in which small increments of selectable phase adjustments can be made to the periodic input signal as a function of propagation delay.
摘要翻译：这里公开了可编程相位调整电路，可编程相位调整混频器电路和这些电路的设计结构的实施例。这些电路包括连接在输入和输出节点之间的可变延迟器件。该器件包括多个FET，其输入扩散区通过开关连接到电压轨，使得它们可以被选择性偏置，与输入节点串联连接的栅极，使得周期性输入信号可以顺序地传播通过门和输出扩散区域并联连接到输出节点。当可变延迟装置关闭时，电流源连接在输出节点和另一个电压轨道之间，用于偏置输出节点。可变延迟装置使得能够作为传播延迟的函数对周期性输入信号进行可选相位调整的小增量的电路。

66. 发明申请

US20090024972A1 STRUCTURES OF POWERING ON INTEGRATED CIRCUIT 失效
标题翻译：集成电路供电结构
公开(公告)号：US20090024972A1
公开(公告)日：2009-01-22
申请号：US12163025
申请日：2008-06-27
申请人： Igor Arsovski , Anthony R. Bonaccio , Serafino Bueti , Hayden C. Cranford, Jr. , Joseph A. Iadanza , Todd E. Leonard , Hemen R. Shah , Pradeep Thiagarajan , Sebastian T. Ventrone
发明人： Igor Arsovski , Anthony R. Bonaccio , Serafino Bueti , Hayden C. Cranford, Jr. , Joseph A. Iadanza , Todd E. Leonard , Hemen R. Shah , Pradeep Thiagarajan , Sebastian T. Ventrone
IPC分类号： G06F17/50
CPC分类号： G06F1/206 , Y02D10/16 , Y10T307/773
摘要： Design structures, method and systems of powering on an integrated circuit (IC) are disclosed. In one embodiment, the system includes a region in the IC including functional logic, a temperature sensor for sensing a temperature in the region when the IC is powered up and a heating element therefor; a processing unit including: a comparator for comparing the temperature against a predetermined temperature value, a controller, which in the case that the temperature is below the predetermined temperature value, delays functional operation of the IC and controls heating of the region of the IC, and a monitor for monitoring the temperature in the region; and wherein the controller, in the case that the temperature rises above the predetermined temperature value, ceases the heating and initiates functional operation of the IC.
摘要翻译：公开了对集成电路（IC）供电的设计结构，方法和系统。在一个实施例中，该系统包括IC中的包括功能逻辑的区域，用于感测IC上电时该区域中的温度的温度传感器及其加热元件; 处理单元，包括：用于将温度与预定温度值进行比较的比较器，在温度低于预定温度值的情况下的控制器，延迟IC的功能操作并控制IC的区域的加热，以及监测该区域的温度的监测器; 并且其中所述控制器在所述温度升高到所述预定温度值以上的情况下停止所述加热并且启动所述IC的功能操作。

67. 发明申请

US20090021085A1 DESIGN STRUCTURES, METHOD AND SYSTEMS OF POWERING ON INTEGRATED CIRCUIT 失效
标题翻译：集成电路供电的设计结构，方法和系统
公开(公告)号：US20090021085A1
公开(公告)日：2009-01-22
申请号：US11866537
申请日：2007-10-03
申请人： Igor Arsovski , Anthony R. Bonaccio , Serafino Bueti , Hayden C. Cranford, JR. , Joseph A. Iadanza , Todd E. Leonard , Hemen R. Shah , Pradeep Thiagarajan , Sebastian T. Ventrone
发明人： Igor Arsovski , Anthony R. Bonaccio , Serafino Bueti , Hayden C. Cranford, JR. , Joseph A. Iadanza , Todd E. Leonard , Hemen R. Shah , Pradeep Thiagarajan , Sebastian T. Ventrone
IPC分类号： H01H37/32
CPC分类号： G06F1/206 , Y02D10/16 , Y10T307/773
摘要： Design structures, method and systems of powering on an integrated circuit (IC) are disclosed. In one embodiment, the system includes a region in the IC including functional logic, a temperature sensor for sensing a temperature in the region when the IC is powered up and a heating element therefor; a processing unit including: a comparator for comparing the temperature against a predetermined temperature value, a controller, which in the case that the temperature is below the predetermined temperature value, delays functional operation of the IC and controls heating of the region of the IC, and a monitor for monitoring the temperature in the region; and wherein the controller, in the case that the temperature rises above the predetermined temperature value, ceases the heating and initiates functional operation of the IC.
摘要翻译：公开了对集成电路（IC）供电的设计结构，方法和系统。在一个实施例中，该系统包括IC中的包括功能逻辑的区域，用于感测IC上电时该区域中的温度的温度传感器及其加热元件; 处理单元，包括：用于将温度与预定温度值进行比较的比较器，在温度低于预定温度值的情况下的控制器，延迟IC的功能操作并控制IC的区域的加热，以及监测该区域的温度的监测器; 并且其中所述控制器在所述温度升高到所述预定温度值以上的情况下停止所述加热并且启动所述IC的功能操作。

68. 发明申请

US20080186051A1 FLEXIBLE MULTIMODE LOGIC ELEMENT FOR USE IN A CONFIGURABLE MIXED-LOGIC SIGNAL DISTRIBUTION PATH 有权
标题翻译：用于可配置混合逻辑信号分配路径的灵活多模态逻辑单元
公开(公告)号：US20080186051A1
公开(公告)日：2008-08-07
申请号：US11670537
申请日：2007-02-02
申请人： Igor Arsovski , Anthony R. Bonaccio , Hayden C. Cranford , Joseph A. Iadanza , Pradeep Thiagarajan , Sebastian T. Ventrone
发明人： Igor Arsovski , Anthony R. Bonaccio , Hayden C. Cranford , Joseph A. Iadanza , Pradeep Thiagarajan , Sebastian T. Ventrone
IPC分类号： H03K19/094
CPC分类号： H03K19/018585 , H03K3/35613 , H03K5/133 , H03K2005/00058 , H03K2005/00208 , H03K2005/00228
摘要： A multimode circuit that is configured to operate in one of multiple operating modes is disclosed. In particular, an exemplary multimode circuit may be configured to operating in one of a full-swing mode, a limited-swing mode, a full-swing to limited-swing converter mode, and a limited-swing to full-swing converter mode. The operating modes of the multimode circuit may be dynamically selectable. One or more multimode circuits may be part of a configurable distribution path for controlling the performance of a signal distribution path or tree of an integrated circuit.
摘要翻译：公开了一种被配置为以多种操作模式之一操作的多模电路。特别地，示例性多模电路可以被配置为以全摆动模式，限制摆动模式，全摆幅至限定摆动转换器模式和限定摆动至全摆幅转换器模式之一进行操作。多模电路的工作模式可以动态地选择。一个或多个多模电路可以是用于控制集成电路的信号分配路径或树的性能的可配置分配路径的一部分。

69. 发明申请

US20080069278A1 Asynchronous Phase Rotator Control 审中-公开
标题翻译：异步相位转子控制
公开(公告)号：US20080069278A1
公开(公告)日：2008-03-20
申请号：US11533105
申请日：2006-09-19
申请人： Steven J. Baumgartner , Anthony R. Bonaccio , Timothy C. Buchholtz , Charles P. Geer
发明人： Steven J. Baumgartner , Anthony R. Bonaccio , Timothy C. Buchholtz , Charles P. Geer
IPC分类号： H04L7/00
CPC分类号： H04L7/0337
摘要： The present invention generally relates to centering a clock edge at or near the center of a data eye. Data may be sent from a first device to a second device in conjunction with a clock signal. A phase rotator operating in an external clock domain governed by the clock signal received at the second device may rotate the phase of the received clock signal to sample data. The data sampled in the unstable external clock domain may be transferred to a stable local clock domain for analysis. Feedback may be provided from the stable clock domain to the phase rotator to adjust the phase of the received clock signal to position an edge of the clock signal at or near the center of the data eye.
摘要翻译：本发明一般地涉及使数据眼的中心处或附近的时钟沿居中。数据可以与时钟信号一起从第一设备发送到第二设备。在由在第二设备处接收的时钟信号控制的外部时钟域中工作的相位旋转器可将接收的时钟信号的相位旋转为采样数据。在不稳定的外部时钟域中采样的数据可能被传送到稳定的本地时钟域进行分析。可以从稳定时钟域向相位旋转器提供反馈以调整接收的时钟信号的相位，以将时钟信号的边沿定位在数据眼的中心处或附近。

70. 发明授权

US07268632B2 Structure and method for providing gate leakage isolation locally within analog circuits 失效
标题翻译：在模拟电路中局部提供栅极泄漏隔离的结构和方法
公开(公告)号：US07268632B2
公开(公告)日：2007-09-11
申请号：US11163013
申请日：2005-09-30
申请人： Anthony R. Bonaccio , Hayden C. Cranford, Jr. , Joseph A. Iadanza , Stephen D. Wyatt
发明人： Anthony R. Bonaccio , Hayden C. Cranford, Jr. , Joseph A. Iadanza , Stephen D. Wyatt
IPC分类号： H03L7/00 , H03L7/099 , H03B5/18
CPC分类号： H03L7/093 , H03L7/0891
摘要： A loop filter for a phase-locked-loop is provided, comprising a set of capacitor banks coupled in parallel to form the loop filter, and a detection circuit for identifying and isolating defective capacitor banks. A method for providing a loop filter for a phase-locked-loop in accordance with an embodiment of the present invention includes the steps of forming the loop filter using a set of capacitor banks coupled in parallel, detecting any defective capacitor banks in the set of capacitor banks, isolating each defective capacitor bank, providing a set of redundant capacitor banks, and replacing each defective capacitor bank with a redundant capacitor bank from the set of redundant capacitor banks.
摘要翻译：提供了一种用于锁相环的环路滤波器，包括并联耦合以形成环路滤波器的一组电容器组，以及用于识别和隔离有缺陷的电容器组的检测电路。根据本发明实施例的用于提供用于锁相环的环路滤波器的方法包括以下步骤：使用并联耦合的一组电容器组形成环路滤波器，检测该组中的任何有缺陷的电容器组电容器组，隔离每个有缺陷的电容器组，提供一组冗余电容器组，并从冗余电容器组组中的冗余电容器组替换每个有缺陷的电容器组。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式