专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

61. 发明授权

US06633920B1 Method and system for network data flow management with improved completion unit 失效
标题翻译：网络数据流管理方法与系统改进完成单元
公开(公告)号：US06633920B1
公开(公告)日：2003-10-14
申请号：US09479028
申请日：2000-01-07
申请人： Brian Mitchell Bass , Jean Louis Calvignac , Marco C. Heddes , Steven Kenneth Jenkins , Michael Steven Siegel , Fabrice Jean Verplanken
发明人： Brian Mitchell Bass , Jean Louis Calvignac , Marco C. Heddes , Steven Kenneth Jenkins , Michael Steven Siegel , Fabrice Jean Verplanken
IPC分类号： G06F1300
CPC分类号： H04L29/06 , H04L69/18 , H04L69/22
摘要： A system and method of data flow management, particularly in a multiple network processor architecture where a plurality of independent processing units are simultaneously processing information from different frames of input information. The present invention includes first-in-first-out files identifying the individual frames and correlating the frames with the processor to which the frames have been assigned for processing as well as a first-in-first-out file of processed frames for each processor to allow the frames to be processed independently, then reassembled into the same order as the frames had been received without communication between the independent processors. Additionally, the present system supports newly-created frames as well as the concept of flushing the system without regard to frame order whereby frames are sent out to the network as the processing is completed without regard to input order, overriding the system of putting the output frames in the same order as the input frames were received from the network.
摘要翻译：特别是在多个独立处理单元同时处理来自不同输入信息帧的信息的多网络处理器架构中的数据流管理系统和方法。本发明包括识别各个帧的先进先出文件，并且将帧与已被分配帧进行处理的处理器相关联，以及每个处理器的处理帧的先进先出文件以允许帧被独立地处理，然后重新组装成与已经被接收的帧相同的顺序，而没有独立处理器之间的通信。此外，本系统支持新创建的帧以及刷新系统的概念，而不考虑帧顺序，由此在不考虑输入顺序的情况下处理完成而将帧发送到网络，覆盖输出的系统与从网络接收输入帧相同顺序的帧。

62. 发明授权

US06584518B1 Cycle saving technique for managing linked lists 失效
标题翻译：用于管理链表的循环保存技术
公开(公告)号：US06584518B1
公开(公告)日：2003-06-24
申请号：US09479751
申请日：2000-01-07
申请人： Brian Mitchell Bass , Jean Louis Calvignac , Marco C. Heddes , Michael Steven Siegel , Michael Raymond Trombley , Fabrice Jean Verplanken
发明人： Brian Mitchell Bass , Jean Louis Calvignac , Marco C. Heddes , Michael Steven Siegel , Michael Raymond Trombley , Fabrice Jean Verplanken
IPC分类号： G06F1314
CPC分类号： G06F12/023
摘要： A method and system for queueing data within a data storage device including a set of storage blocks each having an address, a pointer field, and a data field. This set of storage blocks comprises a linked list of associated storage blocks and also a free pool of available storage blocks. The storage device further includes a tail register for tracking an empty tail block from which a data object is enqueued into the linked list. A request to enqueue a data object into the linked list is received within the data storage system. In response to the data enqueue request, an available storage block from the free pool is selected and associated with the tail register. A single write operation is then required to write the data object into the data field of a current tail block and to write the address of the selected storage block into the pointer field of the current tail block, such that the selected storage block becomes a new tail block to which the tail register points.
摘要翻译：一种用于在数据存储设备内排队数据的方法和系统，包括一组存储块，每个存储块具有地址，指针字段和数据字段。这组存储块包括相关联的存储块的链表以及可用存储块的空闲池。存储装置还包括用于跟踪空尾部块的尾部寄存器，数据对象从该尾部块排入链接列表。在数据存储系统内接收到将数据对象排入链表的请求。响应于数据排入请求，从空闲池中选择一个可用的存储块并将其与尾部寄存器相关联。然后需要单个写入操作来将数据对象写入当前尾部块的数据字段，并将所选择的存储块的地址写入当前尾部块的指针字段，使得所选择的存储块变为新的尾部寄存器指向的尾部块。

63. 发明授权

US06473838B1 Data transfer system for multiple network processors using dual DRAM storage 失效
标题翻译：使用双DRAM存储的多个网络处理器的数据传输系统
公开(公告)号：US06473838B1
公开(公告)日：2002-10-29
申请号：US09477576
申请日：2000-01-04
申请人： Brian Mitchell Bass , Jean Louis Calvignac , Marco C. Heddes , Steven Kenneth Jenkins , Michael Steven Siegel , Michael Raymond Trombley , Fabrice Jean Verplanken
发明人： Brian Mitchell Bass , Jean Louis Calvignac , Marco C. Heddes , Steven Kenneth Jenkins , Michael Steven Siegel , Michael Raymond Trombley , Fabrice Jean Verplanken
IPC分类号： G06F1200
CPC分类号： G06F13/1647 , G06F15/167
摘要： The ability of network processors to move data to and from dynamic random access memory (DRAM) chips used in computer systems is enhanced in several respects. In one aspect of the invention, two double data rate DRAMS are used in parallel to double the bandwidth for increased throughput of data. The movement of data is further improved by setting 4 banks of full ‘read’ and 4 banks of full ‘write’ by the network processor for every repetition of the DRAM time clock. A scheme for randomized ‘read’ and ‘write’ access by the network processor is disclosed. This scheme is particularly applicable to networks such as Ethernet that utilize variable frame sizes.
摘要翻译：网络处理器在计算机系统中使用的动态随机存取存储器（DRAM）芯片中移动数据的能力在几个方面得到了增强。在本发明的一个方面，并行使用两个双数据速率DRAMS以使带宽增加一倍以增加数据吞吐量。数据的移动通过为DRAM时钟的每次重复通过网络处理器设置4组完整“读”和4组完整“写”来进一步改进。公开了一种由网络处理器进行随机“读取”和“写入”访问的方案。该方案特别适用于利用可变帧大小的诸如以太网的网络。

64. 发明授权

US06404752B1 Network switch using network processor and methods 失效
标题翻译：网络交换机采用网络处理器和方法
公开(公告)号：US06404752B1
公开(公告)日：2002-06-11
申请号：US09384747
申请日：1999-08-27
申请人： James Johnson Allen, Jr. , Brian Mitchell Bass , Jean Louis Calvignac , Santosh Prasad Gaur , Marco C. Heddes , Michael Steven Siegel , Fabrice Jean Verplanken
发明人： James Johnson Allen, Jr. , Brian Mitchell Bass , Jean Louis Calvignac , Santosh Prasad Gaur , Marco C. Heddes , Michael Steven Siegel , Fabrice Jean Verplanken
IPC分类号： H04L1228
CPC分类号： H04Q3/002 , H04L45/742 , H04L49/254 , H04L49/351 , H04L49/354 , H04L49/602 , H04L2212/00 , H04Q3/5455 , H04Q2213/1302 , H04Q2213/13034 , H04Q2213/1304 , H04Q2213/13103 , H04Q2213/13104 , H04Q2213/13106 , H04Q2213/13107 , H04Q2213/13322
摘要： A network switch apparatus, components for such an apparatus, and methods of operating such an apparatus in which data flow handling and flexibility is enhanced by the cooperation among a plurality of interface processors and a suite of peripheral elements formed on a semiconductor substrate. The interface processors and peripherals together form a network processor capable of cooperating with other elements including an optional switching fabric device in executing instructions directing the flow of data in a network.
摘要翻译：一种网络交换设备，用于这种设备的部件，以及操作这样一种设备的方法，其中通过多个接口处理器和形成在半导体衬底上的一组外围元件之间的协作来增强数据流处理和灵活性。接口处理器和外围设备一起形成一个网络处理器，能够在执行指导网络中的数据流的指令的情况下与包括可选的交换结构设备在内的其他元件进行协作。

65. 发明授权

US07984038B2 Longest prefix match (LPM) algorithm implementation for a network processor 失效
标题翻译：用于网络处理器的最长前缀匹配（LPM）算法实现
公开(公告)号：US07984038B2
公开(公告)日：2011-07-19
申请号：US12103140
申请日：2008-04-15
申请人： Brian Mitchell Bass , Jean Louis Calvignac , Marco C. Heddes , Antonios Maragkos , Piyush Chunilal Patel , Michael Steven Siegel , Fabrice Jean Verplanken
发明人： Brian Mitchell Bass , Jean Louis Calvignac , Marco C. Heddes , Antonios Maragkos , Piyush Chunilal Patel , Michael Steven Siegel , Fabrice Jean Verplanken
IPC分类号： G06F17/30
CPC分类号： G06F17/30985 , H04L45/7457 , Y10S707/99931 , Y10S707/99933 , Y10S707/99936 , Y10S707/99942 , Y10S707/99943 , Y10S707/99945
摘要： Novel data structures, methods and apparatus for finding the longest prefix match search when searching tables with variable length patterns or prefixes. To find the exact match or the best matching prefix, patterns have to be compared a bit at a time until the exact or first match is found. This requires “n” number of comparisons or memory accesses to identify the closest matching pattern. The trees are built in such a way that the matching result is guaranteed to be a best match, whether it is an exact match or a longest prefix match. Using the trail of all the birds and associated prefix lengths enables determination of the correct prefix result from the trail. By construction, the search tree provides the best matching prefix at or after the first compare during walking of the trail or tree.
摘要翻译：当搜索具有可变长度模式或前缀的表时，用于查找最长前缀的新型数据结构，方法和装置匹配搜索。要找到完全匹配或最匹配的前缀，模式必须一次比较一下，直到发现确切或第一个匹配。这需要“n”个比较或存储器访问来识别最接近的匹配模式。树的建立方式使得匹配结果保证是最佳匹配，无论是完全匹配还是最长匹配前缀。使用所有鸟的踪迹和相关的前缀长度可以确定路线中正确的前缀结果。通过构建，搜索树在步道或树的步行期间在第一次比较之前或之后提供最佳的匹配前缀。

66. 发明申请

US20080222116A1 LONGEST PREFIX MATCH (LPM) ALGORITHM IMPLEMENTATION FOR A NETWORK PROCESSOR 失效
标题翻译：用于网络处理器的最大前缀匹配（LPM）算法实现
公开(公告)号：US20080222116A1
公开(公告)日：2008-09-11
申请号：US12103140
申请日：2008-04-15
申请人： Brian Mitchell Bass , Jean Louis Calvignac , Marco C. Heddes , Antonios Maragkos , Piyush Chunilal Patel , Michael Steven Siegel , Fabrice Jean Verplanken
发明人： Brian Mitchell Bass , Jean Louis Calvignac , Marco C. Heddes , Antonios Maragkos , Piyush Chunilal Patel , Michael Steven Siegel , Fabrice Jean Verplanken
IPC分类号： G06F17/30
CPC分类号： G06F17/30985 , H04L45/7457 , Y10S707/99931 , Y10S707/99933 , Y10S707/99936 , Y10S707/99942 , Y10S707/99943 , Y10S707/99945
摘要： Novel data structures, methods and apparatus for finding the longest prefix match search when searching tables with variable length patterns or prefixes. To find the exact match or the best matching prefix, patterns have to be compared a bit at a time until the exact or first match is found. This requires “n” number of comparisons or memory accesses to identify the closest matching pattern. The trees are built in such a way that the matching result is guaranteed to be a best match, whether it is an exact match or a longest prefix match. Using the trail of all the birds and associated prefix lengths enables determination of the correct prefix result from the trail. By construction, the search tree provides the best matching prefix at or after the first compare during walking of the trail or tree.
摘要翻译：当搜索具有可变长度模式或前缀的表时，用于查找最长前缀的新型数据结构，方法和装置匹配搜索。要找到完全匹配或最匹配的前缀，模式必须一次比较一下，直到发现确切或第一个匹配。这需要“n”个比较或存储器访问来识别最接近的匹配模式。树的建立方式使得匹配结果保证是最佳匹配，无论是完全匹配还是最长匹配前缀。使用所有鸟的踪迹和相关的前缀长度可以确定路线中正确的前缀结果。通过构建，搜索树在步道或树的步行期间在第一次比较之前或之后提供最佳的匹配前缀。

67. 发明授权

US06985431B1 Network switch and components and method of operation 有权
标题翻译：网络交换机及组件及操作方法
公开(公告)号：US06985431B1
公开(公告)日：2006-01-10
申请号：US09384692
申请日：1999-08-27
申请人： Brian Mitchell Bass , Jean Louis Calvignac , Anthony Matteo Gallo , Marco C. Heddes , Sridhar Rao , Michael Steven Siegel , Fabrice Jean Verplanken , Brian Alan Youngman
发明人： Brian Mitchell Bass , Jean Louis Calvignac , Anthony Matteo Gallo , Marco C. Heddes , Sridhar Rao , Michael Steven Siegel , Fabrice Jean Verplanken , Brian Alan Youngman
IPC分类号： H04Q11/04
CPC分类号： H04L49/3036 , G06F13/4022 , H04L49/15 , H04L49/205 , H04L49/3009 , H04L49/351
摘要： A network switch apparatus, components for such an apparatus, and methods of operating such an apparatus in which data flow handling and flexibility is enhanced by the cooperation of a control point and a plurality of interface processors formed on a semiconductor substrate. The control point and interface processors together form a network processor capable of cooperating with other elements including an optional switching fabric device in executing instructions directing the flow of data in a network.
摘要翻译：一种网络交换装置，这种装置的组件，以及操作这样的装置的方法，其中通过控制点和形成在半导体衬底上的多个接口处理器的协作来增强数据流处理和灵活性。控制点和接口处理器一起形成一个网络处理器，能够在执行指导网络中的数据流的指令的情况下与包括可选交换结构设备在内的其他元件协作。

68. 发明授权

US06766381B1 VLSI network processor and methods 失效
标题翻译： VLSI网络处理器和方法
公开(公告)号：US06766381B1
公开(公告)日：2004-07-20
申请号：US09384689
申请日：1999-08-27
申请人： Kenneth James Barker , Brian Mitchell Bass , Jean Louis Calvignac , Marco C. Heddes , Michael Steven Siegel , Michael Raymond Trombley , Fabrice Jean Verplanken
发明人： Kenneth James Barker , Brian Mitchell Bass , Jean Louis Calvignac , Marco C. Heddes , Michael Steven Siegel , Michael Raymond Trombley , Fabrice Jean Verplanken
IPC分类号： G06F1516
CPC分类号： H04L29/06 , H04L49/1507 , H04L49/45 , H04L69/12
摘要： A network processor useful in network switch apparatus and methods of operating such a processor in which data flow handling and flexibility is enhanced by the cooperation of a plurality of interface processors formed on a semiconductor substrate. The interface processors provide data paths for inbound and outbound data flow and operate under the control of instructions stored in an instruction store formed on the semiconductor substrate.
摘要翻译：可用于网络交换设备的网络处理器和操作这样的处理器的方法，其中通过形成在半导体衬底上的多个接口处理器的协作来增强数据流处理和灵活性。接口处理器提供用于入站和出站数据流的数据路径，并且在存储在形成在半导体衬底上的指令存储器中的指令的控制下操作。

69. 发明授权

US06675163B1 Full match (FM) search algorithm implementation for a network processor 失效
标题翻译：网络处理器的完全匹配（FM）搜索算法实现
公开(公告)号：US06675163B1
公开(公告)日：2004-01-06
申请号：US09543531
申请日：2000-04-06
申请人： Brian Mitchell Bass , Jean Louis Calvignac , Marco C. Heddes , Antonios Maragkos , Piyush Chunilal Patel , Michael Steven Siegel , Fabrice Jean Verplanken
发明人： Brian Mitchell Bass , Jean Louis Calvignac , Marco C. Heddes , Antonios Maragkos , Piyush Chunilal Patel , Michael Steven Siegel , Fabrice Jean Verplanken
IPC分类号： G06F1730
CPC分类号： H04L45/742 , H04L45/7453 , Y10S707/99933 , Y10S707/99934 , Y10S707/99935 , Y10S707/99936 , Y10S707/99937 , Y10S707/99943 , Y10S707/99945
摘要： Novel data structures, methods and apparatus for finding a full match between a search pattern and a pattern stored in a leaf of the search tree. A key is input, a hash function is performed on the key, a direct table (DT) is accessed, and a tree is walked through pattern search control blocks (PSCBs) until reaching a leaf. The search mechanism uses a set of data structures that can be located in a few registers and regular memory, and then used to build a Patricia tree structure that can be manipulated by a relatively simple hardware macro. Both keys and corresponding information needed for retrieval are stored in the Patricia tree structure. The hash function provides an n→n mapping of the bits of the key to the bits of the hash key. The data structure that is used to store the hash key and the related information in the tree is called a leaf. Each leaf corresponds to a single key that matches exactly with the input key. The leaf contains the key as well as additional information. The length of the leaf is programmable, as is the length of the key. The leaf is stored in random access memory and is implemented as a single memory entry. If the key is located in the direct table then it is called a direct leaf.
摘要翻译：用于在搜索图案和存储在搜索树的叶中的模式之间找到完全匹配的新型数据结构，方法和装置。键输入，对密钥执行哈希函数，访问直接表（DT），并通过模式搜索控制块（PSCB），树直到达到叶。搜索机制使用一组可以位于几个寄存器和常规内存中的数据结构，然后用于构建可由相对简单的硬件宏操作的Patricia树结构。检索所需的两个密钥和相应的信息都存储在Patricia树结构中。散列函数提供密钥的比特到散列密钥的比特的n> n映射。用于存储散列键和树中相关信息的数据结构称为叶。每个叶对应于与输入键完全匹配的单个键。叶包含关键以及其他信息。叶片的长度是可编程的，密钥的长度也是可编程的。叶存储在随机存取存储器中，并被实现为单个存储器条目。如果键位于直接表中，则称为直接叶。

70. 发明授权

US07315901B1 Method and system for network processor scheduling outputs using disconnect/reconnect flow queues 失效
标题翻译：使用断开/重新连接流队列的网络处理器调度输出的方法和系统
公开(公告)号：US07315901B1
公开(公告)日：2008-01-01
申请号：US09548913
申请日：2000-04-13
申请人： Brian Mitchell Bass , Jean Louis Calvignac , Marco C. Heddes , Michael Steven Siegel , Fabrice Jean Verplanken
发明人： Brian Mitchell Bass , Jean Louis Calvignac , Marco C. Heddes , Michael Steven Siegel , Fabrice Jean Verplanken
IPC分类号： G06F15/173 , H04L12/24
CPC分类号： H04L47/522 , H04L47/2425 , H04L47/50 , H04L47/568 , H04L47/58 , H04L47/6235 , H04L47/6265
摘要： A system and method of moving information units from a network processor toward a data transmission network in a prioritized sequence which accommodates several different levels of service. The present invention includes a method and system for scheduling the egress of processed information units (or frames) from a network processing unit according to stored priorities associated with the various sources of the information units. A system for allowing peak bursts based on a system of credits and charges is taught along limits on such peak bursts. Also taught is a system for preventing a flow's disconnection and reconnection to the queues from allowing it to unfairly achieve an improved position.
摘要翻译：一种将信息单元从网络处理器移动到数据传输网络的系统和方法，其以容纳几个不同级别的服务的优先顺序排列。本发明包括一种方法和系统，用于根据存储的与信息单元的各种源相关联的优先级来调度来自网络处理单元的处理的信息单元（或帧）的出口。根据这种峰值突发的限制，教导了基于信用和费用系统允许峰值突发的系统。还教导了一种用于防止流动断开和重新连接到队列的系统，从而允许其不公平地实现改进的位置。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式