专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

61. 发明申请

US20050077629A1 Photoresist ash process with reduced inter-level dielectric ( ILD) damage 审中-公开
标题翻译：具有降低的层间电介质（ILD）损伤的光刻胶灰工艺
公开(公告)号：US20050077629A1
公开(公告)日：2005-04-14
申请号：US10685012
申请日：2003-10-14
申请人： Timothy Dalton , Nicholas Fuller , Kaushik Kumar
发明人： Timothy Dalton , Nicholas Fuller , Kaushik Kumar
IPC分类号： H01L21/768 , H01L23/532 , H01L23/48
CPC分类号： H01L21/76802 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： Novel interconnect structures possessing an organosilicate dielectric material with unaltered physical and chemical properties post exposure to a specific resist ash chemistry for use in semiconductor devices are provided herein. The novel interconnect structure is capable of delivering improved device performance, functionality and reliability owing to the use of a chemically and physically “friendly” resist ash process. An in situ inert gas/H2 process achieves minimal chemical and physical reactivity with the organosilicate sidewalls during ashing owing to its inherent make up.
摘要翻译：本文提供了具有在暴露于用于半导体器件的特定抗蚀剂灰化学物质之后具有未改变的物理和化学性质的有机硅酸盐介电材料的新型互连结构。由于使用了化学和物理上“友好”的抗蚀灰工艺，新颖的互连结构能够提供改进的器件性能，功能和可靠性。原位惰性气体/ H2过程由于其固有的组成而在灰化过程中与有机硅酸盐侧壁产生最小的化学和物理反应性。

62. 发明申请

US20050064701A1 Formation of low resistance via contacts in interconnect structures 审中-公开
标题翻译：通过互连结构中的触点形成低电阻
公开(公告)号：US20050064701A1
公开(公告)日：2005-03-24
申请号：US10665584
申请日：2003-09-19
申请人： Timothy Dalton , Stephen Gates
发明人： Timothy Dalton , Stephen Gates
IPC分类号： H01L21/306 , H01L21/311 , H01L21/768 , H01L21/4763
CPC分类号： H01L21/02063 , H01L21/76814
摘要： A method of fabricating an interconnect structure including the steps of: forming a porous or dense low k dielectric layer on a substrate; forming single or dual damascene etched openings in the low k dielectric; placing the substrate in a process chamber on a cold chuck at a temperature about −200° C. to about 25° C.; adding to the process chamber a condensable cleaning agent (CCA) to condense a layer of CCA within the etched openings on the substrate; and activating at a temperature about −200° C. to about 25° C. Also provided is an interconnect structure having a substrate, a conductive material disposed on the substrate, a porous or dense low k dielectric layer disposed on the conductive material, wherein the low k dielectric layer has a single or dual damascene etched openings that expose a surface of the conductive material, and metallic lines and vias etched onto the low k dielectric layer; wherein the exposed conductive material has been treated with a CCA and activated in the cold to remove oxide, oxygen and carbon containing residues from the surface of the conductive material.
摘要翻译：一种制造互连结构的方法，包括以下步骤：在衬底上形成多孔或致密的低k电介质层; 在低k电介质中形成单或双镶嵌蚀刻孔; 将基板放置在温度约-200℃至约25℃的冷卡盘上的处理室中; 向处理室中加入可冷凝清洁剂（CCA），以在衬底上的蚀刻开口内冷凝CCA层; 并且在约-200℃至约25℃的温度下活化。还提供了具有基底，设置在基底上的导电材料，设置在导电材料上的多孔或致密的低k电介质层的互连结构，其中低k电介质层具有暴露导电材料的表面的单个或双镶嵌蚀刻开口以及蚀刻到低k电介质层上的金属线和通孔; 其中所述暴露的导电材料已经用CCA处理并且在冷中被活化以从所述导电材料的表面去除氧化物，含氧和碳的残余物。

63. 发明申请

US20120292741A1 INTERCONNECT STRUCTURES AND DESIGN STRUCTURES FOR A RADIOFREQUENCY INTEGRATED CIRCUIT 有权
标题翻译：无线电集成电路的互连结构和设计结构
公开(公告)号：US20120292741A1
公开(公告)日：2012-11-22
申请号：US13560446
申请日：2012-07-27
申请人： Timothy Dalton , Ebenezer E. Eshun , Sarah L. Grunow , Zhong-Xiang He , Anthony K. Stamper
发明人： Timothy Dalton , Ebenezer E. Eshun , Sarah L. Grunow , Zhong-Xiang He , Anthony K. Stamper
IPC分类号： H01L23/522 , G06F17/50
CPC分类号： H01L21/76885 , H01L21/76816 , H01L21/76832 , H01L21/76834 , H01L27/016 , H01L28/20 , H01L28/40
摘要： Interconnect structures that include a passive element, such as a thin film resistor or a metal-insulator-metal (MIM) capacitor, methods for fabricating an interconnect structure that includes a passive element, and design structures embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit, such as a radiofrequency integrated circuit. A top surface of a dielectric layer is recessed relative to a top surface of a conductive feature in the dielectric layer. The passive element is formed on the recessed top surface of the dielectric layer and includes a layer of a conductive material that is coplanar with, or below, the top surface of the conductive feature.
摘要翻译：包括诸如薄膜电阻器或金属 - 绝缘体 - 金属（MIM）电容器的无源元件的互连结构，用于制造包括无源元件的互连结构的方法，以及体现在机器可读介质中的设计结构，用于设计，制造或测试诸如射频集成电路的集成电路。电介质层的顶表面相对于电介质层中导电特征的顶表面凹陷。无源元件形成在介电层的凹入的顶表面上，并且包括与导电特征的顶表面共面或低于导电特征的顶表面的导电材料层。

64. 发明申请

US20100237467A1 Interconnect Structures, Methods for Fabricating Interconnect Structures, and Design Structures for a Radiofrequency Integrated Circuit 有权
标题翻译：互连结构，制造互连结构的方法和射频集成电路的设计结构
公开(公告)号：US20100237467A1
公开(公告)日：2010-09-23
申请号：US12634742
申请日：2009-12-10
申请人： Timothy Dalton , Ebenezer E. Eshun , Sarah L. Grunow , Zhong-Xiang He , Anthony K. Stamper
发明人： Timothy Dalton , Ebenezer E. Eshun , Sarah L. Grunow , Zhong-Xiang He , Anthony K. Stamper
IPC分类号： H01L29/86 , G06F17/50 , H01L21/768
CPC分类号： H01L21/76885 , H01L21/76816 , H01L21/76832 , H01L21/76834 , H01L27/016 , H01L28/20 , H01L28/40
摘要： Interconnect structures that include a passive element, such as a thin film resistor or a metal-insulator-metal (MIM) capacitor, methods for fabricating an interconnect structure that includes a passive element, and design structures embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit, such as a radiofrequency integrated circuit. A top surface of a dielectric layer is recessed relative to a top surface of a conductive feature in the dielectric layer. The passive element is formed on the recessed top surface of the dielectric layer and includes a layer of a conductive material that is coplanar with, or below, the top surface of the conductive feature.
摘要翻译：包括诸如薄膜电阻器或金属 - 绝缘体 - 金属（MIM）电容器的无源元件的互连结构，用于制造包括无源元件的互连结构的方法，以及体现在机器可读介质中的设计结构，用于设计，制造或测试诸如射频集成电路的集成电路。电介质层的顶表面相对于电介质层中导电特征的顶表面凹陷。无源元件形成在介电层的凹入的顶表面上，并且包括与导电特征的顶表面共面或低于导电特征的顶表面的导电材料层。

65. 发明申请

US20100044759A1 DOUBLE-SIDED INTEGRATED CIRCUIT CHIPS 有权
标题翻译：双面集成电路板
公开(公告)号：US20100044759A1
公开(公告)日：2010-02-25
申请号：US12612957
申请日：2009-11-05
申请人： Kerry Bernstein , Timothy Dalton , Jeffrey Peter Gambino , Mark David Jaffe , Paul David Kartschoke , Stephen Ellinwood Luce , Anthony Kendall Stamper
发明人： Kerry Bernstein , Timothy Dalton , Jeffrey Peter Gambino , Mark David Jaffe , Paul David Kartschoke , Stephen Ellinwood Luce , Anthony Kendall Stamper
IPC分类号： H01L29/786 , H01L21/18 , H01L21/768 , H01L23/48
CPC分类号： H01L25/0657 , H01L21/76895 , H01L23/481 , H01L23/522 , H01L23/5329 , H01L25/50 , H01L27/0688 , H01L2225/06513 , H01L2225/06527 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure and method of fabricating the structure. The method includes removing the backside silicon from two silicon-on-insulator wafers having devices fabricated therein and bonding them back to back utilizing the buried oxide layers. Contacts are then formed in the upper wafer to devices in the lower wafer and wiring levels are formed on the upper wafer. The lower wafer may include wiring levels. The lower wafer may include landing pads for the contacts. Contacts to the silicon layer of the lower wafer may be silicided.
摘要翻译：一种半导体结构及其制造方法。该方法包括从具有在其中制造的器件的两个绝缘体上硅晶片上去除背面硅，并利用掩埋氧化物层将它们背对背地接合。然后在上晶片中形成与下晶片中的器件接触，并在上晶片上形成布线层。下晶片可以包括布线水平。下部晶片可以包括用于触点的着陆焊盘。与下晶片的硅层的接触可以被硅化。

66. 发明申请

US20080083697A1 POROUS SILICON COMPOSITE STRUCTURE AS LARGE FILTRATION ARRAY 审中-公开
标题翻译：多孔硅复合结构作为大的过滤阵列
公开(公告)号：US20080083697A1
公开(公告)日：2008-04-10
申请号：US11872693
申请日：2007-10-15
申请人： Timothy Dalton , Michelle Steen
发明人： Timothy Dalton , Michelle Steen
IPC分类号： C23F1/00
CPC分类号： B01D67/0062 , B01D67/0034 , B01D67/0072 , B01D67/0079 , B01D69/10 , B01D69/12 , B01D71/02 , B01D71/64 , B01D71/68 , B01D2325/022 , B01D2325/08 , B01D2325/24
摘要： A novel asymmetric filter membrane, and process for making is disclosed in several exemplary versions. The membrane structure is physically robust and suitable for use in a wide variety of applications. The support membrane is may be comprised of material such as a porous silicon or a silicon oxide, and the separation membrane may be comprised of material such as a polymer, zeolite film, or silicon oxide. The process relies on steps adapted from the microelectronics industry.
摘要翻译：在几个示例性版本中公开了一种新型的不对称滤膜和制造方法。膜结构物理坚固，适用于各种应用。支撑膜可以由诸如多孔硅或氧化硅的材料构成，并且分离膜可以由诸如聚合物，沸石膜或氧化硅的材料构成。该过程依赖于微电子行业的改进。

67. 发明申请

US20080054393A1 METHODS OF FABRICATING PASSIVE ELEMENT WITHOUT PLANARIZING AND RELATED SEMICONDUCTOR DEVICE 有权
标题翻译：无平面化和相关半导体器件制造被动元件的方法
公开(公告)号：US20080054393A1
公开(公告)日：2008-03-06
申请号：US11928798
申请日：2007-10-30
申请人： Anil Chinthakindi , Timothy Dalton , Ebenezer Eshun , Jeffrey Gambino , Anthony Stamper , Kunal Vaed
发明人： Anil Chinthakindi , Timothy Dalton , Ebenezer Eshun , Jeffrey Gambino , Anthony Stamper , Kunal Vaed
IPC分类号： H01L29/00 , H01L21/02
CPC分类号： H01L21/76819 , H01L23/522 , H01L28/40 , H01L2924/0002 , H01L2924/00
摘要： Methods of fabricating a passive element and a semiconductor device including the passive element are disclosed including the use of a dummy passive element. A dummy passive element is a passive element or wire which is added to the chip layout to aid in planarization but is not used in the active circuit. One embodiment of the method includes forming the passive element and a dummy passive element adjacent to the passive element; forming a dielectric layer over the passive element and the dummy passive element, wherein the dielectric layer is substantially planar between the passive element and the dummy passive element; and forming in the dielectric layer an interconnect to the passive element through the dielectric layer and a dummy interconnect portion overlapping at least a portion of the dummy passive element. The methods eliminate the need for planarizing.
摘要翻译：公开了制造无源元件的方法和包括无源元件的半导体器件，其包括使用虚拟无源元件。虚拟无源元件是被添加到芯片布局以帮助平坦化但在有源电路中不使用的无源元件或线。该方法的一个实施例包括形成无源元件和邻近无源元件的虚拟无源元件; 在无源元件和虚拟无源元件上形成电介质层，其中介电层在无源元件和虚拟无源元件之间基本上是平面的; 并且在所述电介质层中形成通过所述介电层与所述无源元件的互连以及与所述虚拟无源元件的至少一部分重叠的虚拟互连部分。该方法消除了平面化的需要。

68. 发明申请

US20070267746A1 DUAL-SIDED CHIP ATTACHED MODULES 有权
标题翻译：双面芯片连接模块
公开(公告)号：US20070267746A1
公开(公告)日：2007-11-22
申请号：US11383595
申请日：2006-05-16
申请人： Kerry Bernstein , Timothy Dalton , Timothy Harrison Daubenspeck , Jeffrey Peter Gambino , Mark David Jaffe , Christopher David Muzzy , Wolfgang Sauter , Edmund Sprogis , Anthony Kendall Stamper
发明人： Kerry Bernstein , Timothy Dalton , Timothy Harrison Daubenspeck , Jeffrey Peter Gambino , Mark David Jaffe , Christopher David Muzzy , Wolfgang Sauter , Edmund Sprogis , Anthony Kendall Stamper
IPC分类号： H01L23/48 , H01L23/52
CPC分类号： H01L24/10 , H01L23/13 , H01L23/481 , H01L23/49833 , H01L23/5385 , H01L24/13 , H01L24/45 , H01L24/48 , H01L24/73 , H01L25/0652 , H01L25/0655 , H01L2224/13 , H01L2224/13099 , H01L2224/14181 , H01L2224/16225 , H01L2224/16235 , H01L2224/17181 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/73257 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/09701 , H01L2924/1305 , H01L2924/1306 , H01L2924/14 , H01L2924/15174 , H01L2924/15192 , H01L2924/15311 , H01L2924/15787 , H05K1/145 , H05K3/222 , H05K2201/10674 , Y10T436/171538 , Y10T436/172307 , H01L2924/00014 , H01L2924/00
摘要： An electronic device and method of packaging an electronic device. The device including: a first substrate, a second substrate and an integrated circuit chip having a first side and an opposite second side, a first set of chip pads on the first side and a second set of chip pads on the second side of the integrated circuit chip, chip pads of the first set of chip pads physically and electrically connected to corresponding substrate pads on the first substrate and chip pads of the second set of chip pads physically and electrically connected to substrate pads of the substrate.
摘要翻译：一种电子装置和包装电子装置的方法。该装置包括：第一基板，第二基板和具有第一侧和相对的第二侧的集成电路芯片，在第一侧上的第一组芯片焊盘和在集成的第二侧上的第二组芯片焊盘电路芯片，第一组芯片焊盘的芯片焊盘物理和电连接到第一衬底上的对应衬底焊盘，并且第二组芯片焊盘的芯片焊盘物理和电连接到衬底的衬底焊盘。

69. 发明申请

US20070257689A1 High density thermally matched contacting probe assembly and method for producing same 失效
标题翻译：高密度热匹配接触探针组件及其制造方法
公开(公告)号：US20070257689A1
公开(公告)日：2007-11-08
申请号：US11429419
申请日：2006-05-05
申请人： Timothy Dalton , Simon Karecki , Anna Karecki , Samuel Mcknight , George Walker
发明人： Timothy Dalton , Simon Karecki , Anna Karecki , Samuel Mcknight , George Walker
IPC分类号： G01R31/02
CPC分类号： G01R1/07371 , G01R3/00 , Y10T29/49117 , Y10T29/49204 , Y10T29/49208 , Y10T29/49217 , Y10T29/49995
摘要： A method to fabricate a high density, minimal pitch, thermally matched contactor assembly to maintain electrical contact with contact regions on fully processed semiconductors, preferably while still in wafer form, and throughout a range of temperatures. A guide plate and a contactor assembly for such use, comprising a substrate formed of a material having a coefficient of thermal expansion approximately equal to that of the device; and at least one hole in the guide plate for receiving an electrical contact (probe element) for contacting at least one respective region on said surface, said at least one hole being sized and shaped so as to accept said electrical contact, while allowing said electrical contact (probe element) to move with respect to said hole in said guide plate. The material can be one of silicon, borosilicate glass and cordierite.
摘要翻译：制造高密度，最小间距，热匹配的接触器组件的方法，以保持与完全处理的半导体上的接触区域的电接触，优选同时处于晶片形式，并且在整个温度范围内。一种用于这种用途的引导板和接触器组件，包括由具有大约等于该装置的热膨胀系数的材料形成的基底; 和引导板中的至少一个孔，用于接收用于接触所述表面上的至少一个相应区域的电接触（探针元件），所述至少一个孔的尺寸和形状被设计成接纳所述电接触，同时允许所述电气接触（探针元件）相对于所述引导板中的所述孔移动。该材料可以是硅，硼硅酸盐玻璃和堇青石中的一种。

70. 发明申请

US20070241424A1 VERTICAL PARALLEL PLATE CAPACITOR USING SPACER SHAPED ELECTRODES AND METHOD FOR FABRICATION THEREOF 有权
标题翻译：使用间隔型电极的垂直平行平板电容器及其制造方法
公开(公告)号：US20070241424A1
公开(公告)日：2007-10-18
申请号：US11279434
申请日：2006-04-12
申请人： Timothy Dalton , Jeffrey Gambino , Anthony Stamper
发明人： Timothy Dalton , Jeffrey Gambino , Anthony Stamper
IPC分类号： H01L29/00
CPC分类号： H01G4/33 , H01G4/236 , H01L28/91 , Y10T29/435
摘要： A capacitor structure uses an aperture located within a dielectric layer in turn located over a substrate. A pair of conductor interconnection layers embedded within the dielectric layer terminates at a pair of opposite sidewalks of the aperture. A pair of capacitor plates is located upon the pair of opposite sidewalks of the aperture and contacting the pair of conductor interconnection layers, but not filling the aperture. A capacitor dielectric layer is located interposed between the pair of capacitor plates and filling the aperture. The pair of capacitor plates may be formed using an anisotropic unmasked etch followed by a masked trim etch. Alternatively, the pair of capacitor plates may be formed using an unmasked anisotropic etch only, when the pair of opposite sidewalks of the aperture is vertical and separated by a second pair of opposite sidewalks that is outward sloped.
摘要翻译：电容器结构使用位于电介质层内的开口依次位于衬底上。嵌入电介质层内的一对导体互连层终止于孔的一对相对的人行道。一对电容器板位于孔的一对相对的人行道上，并接触一对导体互连层，但不填充孔。电容器介质层位于一对电容器板之间并填充孔。可以使用各向异性无掩模蚀刻，然后进行掩模修整蚀刻来形成该对电容器板。或者，一对电容器板可以仅使用未屏蔽的各向异性蚀刻形成，当孔的一对相对的人行道是垂直的并且被向外倾斜的第二对相对的人行道分隔开时。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式