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61. 发明申请

US20130328127A1 SiGe SRAM BUTTED CONTACT RESISTANCE IMPROVEMENT 有权
标题翻译： SiGe SRAM引脚接触电阻改进
公开(公告)号：US20130328127A1
公开(公告)日：2013-12-12
申请号：US13494157
申请日：2012-06-12
申请人： Chao-Hsuing Chen , Ling-Sung Wang , Chi-Yen Lin
发明人： Chao-Hsuing Chen , Ling-Sung Wang , Chi-Yen Lin
IPC分类号： H01L21/336 , H01L27/088
CPC分类号： H01L21/823814 , H01L21/76895 , H01L21/823412 , H01L21/823418 , H01L21/823475 , H01L21/823878 , H01L27/0207 , H01L27/088 , H01L27/1104 , H01L29/0688 , H01L29/165 , H01L29/7848
摘要： The present disclosure relates to a device and method for fabricating a semiconductor memory device arrangement comprising a butted a contact arrangement configured to couple two transistors, wherein an active area of a first transistor is coupled to an active gate of a second transistor. The active gate of the second transistor is formed from a gate material which comprises a dummy gate of the first transistor, and is configured to straddle a boundary between the active area of the first transistor and an isolation layer formed about the first transistor. The butted a contact arrangement results in a decreased contact resistance for the butted contact as compared to previous methods.
摘要翻译：本公开涉及一种用于制造半导体存储器件装置的器件和方法，该器件包括配置成耦合两个晶体管的对接触点布置，其中第一晶体管的有源区域耦合到第二晶体管的有源栅极。第二晶体管的有源栅极由包括第一晶体管的伪栅极的栅极材料形成，并且被配置为跨越第一晶体管的有源区域和围绕第一晶体管形成的隔离层之间的边界。与之前的方法相比，对接的接触布置导致对接触点的接触电阻降低。

62. 发明授权

US08586486B2 Method for forming semiconductor device 有权
标题翻译：半导体器件形成方法
公开(公告)号：US08586486B2
公开(公告)日：2013-11-19
申请号：US13327947
申请日：2011-12-16
申请人： Jen-Yi Chen , Kun-Ei Chen , Ling-Sung Wang , Chen-Chieh Chiang
发明人： Jen-Yi Chen , Kun-Ei Chen , Ling-Sung Wang , Chen-Chieh Chiang
IPC分类号： H01L21/31
CPC分类号： H01L21/76802 , H01L21/0271 , H01L21/3105 , H01L21/31144 , H01L21/76826
摘要： A method of patterning a material layer of a semiconductor device is disclosed, the method including treating a material layer above a semiconductor substrate with plasma oxygen; depositing a layer of photoresist over a first surface of the material layer after the treating of the material layer; patterning the layer of photoresist, thereby forming a patterned photoresist, exposing portions of the material layer; etching the exposed portions of at least the material layer to form at least one contact via in the material layer extending to a source or drain region of a device at a surface of the substrate; and removing the patterned photoresist from the first surface of the material layer.
摘要翻译：公开了一种图案化半导体器件的材料层的方法，该方法包括用等离子体氧处理半导体衬底之上的材料层; 在处理材料层之后，在材料层的第一表面上沉积光致抗蚀剂层; 图案化光致抗蚀剂层，从而形成图案化的光致抗蚀剂，暴露材料层的部分; 蚀刻至少材料层的暴露部分以在材料层中形成至少一个接触通孔，延伸到衬底的表面处的器件的源极或漏极区域; 以及从所述材料层的第一表面去除所述图案化的光致抗蚀剂。

63. 发明授权

US08558350B2 Metal-oxide-metal capacitor structure 有权
标题翻译：金属氧化物 - 金属电容器结构
公开(公告)号：US08558350B2
公开(公告)日：2013-10-15
申请号：US13274122
申请日：2011-10-14
申请人： Jiun-Jie Huang , Ling-Sung Wang , Chi-Yen Lin
发明人： Jiun-Jie Huang , Ling-Sung Wang , Chi-Yen Lin
IPC分类号： H01L21/02
CPC分类号： H01L23/5223 , H01L23/585 , H01L28/60 , H01L28/86 , H01L28/90 , H01L2924/0002 , H01L2924/00
摘要： A metal-oxide-metal capacitor comprises a first electrode, a second electrode, a plurality of first fingers and a plurality of second fingers. Each first finger and its corresponding second finger are in parallel and separated by a low k dielectric material. A guard ring is employed to enclose the metal-oxide-metal capacitor so as to prevent moisture from penetrating into the low k dielectric material.
摘要翻译：金属氧化物 - 金属电容器包括第一电极，第二电极，多个第一指状物和多个第二指状物。每个第一指状物及其相应的第二指状物平行并由低k电介质材料隔开。采用保护环包围金属氧化物 - 金属电容器，以防止水分渗透到低k电介质材料中。

64. 发明申请

US20130069162A1 OPTICAL PROXIMITY CORRECTION FOR ACTIVE REGION DESIGN LAYOUT 有权
标题翻译：主动区域设计布局的光临近度校正
公开(公告)号：US20130069162A1
公开(公告)日：2013-03-21
申请号：US13233453
申请日：2011-09-15
申请人： Mei-Hsuan Lin , Chih-Chan Lu , Chih-Hsun Lin , Chih-Kang Chao , Ling-Sung Wang , Jen-Pan Wang
发明人： Mei-Hsuan Lin , Chih-Chan Lu , Chih-Hsun Lin , Chih-Kang Chao , Ling-Sung Wang , Jen-Pan Wang
IPC分类号： H01L27/088 , G06F17/50
CPC分类号： G06F17/50 , G06F17/5072 , H01L21/823412 , H01L21/823418 , H01L21/823475 , H01L21/823481 , H01L25/00 , H01L27/0207 , H01L27/11 , H01L27/12 , H01L29/788 , H01L2924/0002 , H03K19/00 , H01L2924/00
摘要： The present disclosure provides an integrated circuit design method. In an example, a method includes receiving an integrated circuit design layout that includes an active region feature, a contact feature, and an isolation feature, wherein a portion of the active region feature is disposed between the contact feature and the isolation feature; determining whether a thickness of the portion of the active region feature disposed between the contact feature and the isolation feature is less than a threshold value; and modifying the integrated circuit design layout if the thickness is less than the threshold value, wherein the modifying includes adding a supplementary active region feature adjacent to the portion of the active region feature disposed between the contact feature and the isolation feature.
摘要翻译：本公开提供了一种集成电路设计方法。在一个示例中，一种方法包括接收包括有源区域特征，接触特征和隔离特征的集成电路设计布局，其中有源区域特征的一部分设置在接触特征和隔离特征之间; 确定布置在接触特征和隔离特征之间的有源区域特征的部分的厚度是否小于阈值; 以及如果所述厚度小于所述阈值，则修改所述集成电路设计布局，其中所述修改包括在所述接触特征与所述隔离特征之间的所述有源区域特征的所述部分附近添加辅助有源区域特征。

65. 发明授权

US08341562B1 Reducing metal pits through optical proximity correction 有权
标题翻译：通过光学邻近校正减少金属凹坑
公开(公告)号：US08341562B1
公开(公告)日：2012-12-25
申请号：US13188166
申请日：2011-07-21
申请人： Jiun-Jie Huang , Chi-Yen Lin , Ling-Sung Wang
发明人： Jiun-Jie Huang , Chi-Yen Lin , Ling-Sung Wang
IPC分类号： G06F17/50
CPC分类号： H01L21/76838 , H01L23/528 , H01L23/5283 , H01L2924/0002 , H01L2924/00
摘要： A method includes retrieving first layouts of an integrated circuit from a non-transitory computer-readable medium. The first layouts include a via pattern in a via layer, and a metal line pattern in a metal layer immediately over the via layer. The metal line pattern has an enclosure to the via pattern. The enclosure is increased to a second enclosure to generate second layouts of the integrated circuit.
摘要翻译：一种方法包括从非暂时计算机可读介质检索集成电路的第一布局。第一布局包括通孔层中的通孔图案，以及在通孔层上方的金属层中的金属线图案。金属线图案具有到通孔图案的外壳。外壳增加到第二个外壳以产生集成电路的第二布局。

66. 发明授权

US06362113B1 Method of forming pattern 有权
标题翻译：形成图案的方法
公开(公告)号：US06362113B1
公开(公告)日：2002-03-26
申请号：US09491067
申请日：2000-01-25
申请人： Ling-Sung Wang
发明人： Ling-Sung Wang
IPC分类号： H01L2144
CPC分类号： H01L21/308 , H01L21/32 , H01L21/76202 , H01L21/76224
摘要： A method of forming a desired rectangular pattern in a material layer above a substrate. The method includes providing a substrate having a material layer thereon. A hard mask layer is next formed over the material layer, and then a first photoresist layer having a first pattern therein is formed over the hard mask layer. A first etching operation is carried out while using the first photoresist layer as an etching mask to remove a portion of the hard mask layer, thereby transferring the pattern in the first photoresist layer to the hard mask layer. The first photoresist layer is removed. A second photoresist layer having a second pattern therein is formed over the substrate. A second etching operation is carried out to remove a portion of the material layer while using the patterned second photoresist layer and the hard mask layer as an etching mask. Hence, the desired rectangular pattern is formed in the material layer.
摘要翻译：在衬底上方的材料层中形成所需矩形图案的方法。该方法包括提供其上具有材料层的基底。接着在材料层上形成硬掩模层，然后在硬掩模层上形成其中具有第一图案的第一光致抗蚀剂层。在使用第一光致抗蚀剂层作为蚀刻掩模以去除硬掩模层的一部分的同时进行第一蚀刻操作，从而将第一光致抗蚀剂层中的图案转印到硬掩模层。去除第一光致抗蚀剂层。在衬底上形成其中具有第二图案的第二光刻胶层。在使用图案化的第二光致抗蚀剂层和硬掩模层作为蚀刻掩模的同时进行第二蚀刻操作以去除材料层的一部分。因此，在材料层中形成所需的矩形图案。

67. 发明授权

US06255164B1 EPROM cell structure and a method for forming the EPROM cell structure 有权
标题翻译： EPROM单元结构和形成EPROM单元结构的方法
公开(公告)号：US06255164B1
公开(公告)日：2001-07-03
申请号：US09365732
申请日：1999-08-03
申请人： Chia-Chen Liu , Ling-Sung Wang
发明人： Chia-Chen Liu , Ling-Sung Wang
IPC分类号： H01L218247
CPC分类号： H01L27/11521 , H01L27/115
摘要： The present invention provides a cell structure of an electrically programmable read only memory (EPROM) which includes an EPROM gate structure, a source junction region, a drain junction region, a first dielectric layer, a self-aligned common source line, a self-aligned drain contact, a second dielectric layer, and a conductive line. The EPROM gate structure is on a portion of the substrate. The source junction region is in the substrate located on a first lateral side, namely the left side in the figure, of the EPROM gate structure. The drain junction region is in the substrate located on a second lateral side, namely the right side in the figure, of the EPROM gate structure. The first dielectric layer covers on top and sidewalls of the EPROM gate structure. The self-aligned common source line neighbors the first dielectric layer and is above the substrate on a portion of the source junction region. The self-aligned drain contact neighbors the first dielectric layer, and is above the substrate on a portion of the drain junction region. The second dielectric layer covers the first dielectric layer, the self-aligned common source line, and the self-aligned drain contact. The conductive line is on the second dielectric layer and communicates to the self-aligned drain contact.
摘要翻译：本发明提供一种电可编程只读存储器（EPROM）的单元结构，其包括EPROM栅极结构，源极结，漏极结区，第一介电层，自对准共源源极线，排列的漏极接触，第二介电层和导电线。 EPROM门结构位于衬底的一部分上。源极结区位于EPROM栅极结构的位于第一侧面（即图中左侧）的衬底中。漏极结区域位于EPROM栅极结构的位于第二侧面（即，图中右侧）的衬底中。第一介电层覆盖在EPROM门结构的顶部和侧壁上。自对准的公共源极线邻近第一电介质层，并且在源极结部分的一部分上方的衬底上方。自对准漏极接触器邻近第一介电层，并且在漏极结区域的一部分上方的衬底上方。第二电介质层覆盖第一介电层，自对准公共源极线和自对准漏极接触。导线在第二电介质层上并与自对准漏极接触连通。

68. 发明授权

US06232184B1 Method of manufacturing floating gate of stacked-gate nonvolatile memory unit 有权
标题翻译：堆叠栅极非易失性存储器单元浮栅的制造方法
公开(公告)号：US06232184B1
公开(公告)日：2001-05-15
申请号：US09394270
申请日：1999-09-10
申请人： Ling-Sung Wang , Chingfu Lin
发明人： Ling-Sung Wang , Chingfu Lin
IPC分类号： H01L21336
CPC分类号： H01L21/28273
摘要： A method of manufacturing the floating gate of a stacked-gate type of nonvolatile memory unit. A gate oxide layer and a polysilicon layer are sequentially formed over a substrate. The polysilicon layer is etched to form a floating gate above the gate oxide layer. During the polysilicon etching operation, a polymeric material is also deposited on the sidewalls of the floating gate and over the exposed gate oxide. An isotropic chemical dry etching of the floating gate is carried out so that its bottom section is slightly wider than its top section. Finally, a thermal oxidation operation is carried out to form an oxide layer over the floating gate.
摘要翻译：一种制造堆叠栅极型非易失性存储器单元的浮置栅极的方法。栅极氧化层和多晶硅层依次形成在衬底上。蚀刻多晶硅层以在栅极氧化物层上方形成浮置栅极。在多晶硅蚀刻操作期间，聚合物材料也沉积在浮动栅极的侧壁上以及暴露的栅极氧化物上。执行浮动栅极的各向同性化学干蚀刻，使其底部部分比其顶部部分稍宽。最后，进行热氧化操作以在浮栅上形成氧化物层。

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