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61. 发明申请

US20100008152A1 SEMICONDUCTOR DEVICE INCLUDING DRIVING TRANSISTORS 有权
标题翻译：包括驱动晶体管的半导体器件
公开(公告)号：US20100008152A1
公开(公告)日：2010-01-14
申请号：US12481916
申请日：2009-06-10
申请人： Se-Hoon Lee , Choong-Ho Lee , Jeong-Dong Choe , Tae-Yong Kim , Woo-Jung Kim , Dong-Hoon Jang , Young-Bae Yoon , Ki-Hyun Kim , Min-Tai Yu
发明人： Se-Hoon Lee , Choong-Ho Lee , Jeong-Dong Choe , Tae-Yong Kim , Woo-Jung Kim , Dong-Hoon Jang , Young-Bae Yoon , Ki-Hyun Kim , Min-Tai Yu
IPC分类号： G11C11/4096 , G11C5/06
CPC分类号： H01L27/11573 , H01L21/823425 , H01L27/0207 , H01L27/105 , H01L27/11519 , H01L27/11526 , H01L27/11531 , H01L27/11568 , H01L29/78
摘要： A semiconductor device includes a driving active region defined in a substrate and at least three driving transistors disposed at the driving active region. The driving transistors share one common source/drain, and each of the driving transistors includes individual source/drains being independent from each other. The common source/drain and the individual source/drains are disposed in the driving active region.
摘要翻译：半导体器件包括限定在衬底中的驱动有源区和设置在驱动有源区的至少三个驱动晶体管。驱动晶体管共享一个共同的源极/漏极，并且每个驱动晶体管包括彼此独立的各个源极/漏极。公共源极/漏极和各个源极/漏极设置在驱动有源区域中。

62. 发明申请

US20080001209A1 Non-volatile memory device and method of manufacturing the non-volatile memory device 审中-公开
标题翻译：非易失性存储器件和制造非易失性存储器件的方法
公开(公告)号：US20080001209A1
公开(公告)日：2008-01-03
申请号：US11783548
申请日：2007-04-10
申请人： Eun-Suk Cho , Kyu-Charn Park , Jong-Jin Lee , Jeong-Dong Choe
发明人： Eun-Suk Cho , Kyu-Charn Park , Jong-Jin Lee , Jeong-Dong Choe
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L29/7883 , H01L27/115 , H01L27/11521 , H01L29/42324 , H01L29/42336
摘要： A non-volatile memory device may include a substrate having a field region and an active region including a rounded upper edge portion and a flat upper central portion, an effective tunnel oxide layer on the flat upper central portion of the active region, a split floating gate electrode on the effective tunnel oxide layer, the floating gate electrode having a width greater than a width of the effective tunnel oxide layer, a dielectric layer pattern on the floating gate electrode, the dielectric layer pattern including metal oxide, and a control gate electrode on the dielectric layer pattern.
摘要翻译：非易失性存储器件可以包括具有场区域和包括圆形上边缘部分和平坦上中心部分的有源区域的基板，在有源区域的平坦上中心部分上的有效隧道氧化物层，分裂浮动栅极电极在有效隧道氧化物层上，浮栅电极的宽度大于有效隧道氧化物层的宽度，浮栅电极上的电介质层图案，包括金属氧化物的电介质层图案和控制栅电极在电介质层图案上。

63. 发明授权

US08178408B2 Methods of manufacturing charge trap-type non-volatile memory devices 有权
标题翻译：制造电荷陷阱型非易失性存储器件的方法
公开(公告)号：US08178408B2
公开(公告)日：2012-05-15
申请号：US12651781
申请日：2010-01-04
申请人： Hak-Sun Lee , Kyoung-Sub Shin , Jeong-Dong Choe
发明人： Hak-Sun Lee , Kyoung-Sub Shin , Jeong-Dong Choe
IPC分类号： H01L21/336 , H01L21/3205
CPC分类号： H01L27/11568
摘要： Some methods are directed to manufacturing charge trap-type non-volatile memory devices. An isolation layer pattern can be formed that extends in a first direction in a substrate. A recess unit is formed in the substrate by recessing an exposed surface of the substrate adjacent to the isolation layer pattern. A tunnel insulating layer and a charge trap layer are sequentially formed on the substrate. The tunnel insulating layer and the charge trap layer are patterned to form an isolated island-shaped tunnel insulating layer pattern and an isolated island-shaped charge trap layer pattern by etching defined regions of the substrate, the isolation layer pattern, the tunnel insulating layer, and the charge trap layer until a top surface of the charge trap layer that is disposed on a bottom surface of the recess unit is aligned with a top surface of the isolation layer pattern. A blocking insulating layer is formed that covers the charge trap layer pattern, the isolation layer pattern, and a defined region of the substrate interposed between the charge trap patterns. A gate electrode pattern is formed on the blocking insulating layer to face the charge trap layer pattern. This manufacturing process may reduce charge spreading between unit memory cells and/or may prevent/avoid reduction in the breakdown voltage of the blocking insulating layer.
摘要翻译：一些方法涉及制造电荷陷阱型非易失性存储器件。可以形成在衬底中沿第一方向延伸的隔离层图案。通过使邻近隔离层图案的基板的暴露表面凹陷而在基板中形成凹部单元。隧道绝缘层和电荷陷阱层依次形成在基板上。图案化隧道绝缘层和电荷陷阱层，通过蚀刻衬底的限定区域，隔离层图案，隧道绝缘层，隔离层状图案，隔离层状图案，隧道绝缘层，并且电荷陷阱层直到设置在凹陷单元的底表面上的电荷陷阱层的顶表面与隔离层图案的顶表面对准。形成了覆盖电荷陷阱层图案，隔离层图案和插入在电荷阱图案之间的基板的限定区域的阻挡绝缘层。在阻挡绝缘层上形成面对电荷陷阱层图案的栅电极图案。该制造过程可以减小单元存储单元之间的电荷扩展和/或可以防止/避免阻塞绝缘层的击穿电压的降低。

64. 发明申请

US20120015496A1 METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20120015496A1
公开(公告)日：2012-01-19
申请号：US13240883
申请日：2011-09-22
申请人： Young-Bae YOON , Jeong-Dong Choe , Dong-Hoon Jang , Ki-Hyun Kim
发明人： Young-Bae YOON , Jeong-Dong Choe , Dong-Hoon Jang , Ki-Hyun Kim
IPC分类号： H01L21/762
CPC分类号： H01L21/823481 , H01L21/823456 , H01L27/11521 , H01L27/11524
摘要： A semiconductor device includes a substrate having a first area and a second area, a first transistor in the first area, a second transistor in the second area, an isolation layer between the first area and the second area, and at least one buried shield structure on the isolation layer.
摘要翻译：半导体器件包括具有第一区域和第二区域的衬底，第一区域中的第一晶体管，第二区域中的第二晶体管，第一区域和第二区域之间的隔离层，以及至少一个掩埋屏蔽结构在隔离层上。

65. 发明授权

US08049269B2 Non-volatile memory device and method of manufacturing the same 有权
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US08049269B2
公开(公告)日：2011-11-01
申请号：US11898266
申请日：2007-09-11
申请人： Se-Hoon Lee , Kyu-Charn Park , Jeong-Dong Choe
发明人： Se-Hoon Lee , Kyu-Charn Park , Jeong-Dong Choe
IPC分类号： H01L29/792 , H01L29/788 , H01L21/336 , H01L21/8247
CPC分类号： H01L27/115 , H01L27/11568 , H01L29/66833 , H01L29/792 , H01L29/7926
摘要： In a non-volatile memory device, active fin structures extending in a first direction may be formed on a substrate. A tunnel insulating layer may be formed on surfaces of the active fin structures and bottom surfaces of trenches that may be defined by the active fin structures. A charge trapping layer and a blocking layer may be sequentially formed on the tunnel insulating layer. A gate electrode structure may include first portions disposed over top surfaces of the active fin structures and second portions vertically spaced apart from portions of the charge trapping layer that may be disposed over the bottom surfaces of the trenches, and may extend in a second direction substantially perpendicular to the first direction. Thus, lateral electron diffusion may be reduced in the charge trapping layer, and thereby the data retention performance and/or reliability of the non-volatile memory device may be improved.
摘要翻译：在非易失性存储器件中，可以在衬底上形成沿第一方向延伸的活性鳍结构。隧道绝缘层可以形成在活动鳍结构和沟槽底表面的表面上，沟槽绝缘层可以由活性鳍结构限定。电荷俘获层和阻挡层可以顺序形成在隧道绝缘层上。栅极电极结构可以包括设置在有源鳍结构的顶表面上的第一部分和与可以设置在沟槽的底表面之上的电荷俘获层的部分垂直间隔开的第二部分，并且可以在基本上垂直于第一方向。因此，电荷捕捉层中的横向电子扩散可能减少，从而可以提高非易失性存储器件的数据保持性能和/或可靠性。

66. 发明申请

US20080265304A1 Nonvolatile semiconductor device including a floating gate, method of manufacturing the same and associated systems 失效
标题翻译：包括浮动栅极的非易失性半导体器件，其制造方法和相关系统
公开(公告)号：US20080265304A1
公开(公告)日：2008-10-30
申请号：US11896982
申请日：2007-09-07
申请人： Se-Hoon Lee , Donghoon Jang , Jong Jin Lee , Jeong-Dong Choe
发明人： Se-Hoon Lee , Donghoon Jang , Jong Jin Lee , Jeong-Dong Choe
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L29/42324 , H01L21/28273 , H01L29/66825 , H01L29/7881
摘要： A memory device includes a first floating gate electrode on a substrate between adjacent isolation layers in the substrate, at least a portion of the first floating gate protruding above a portion of the adjacent isolation layers, a second floating gate electrode, electrically connected to the first floating gate electrode, on at least one of the adjacent isolation layers, a dielectric layer over the first and second floating gate electrodes, and a control gate over the dielectric layer and the first and second floating gate electrodes.
摘要翻译：存储器件包括在衬底中相邻隔离层之间的衬底上的第一浮置栅电极，第一浮置栅极的至少一部分突出在相邻隔离层的一部分上方，第二浮栅电极电连接到第一浮栅浮栅电极，在至少一个相邻的隔离层上，第一和第二浮置栅电极之上的电介质层，以及介电层上的控制栅极以及第一和第二浮栅电极。

67. 发明申请

US20080061361A1 Non-volatile memory device and method of manufacturing the same 有权
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US20080061361A1
公开(公告)日：2008-03-13
申请号：US11898266
申请日：2007-09-11
申请人： Se-Hoon Lee , Kyu-Charn Park , Jeong-Dong Choe
发明人： Se-Hoon Lee , Kyu-Charn Park , Jeong-Dong Choe
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L27/115 , H01L27/11568 , H01L29/66833 , H01L29/792 , H01L29/7926
摘要： In a non-volatile memory device, active fin structures extending in a first direction may be formed on a substrate. A tunnel insulating layer may be formed on surfaces of the active fin structures and bottom surfaces of trenches that may be defined by the active fin structures. A charge trapping layer and a blocking layer may be sequentially formed on the tunnel insulating layer. A gate electrode structure may include first portions disposed over top surfaces of the active fin structures and second portions vertically spaced apart from portions of the charge trapping layer that may be disposed over the bottom surfaces of the trenches, and may extend in a second direction substantially perpendicular to the first direction. Thus, lateral electron diffusion may be reduced in the charge trapping layer, and thereby the data retention performance and/or reliability of the non-volatile memory device may be improved.
摘要翻译：在非易失性存储器件中，可以在衬底上形成沿第一方向延伸的活性鳍结构。隧道绝缘层可以形成在活动鳍结构和沟槽底表面的表面上，沟槽绝缘层可以由活性鳍结构限定。电荷俘获层和阻挡层可以顺序形成在隧道绝缘层上。栅极电极结构可以包括设置在有源鳍结构的顶表面上的第一部分和与可以设置在沟槽的底表面之上的电荷俘获层的部分垂直间隔开的第二部分，并且可以在基本上垂直于第一方向。因此，电荷捕捉层中的横向电子扩散可能减少，从而可以提高非易失性存储器件的数据保持性能和/或可靠性。

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