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61. 发明授权

US07843747B2 System and method for better testability of OTP memory 有权
标题翻译： OTP内存的更好的可测试性的系统和方法
公开(公告)号：US07843747B2
公开(公告)日：2010-11-30
申请号：US12124989
申请日：2008-05-21
申请人： Fu-Lung Hsueh , Shine Chung , Wen-Kuan Fang , Po-Hung Chen
发明人： Fu-Lung Hsueh , Shine Chung , Wen-Kuan Fang , Po-Hung Chen
IPC分类号： G11C29/00
CPC分类号： G11C29/08 , G11C2216/26
摘要： A system for testing logic circuits for executing writing and reading operations in a one-time programmable (OTP) memory having an array of memory cells is disclosed, the system comprising a column of testing cells having the same number of cells as that of an entire column of the array of memory cells, a row of testing cells having the same number of cells as that of an entire row of the array of memory cells, wherein both the column and row of testing cells are first written to and then read out from during a testing operation, and can never be accessed during non-testing operations of the OTP memory.
摘要翻译：公开了一种用于测试在具有存储器单元阵列的一次可编程（OTP）存储器中执行写入和读取操作的逻辑电路的系统，该系统包括具有与整个存储器单元相同数量的单元格的测试单元列存储单元阵列的列，一行具有与存储器单元阵列的整行相同数量的单元的测试单元，其中测试单元的列和行首先被写入然后从在测试操作期间，并且在OTP存储器的非测试操作期间永远不能被访问。

62. 发明授权

US07821041B2 Electrical fuse circuit for security applications 有权
标题翻译：电熔丝电路用于安全应用
公开(公告)号：US07821041B2
公开(公告)日：2010-10-26
申请号：US11748959
申请日：2007-05-15
申请人： Shine Chung , Fu-Lung Hsueh , Fu-Chieh Hsu
发明人： Shine Chung , Fu-Lung Hsueh , Fu-Chieh Hsu
IPC分类号： H01L29/73
CPC分类号： G11C17/18
摘要： A fuse circuit is disclosed, which comprises at least one electrical fuse element having a resistance that changes after being stressed in an electromigration mode, a switching device serially coupled with the electrical fuse element in a predetermined path between a fuse programming power supply (VDDQ) and a low voltage power supply (GND) for selectively allowing a programming current passing through the electrical fuse element during a programming operation, and at least one peripheral circuit coupled to the VDDQ, wherein the peripheral circuit is active and draws current from the VDDQ during a fuse programming operation.
摘要翻译：公开了一种熔丝电路，其包括至少一个电熔丝元件，该电熔丝元件具有在电迁移模式下受到应力之后变化的电阻;开关装置，其在熔丝编程电源（VDDQ）之间的预定路径中与电熔丝元件串联连接，以及用于在编程操作期间选择性地允许通过电熔丝元件的编程电流的低电压电源（GND），以及耦合到所述VDDQ的至少一个外围电路，其中所述外围电路是有效的并且在VDDQ期间从VDDQ引出电流保险丝编程操作。

63. 发明申请

US20080169514A1 Stack resistor structure for integrated circuits 有权
标题翻译：集成电路的堆叠电阻结构
公开(公告)号：US20080169514A1
公开(公告)日：2008-07-17
申请号：US11652895
申请日：2007-01-11
申请人： Fu-Lung Hsueh , Sung-Chieh Lin
发明人： Fu-Lung Hsueh , Sung-Chieh Lin
IPC分类号： H01L29/76 , H01L29/94 , H01L31/00
CPC分类号： H01L23/5228 , H01L2924/0002 , H01L2924/00
摘要： A resistor structure for an integrated circuit includes a first set of contacts connected between a semiconductor layer and a first conductive layer; and a second set of plugs connected between the first conductive layer and a second conductive layer, wherein the first set of contacts and the second set of plugs are coupled together as a first resistor segment to provide a predetermined resistance for the integrated circuit.
摘要翻译：用于集成电路的电阻器结构包括连接在半导体层和第一导电层之间的第一组触点; 以及连接在所述第一导电层和第二导电层之间的第二组插头，其中所述第一组触点和所述第二组插头作为第一电阻器段耦合在一起以为所述集成电路提供预定电阻。

64. 发明申请

US20080012663A1 Waveguides in integrated circuits 有权
标题翻译：集成电路中的波导
公开(公告)号：US20080012663A1
公开(公告)日：2008-01-17
申请号：US11486903
申请日：2006-07-14
申请人： Shine Chung , Fu-Lung Hsueh
发明人： Shine Chung , Fu-Lung Hsueh
IPC分类号： H01P3/12
CPC分类号： H01P3/12 , H01L2924/0002 , H01L2924/00
摘要： A waveguide in semiconductor integrated circuit is disclosed, the waveguide comprises a horizontal first metal plate, a horizontal second metal plate above the first metal plate, separated by an insulation material, and a plurality of metal vias positioned in two parallel lines, running vertically through the insulation material in contacts with both the first and second metal plates, wherein the first and second metal plates and the plurality of metal vias form a metal enclosure in a cross-sectional view that can serve as a waveguide.
摘要翻译：公开了一种半导体集成电路中的波导，波导包括水平的第一金属板，在第一金属板上方的水平的第二金属板，由绝缘材料隔开，并且多个金属通孔位于两条平行的线上，垂直延伸穿过所述绝缘材料与所述第一和第二金属板两者接触，其中所述第一和第二金属板和所述多个金属通孔以横截面视图形成可用作波导的金属外壳。

65. 发明授权

US5014055A Analog-to-digital converter and method of use utilizing charge redistribution 失效
标题翻译：模数转换器和利用电荷再分配的使用方法
公开(公告)号：US5014055A
公开(公告)日：1991-05-07
申请号：US356084
申请日：1989-05-24
申请人： Andrew G. F. Dingwall , Fu-Lung Hsueh
发明人： Andrew G. F. Dingwall , Fu-Lung Hsueh
IPC分类号： G11C27/02 , H03M1/12 , H03M1/14 , H03M1/36
CPC分类号： G11C27/024 , H03M1/1215 , H03M1/146 , H03M1/365
摘要： A twelve bit analog-to-digital converter uses two banks of 31 capacitors each coupled through separate control circuitry to a five bit analog-to-digital converter with plus or minus 1/2 bit accuracy and two separate eight bit analog-to-digital converters each having plus or minus 1/2 bit accuracy to achieve a frequency of operation from at least several MHz to up to about 40 MHz.
摘要翻译：一个十二位模数转换器使用两组31个电容，每组分别通过单独的控制电路耦合到具有正或负1/2位精度的五位模数转换器和两个独立的八位模数转换器每个转换器具有正或负1/2位精度，以实现从至少几MHz到高达约40MHz的操作频率。

66. 发明授权

US08648779B2 LCD driver 有权
标题翻译：液晶驱动
公开(公告)号：US08648779B2
公开(公告)日：2014-02-11
申请号：US12582107
申请日：2009-10-20
申请人： Fu-Lung Hsueh , Yung-Chow Peng , Kuo-Liang Deng
发明人： Fu-Lung Hsueh , Yung-Chow Peng , Kuo-Liang Deng
IPC分类号： G09G5/00 , G09G3/36
CPC分类号： G09G3/3688 , G09G2310/027 , G09G2320/02 , G09G2330/021
摘要： A method includes outputting a first signal from a first DAC decoder circuit in response to receiving a first number of bits of a digital control signal, outputting a second signal from a second DAC decoder circuit in response to receiving a second number of bits of the digital control signal, and alternately outputting one of the first and second signals to an LCD column from a buffer coupled to the first and second DAC decoder circuits. The first signal has a voltage level equal to one of a first plurality of voltage levels received at one of a first plurality of inputs of the first DAC decoder circuit. The second signal has a voltage level equal to one of a second plurality of voltage levels received at one of a second plurality of inputs of the second DAC decoder circuit.
摘要翻译：一种方法包括响应于接收数字控制信号的第一位数而输出来自第一DAC解码器电路的第一信号，响应于接收到数字控制信号的第二位数而从第二DAC解码器电路输出第二信号并且从耦合到第一和第二DAC解码器电路的缓冲器交替地将第一和第二信号之一输出到LCD列。第一信号具有等于在第一DAC解码器电路的第一多个输入端之一处接收的第一多个电压电平之一的电压电平。第二信号具有等于在第二DAC解码器电路的第二多个输入端之一处接收的第二多个电压电平之一的电压电平。

67. 发明授权

US08619488B2 Multi-level electrical fuse using one programming device 有权
标题翻译：使用一个编程设备的多级电气保险丝
公开(公告)号：US08619488B2
公开(公告)日：2013-12-31
申请号：US13492635
申请日：2012-06-08
申请人： Yung-Lung Lin , Jui-Jen Wu , Shine Chung , Fu-Lung Hsueh
发明人： Yung-Lung Lin , Jui-Jen Wu , Shine Chung , Fu-Lung Hsueh
IPC分类号： G11C17/18 , G11C17/14 , G11C17/16 , G11C17/00
CPC分类号： G11C11/5692 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A method for programming a multi-level electrical fuse system comprises providing a fuse box with an electrical fuse and providing one of at least two fuse writing voltages to the electrical fuse to program the electrical fuse to one of at least two resistance states. The fuse box comprises at least one electrical fuse, a programming device serially coupled to the electrical fuse, and a variable power supply coupled to the fuse box and configured to generate two or more voltage levels.
摘要翻译：一种用于编程多电平电熔丝系统的方法包括：提供具有电熔丝的保险丝盒，并向所述电熔丝提供至少两个熔丝写入电压中的一个，以将所述电熔丝编程为至少两个电阻状态之一。保险丝盒包括至少一个电熔丝，串联耦合到电熔丝的编程装置，以及耦合到保险丝盒并配置成产生两个或多个电压电平的可变电源。

68. 发明授权

US08418098B2 Advisory system for verifying sensitive circuits in chip-design 有权
标题翻译：用于验证芯片设计中的敏感电路的咨询系统
公开(公告)号：US08418098B2
公开(公告)日：2013-04-09
申请号：US12054195
申请日：2008-03-24
申请人： Chi-Heng Huang , Gary Lin , Chu-Fu Chen , Yi-Kan Cheng , Fu-Lung Hsueh
发明人： Chi-Heng Huang , Gary Lin , Chu-Fu Chen , Yi-Kan Cheng , Fu-Lung Hsueh
IPC分类号： G06F17/50 , H03K5/22
CPC分类号： G06F17/5036 , G06F17/5009
摘要： A verification system for verifying an integrated circuit design is provided. The verification system includes a functional block finding module configured to identify potential sensitive circuits in the integrated circuit design; and a search module. The search module is configured to find sensitive circuits from the potential sensitive circuits; and verify the sensitive circuits.
摘要翻译：提供了用于验证集成电路设计的验证系统。验证系统包括：功能块查找模块，被配置为识别集成电路设计中的潜在敏感电路; 和搜索模块。搜索模块被配置为从潜在敏感电路中找到敏感电路; 并验证敏感电路。

69. 发明授权

US08279008B2 CMOS millimeter-wave variable-gain low-noise amplifier 有权
标题翻译： CMOS毫米波可变增益低噪声放大器
公开(公告)号：US08279008B2
公开(公告)日：2012-10-02
申请号：US12851705
申请日：2010-08-06
申请人： Hsieh-Hung Hsieh , Po-Yi Wu , Ho-Hsiang Chen , Chewn-Pu Jou , Fu-Lung Hsueh
发明人： Hsieh-Hung Hsieh , Po-Yi Wu , Ho-Hsiang Chen , Chewn-Pu Jou , Fu-Lung Hsueh
IPC分类号： H03G3/30 , H03F1/22 , H03F3/16
CPC分类号： H03G1/0029 , H03F1/223 , H03F3/195 , H03F2200/249 , H03F2200/318 , H03F2200/408 , H03F2200/411 , H03F2200/451 , H03F2200/492 , H03G3/3052
摘要： A low-noise amplifier (LNA) includes a first cascode gain stage coupled to an input node for increasing an amplitude of an RF input signal. A first variable gain network is coupled to the first cascode gain stage and includes a first inductor for boosting a gain of the first cascode gain stage, a first capacitor coupled to the first inductor for blocking a direct current (DC) voltage, and a first switch coupled to the first inductor and to the first capacitor. The first switch is configured to selectively couple the first inductor to the first cascode gain stage in response to a first control signal.
摘要翻译：低噪声放大器（LNA）包括耦合到输入节点的第一共源共同增益级，用于增加RF输入信号的幅度。第一可变增益网络耦合到第一共源共同增益级，并且包括用于升高第一共源共享增益级的增益的第一电感器，耦合到第一电感器以阻止直流（DC）电压的第一电容器，以及第一可变增益网络开关耦合到第一电感器和第一电容器。第一开关被配置为响应于第一控制信号选择性地将第一电感器耦合到第一共源共享增益级。

70. 发明授权

US08143644B2 Bipolar device compatible with CMOS process technology 有权
标题翻译：双极器件兼容CMOS工艺技术
公开(公告)号：US08143644B2
公开(公告)日：2012-03-27
申请号：US12256376
申请日：2008-10-22
申请人： Shine Chung , Fu-Lung Hsueh
发明人： Shine Chung , Fu-Lung Hsueh
IPC分类号： H01L29/739
CPC分类号： H01L29/735 , H01L27/0207 , H01L27/0623 , H01L29/0692 , H01L29/1008
摘要： A bipolar device includes: an emitter of a first polarity type constructed on a semiconductor substrate; a collector of the first polarity type constructed on the semiconductor substrate; a gate pattern in a mesh configuration defining the emitter and the collector; an intrinsic base of a second polarity type underlying the gate pattern; and an extrinsic base constructed atop the gate pattern and coupled with the intrinsic base, for functioning together with the intrinsic base as a base of the bipolar device.
摘要翻译：双极器件包括：构造在半导体衬底上的第一极性类型的发射极; 在半导体衬底上构造的第一极性类型的集电极; 限定发射极和集电极的网格配置中的栅极图案; 位于栅极图案下方的第二极性类型的本征基极; 以及构造在栅极图案顶部并与本征基极耦合的外部基极，用于与作为双极器件的基极的本征基极一起工作。

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