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61. 发明申请

US20090164399A1 Method for Autonomic Workload Distribution on a Multicore Processor 有权
标题翻译：多核处理器上的自动工作负载分配方法
公开(公告)号：US20090164399A1
公开(公告)日：2009-06-25
申请号：US11959520
申请日：2007-12-19
申请人： Robert H. Bell, JR. , Louis Bennie Capps, JR. , Thomas Edward Cook , Thomas J. Dewkett , Naresh Nayar , Ronald Edward Newhart , Bernadette Ann Pierson , Michael Jay Shapiro
发明人： Robert H. Bell, JR. , Louis Bennie Capps, JR. , Thomas Edward Cook , Thomas J. Dewkett , Naresh Nayar , Ronald Edward Newhart , Bernadette Ann Pierson , Michael Jay Shapiro
IPC分类号： G06F15/76 , G06F15/18
CPC分类号： G06F9/5083
摘要： A multiprocessor system which includes automatic workload distribution. As threads execute in the multiprocessor system, an operating system or hypervisor continuously learns the execution characteristics of the threads and saves the information in thread-specific control blocks. The execution characteristics are used to generate thread performance data. As the thread executes, the operating system continuously uses the performance data to steer the thread to a core that will execute the workload most efficiently.
摘要翻译：一个包含自动工作负载分配的多处理器系统。当线程在多处理器系统中执行时，操作系统或管理程序将持续学习线程的执行特性，并将信息保存在线程特定的控制块中。执行特性用于生成线程性能数据。当线程执行时，操作系统会持续使用性能数据来将线程引导到最高效执行工作负载的内核。

62. 发明申请

US20090144737A1 DYNAMIC SWITCHING OF MULTITHREADED PROCESSOR BETWEEN SINGLE THREADED AND SIMULTANEOUS MULTITHREADED MODES 有权
标题翻译：单螺纹和同时多路模式之间的多处理器的动态切换
公开(公告)号：US20090144737A1
公开(公告)日：2009-06-04
申请号：US12358405
申请日：2009-01-23
申请人： William Joseph Armstrong , Bruce G. Mealey , Naresh Nayar , Balaram Sinharoy
发明人： William Joseph Armstrong , Bruce G. Mealey , Naresh Nayar , Balaram Sinharoy
IPC分类号： G06F9/44 , G06F9/38
CPC分类号： G06F9/4812 , G06F9/30189 , G06F9/3851 , G06F9/485
摘要： An apparatus and program product utilize a multithreaded processor having at least one hardware thread among a plurality of hardware threads that is capable of being selectively activated and deactivated responsive to a control circuit. The control circuit additionally provides the capability of controlling how an inactive thread can be activated after the thread has been deactivated, e.g., by enabling or disabling reactivation in response to an interrupt.
摘要翻译：一种装置和程序产品利用多线程处理器，其具有能够响应于控制电路选择性地激活和去激活的多个硬件线程中的至少一个硬件线程。控制电路另外提供了控制如何在线程被去激活之后如何激活非活动线程的能力，例如通过启用或禁用响应于中断的重新激活。

63. 发明申请

US20090138660A1 Power-aware line intervention for a multiprocessor snoop coherency protocol 有权
标题翻译：多处理器侦听一致性协议的功率感知线路干预
公开(公告)号：US20090138660A1
公开(公告)日：2009-05-28
申请号：US11946249
申请日：2007-11-28
申请人： Robert H. Bell, JR. , Louis B. Capps, JR. , Thomas E. Cook , Michael J. Shapiro , Naresh Nayar
发明人： Robert H. Bell, JR. , Louis B. Capps, JR. , Thomas E. Cook , Michael J. Shapiro , Naresh Nayar
IPC分类号： G06F12/08
CPC分类号： G06F12/0831 , G06F2212/1028 , Y02D10/13
摘要： A snoop coherency method, system and program are provided for intervening a requested cache line from a plurality of candidate memory sources in a multiprocessor system on the basis of the sensed temperature or power dissipation value at each memory source. By providing temperature or power dissipation sensors in each of the candidate memory sources (e.g., at cores, cache memories, memory controller, etc.) that share a requested cache line, control logic may be used to determine which memory source should source the cache line by using the power sensor signals to signal only the memory source with acceptable power dissipation to provide the cache line to the requester.
摘要翻译：提供窥探一致性方法，系统和程序，用于基于每个存储器源处的感测温度或功率耗散值，在多处理器系统中从多个候选存储器源插入所请求的高速缓存行。通过在共享所请求的高速缓存行的每个候选存储器源（例如，在内核，高速缓冲存储器，存储器控制器等）中提供温度或功率耗散传感器，可以使用控制逻辑来确定哪个存储器源应该来源于高速缓存通过使用功率传感器信号仅以可接受的功率消耗信号通知存储器源，以向请求器提供高速缓存线。

64. 发明申请

US20080256321A1 System and Method for Tracking the Memory State of a Migrating Logical Partition 有权
标题翻译：跟踪迁移逻辑分区的内存状态的系统和方法
公开(公告)号：US20080256321A1
公开(公告)日：2008-10-16
申请号：US11735809
申请日：2007-04-16
申请人： William Joseph Armstrong , Michael J. Corrigan , Stuart Zachary Jacobs , David Anthony Larson , Naresh Nayar , Wade Byron Ouren
发明人： William Joseph Armstrong , Michael J. Corrigan , Stuart Zachary Jacobs , David Anthony Larson , Naresh Nayar , Wade Byron Ouren
IPC分类号： G06F12/00
CPC分类号： G06F12/10 , G06F9/4856 , G06F9/5077 , G06F12/08 , G06F12/1036 , G06F12/109
摘要： An apparatus, program product and method for tracking the state of a migrating logical partition. Embodiments may use the state to determine the readiness and/or appropriateness of a page of the logical partition for transferring. The state may include a value or other data used to track changes affecting the page or the relative ease and/or appropriateness of migrating the page. A page manager table with entries corresponding to the state of each page of the logical partition may be used to track the state while the logical partition continues to run during a migration.
摘要翻译：用于跟踪迁移逻辑分区的状态的装置，程序产品和方法。实施例可以使用该状态来确定用于传送的逻辑分区的页面的准备和/或适当性。状态可以包括用于跟踪影响页面的变化的值或其他数据，或迁移页面的相对容易度和/或适当性。可以使用具有与逻辑分区的每个页面的状态对应的条目的页面管理器表来跟踪状态，同时逻辑分区在迁移期间继续运行。

65. 发明授权

US07428485B2 System for yielding to a processor 失效
标题翻译：用于屈服于处理器的系统
公开(公告)号：US07428485B2
公开(公告)日：2008-09-23
申请号：US09939232
申请日：2001-08-24
申请人： William Joseph Armstrong , Chris Francois , Naresh Nayar
发明人： William Joseph Armstrong , Chris Francois , Naresh Nayar
IPC分类号： G06F9/44
CPC分类号： G06F9/4843 , G06F9/4881 , G06F9/5077
摘要： An apparatus, program product and method for coordinating the distribution of CPUs as among logically-partitioned virtual processors. A virtual processor may yield a CPU to precipitate an occurrence upon which its own execution may be predicated. As such, program code may dispatch the surrendered CPU to a designated virtual processor.
摘要翻译：用于协调在逻辑分区虚拟处理器之间分配CPU的装置，程序产品和方法。虚拟处理器可能会产生一个CPU来沉淀其本身可执行的事件。因此，程序代码可以将投降的CPU分派到指定的虚拟处理器。

66. 发明申请

US20080201550A1 AUTONOMICALLY SUSPENDING AND RESUMING LOGICAL PARTITIONS WHEN I/O RECONFIGURATION IS REQUIRED 审中-公开
标题翻译：当需要I / O重新配置时，自动暂停和恢复逻辑分区
公开(公告)号：US20080201550A1
公开(公告)日：2008-08-21
申请号：US12111940
申请日：2008-04-29
申请人： David Alan Bailey , William Joseph Armstrong , Naresh Nayar , Gregory Michael Nordstrom
发明人： David Alan Bailey , William Joseph Armstrong , Naresh Nayar , Gregory Michael Nordstrom
IPC分类号： G06F12/06
CPC分类号： G06F9/5077
摘要： A partition manager includes an I/O reconfiguration mechanism and a logical partition suspend/resume mechanism that work together to perform autonomic I/O reconfiguration in a logically partitioned computer system. When I/O reconfiguration is required, the affected logical partitions are suspended, the I/O is reconfigured, and the affected logical partitions are resumed. Because the logical partitions are suspended during I/O reconfiguration, any ghost packet that may occur when the I/O is reconfigured is ignored.
摘要翻译：分区管理器包括I / O重新配置机制和逻辑分区挂起/恢复机制，其协同工作以在逻辑分区的计算机系统中执行自主I / O重新配置。当需要I / O重新配置时，受影响的逻辑分区将被挂起，重新配置I / O，并恢复受影响的逻辑分区。因为逻辑分区在I / O重新配置期间被挂起，所以当I / O被重新配置时可能发生的任何ghost数据包被忽略。

67. 发明授权

US07389400B2 Apparatus and method for selectively invalidating entries in an address translation cache 有权
标题翻译：用于选择性地使地址转换高速缓存中的条目无效的装置和方法
公开(公告)号：US07389400B2
公开(公告)日：2008-06-17
申请号：US11304136
申请日：2005-12-15
申请人： Michael J. Corrigan , Paul LuVerne Godtland , Joaquin Hinojosa , Cathy May , Naresh Nayar , Edward John Silha
发明人： Michael J. Corrigan , Paul LuVerne Godtland , Joaquin Hinojosa , Cathy May , Naresh Nayar , Edward John Silha
IPC分类号： G06F12/00
CPC分类号： G06F12/1036 , G06F12/126 , G06F2212/1016 , G06F2212/683
摘要： An apparatus and method selectively invalidate entries in an address translation cache instead of invalidating all, or nearly all, entries. One or more translation mode bits are provided in each entry in the address translation cache. These translation mode bits may be set according to the addressing mode used to create the cache entry. One or more “hint bits” are defined in an instruction that allow specifying which of the entries in the address translation cache are selectively preserved during an invalidation operation according to the value(s) of the translation mode bit(s). In the alternative, multiple instructions may be defined to preserve entries in the address translation cache that have specified addressing modes. In this manner, more intelligence is used to recognize that some entries in the address translation cache may be valid after a task or partition switch, and may therefore be retained, while other entries in the address translation cache are invalidated.
摘要翻译：一种装置和方法选择性地使地址转换高速缓存中的条目无效，而不是使所有或几乎所有条目无效。在地址转换高速缓存中的每个条目中提供一个或多个翻译模式位。可以根据用于创建高速缓存条目的寻址模式来设置这些转换模式位。在指令中定义一个或多个“提示位”，该指令允许根据翻译模式位的值来指定在无效操作期间选择性地保留地址转换高速缓存中的哪些条目。在替代方案中，可以定义多个指令以保留具有指定寻址模式的地址转换高速缓存中的条目。以这种方式，使用更多的智能来识别地址转换高速缓存中的一些条目在任务或分区切换之后可能是有效的，并且因此可以被保留，而地址转换高速缓存中的其他条目是无效的。

68. 发明授权

US07281075B2 Virtualization of a global interrupt queue 有权
标题翻译：虚拟化全局中断队列
公开(公告)号：US07281075B2
公开(公告)日：2007-10-09
申请号：US10422513
申请日：2003-04-24
申请人： William Joseph Armstrong , David Anthony Larson , Naresh Nayar
发明人： William Joseph Armstrong , David Anthony Larson , Naresh Nayar
IPC分类号： G06F13/24
CPC分类号： G06F9/45533 , G06F13/24
摘要： A method, system, and article of manufacture for processing virtual interrupts in a logically partitioned system are provided. An intelligent virtual global interrupt queue (virtual GIQ) that may be associated with a plurality of virtual processors running in a logical partition may be utilized. Upon receiving a virtual interrupt, the virtual GIQ may examine the operating states of the associated virtual processors. In an effort to ensure the virtual interrupt is processed as quickly as possible, the virtual GIQ may present the virtual interrupt to one of the associated virtual processors determined to be in an operating state best suited for processing the virtual interrupt.
摘要翻译：提供了一种用于处理逻辑分区系统中的虚拟中断的方法，系统和制品。可以利用可以与在逻辑分区中运行的多个虚拟处理器相关联的智能虚拟全局中断队列（虚拟GIQ）。在接收到虚拟中断时，虚拟GIQ可以检查相关联的虚拟处理器的操作状态。为了确保尽可能快地处理虚拟中断，虚拟GIQ可以将虚拟中断呈现给被确定为处于最适合于处理虚拟中断的操作状态的相关虚拟处理器之一。

69. 发明申请

US20060242442A1 Method, apparatus, and product for an efficient virtualized time base in a scaleable multi-processor computer 失效
公开(公告)号：US20060242442A1
公开(公告)日：2006-10-26
申请号：US11110180
申请日：2005-04-20
申请人： William Armstrong , Michael Corrigan , Naresh Nayar , Scott Swaney
发明人： William Armstrong , Michael Corrigan , Naresh Nayar , Scott Swaney
IPC分类号： G06F1/12
CPC分类号： G06F1/14
摘要： A method, apparatus, and computer program product are disclosed in a data processing system for providing a virtualized time base in a logically partitioned data processing system. A time base is determined for each one of multiple processor cores. The time base is used to indicate a current time to one of the processor cores for which the time base is determined. The time bases are synchronized together for the processor cores such that each one of the processor cores includes its own copy of a synchronized time base. For one of the processor cores, a virtualized time base is generated that is different from the synchronized time base but that remains synchronized with at least a portion of the synchronized time base. The processor core utilizes the virtualized time base instead of the synchronized time base for indicating the current time to the processor core. The synchronized time bases and the portion of the virtualized time base remaining in synchronization together.

70. 发明授权

US07000051B2 Apparatus and method for virtualizing interrupts in a logically partitioned computer system 失效
标题翻译：用于虚拟化逻辑分区计算机系统中的中断的装置和方法
公开(公告)号：US07000051B2
公开(公告)日：2006-02-14
申请号：US10403158
申请日：2003-03-31
申请人： William Joseph Armstrong , Richard Louis Arndt , Naresh Nayar
发明人： William Joseph Armstrong , Richard Louis Arndt , Naresh Nayar
IPC分类号： G06F13/24 , G06F9/45
CPC分类号： G06F13/24 , G06F9/45541 , G06F9/4812 , G06F9/5077
摘要： A resource and partition manager virtualizes interrupts without using any additional hardware in a way that does not disturb the interrupt processing model of operating systems running on a logical partition. In other words, the resource and partition manager supports virtual interrupts in a logically partitioned computer system that may include share processors with no changes to a logical partition's operating system. A set of virtual interrupt registers is created for each virtual processor in the system. The resource and partition manager uses the virtual interrupt registers to process interrupts for the corresponding virtual processor. In this manner, from the point of view of the operating system, the interrupt processing when the operating system is running in a logical partition that may contain shared processors and virtual interrupts is no different that the interrupt processing when the operating system is running in computer system that only contains dedicated processor partitions.
摘要翻译：资源和分区管理器以不干扰在逻辑分区上运行的操作系统的中断处理模型的方式，虚拟化中断而不使用任何附加硬件。换句话说，资源和分区管理器支持逻辑分区的计算机系统中的虚拟中断，其可以包括共享处理器，而不改变逻辑分区的操作系统。为系统中的每个虚拟处理器创建一组虚拟中断寄存器。资源和分区管理器使用虚拟中断寄存器来处理相应虚拟处理器的中断。以这种方式，从操作系统的观点来看，当操作系统在可能包含共享处理器和虚拟中断的逻辑分区中运行时的中断处理与操作系统在计算机中运行时的中断处理没有区别只包含专用处理器分区的系统。

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