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61. 发明申请

US20090121291A1 DENSE CHEVRON NON-PLANAR FIELD EFFECT TRANSISTORS AND METHOD 有权
标题翻译： DENSE CHEVRON非平面场效应晶体管和方法
公开(公告)号：US20090121291A1
公开(公告)日：2009-05-14
申请号：US11939574
申请日：2007-11-14
申请人： Brent A. Anderson , Andres Bryant , Edward J. Nowak
发明人： Brent A. Anderson , Andres Bryant , Edward J. Nowak
IPC分类号： H01L27/088 , H01L21/8234
CPC分类号： H01L27/0207 , H01L21/823412 , H01L29/785
摘要： Disclosed are embodiments of semiconductor structure and a method of forming the semiconductor structure that simultaneously maximizes device density and avoids contacted-gate pitch and fin pitch mismatch, when multiple parallel angled fins are formed within a limited area on a substrate and then traversed by multiple parallel gates (e.g., in the case of stacked, chevron-configured, CMOS devices). This is accomplished by using, not a minimum lithographic fin pitch, but rather by using a fin pitch that is calculated as a function of a pre-selected contacted-gate pitch, a pre-selected fin angle and a pre-selected periodic pattern for positioning the fins relative to the gates within the limited area. Thus, the disclosed structure and method allow for the conversion of a semiconductor product design layout with multiple, stacked, planar FETs in a given area into a semiconductor product design layout with multiple, stacked, chevron-configured, non-planar FETs in the same area.
摘要翻译：公开了半导体结构的实施例以及形成半导体结构的方法，其同时使器件密度最大化并避免接触栅极间距和鳍片间距失配，当在衬底上的有限区域内形成多个平行的有角度的鳍片然后穿过多个平行门（例如，在堆叠，人字形配置的CMOS设备的情况下）。这是通过使用而不是最小光刻鳍间距来实现的，而是通过使用根据预先选择的接触栅间距，预选翅片角和预选择的周期性图案计算的鳍间距来实现在有限的区域内相对于门定位翅片。因此，所公开的结构和方法允许将具有给定区域中的多个堆叠的平面FET的半导体产品设计布局转换成具有多个，堆叠的，人造V形的非平面FET的半导体产品设计布局区。

62. 发明申请

US20090020830A1 ASYMMETRIC FIELD EFFECT TRANSISTOR STRUCTURE AND METHOD 有权
标题翻译：不对称场效应晶体管结构与方法
公开(公告)号：US20090020830A1
公开(公告)日：2009-01-22
申请号：US11869145
申请日：2007-10-09
申请人： Brent A. Anderson , Andres Bryant , William F. Clark, JR. , Edward J. Nowak
发明人： Brent A. Anderson , Andres Bryant , William F. Clark, JR. , Edward J. Nowak
IPC分类号： H01L29/78
CPC分类号： H01L29/0847 , H01L29/665 , H01L29/66628 , H01L29/66636 , H01L29/66659 , H01L29/78 , H01L29/7834 , H01L29/7835
摘要： Disclosed are embodiments for a design structure of an asymmetric field effect transistor structure and a method of forming the structure in which both series resistance in the source region (Rs) and gate to drain capacitance (Cgd) are reduced in order to provide optimal performance (i.e., to provide improved drive current with minimal circuit delay). Specifically, different heights of the source and drain regions and/or different distances between the source and drain regions and the gate are tailored to minimize series resistance in the source region (i.e., in order to ensure that series resistance is less than a predetermined resistance value) and in order to simultaneously to minimize gate to drain capacitance (i.e., in order to simultaneously ensure that gate to drain capacitance is less than a predetermined capacitance value).
摘要翻译：公开了用于非对称场效应晶体管结构的设计结构的实施例以及形成其中源极区（Rs）和栅极 - 漏极电容（Cgd）中的串联电阻都被降低以便提供最佳性能（即，以最小的电路延迟来提供改进的驱动电流）。具体地说，源极和漏极区域的不同高度和/或源极和漏极区域与栅极之间的不同距离被调整以最小化源极区域中的串联电阻（即，为了确保串联电阻小于预定电阻值），并且为了同时使栅极 - 漏极电容最小化（即，为了同时确保栅极到漏极电容小于预定的电容值）。

63. 发明授权

US07335932B2 Planar dual-gate field effect transistors (FETs) 失效
标题翻译：平面双栅场效应晶体管（FET）
公开(公告)号：US07335932B2
公开(公告)日：2008-02-26
申请号：US10907745
申请日：2005-04-14
申请人： Brent A. Anderson , Andres Bryant , Edward J. Nowak
发明人： Brent A. Anderson , Andres Bryant , Edward J. Nowak
IPC分类号： H01L29/76
CPC分类号： H01L29/66772 , H01L29/665 , H01L29/78645 , H01L29/78648
摘要： A semiconductor structure and the associated method for fabricating the same. The semiconductor structure includes (a) a semiconductor substrate, (b) a back gate region on the semiconductor substrate, (c) a back gate dielectric region on the back gate region, (d) a semiconductor region on the back gate dielectric region comprising a channel region disposed between first and second source/drain (S/D) regions, (e) a main gate dielectric region on the semiconductor region, (f) a main gate region on the main gate dielectric region, (g) a first contact pad adjacent to the first S/D region and electrically insulated from the back gate region, and (h) a first buried dielectric region that physically and electrically isolates the first contact pad and the back gate region, and wherein the first buried dielectric region has a first thickness in the first direction at least 1.5 times a second thickness of the back gate region.
摘要翻译：半导体结构及其制造方法。半导体结构包括（a）半导体衬底，（b）半导体衬底上的背栅区，（c）背栅区上的背栅电介质区，（d）背栅电介质区上的半导体区，包括设置在第一和第二源极/漏极（S / D）区域之间的沟道区域，（e）半导体区域上的主栅极电介质区域，（f）主栅极电介质区域上的主栅极区域，（g）接触垫，其与所述第一S / D区相邻并且与所述背栅区电绝缘，以及（h）物理地和电隔离所述第一接触焊盘和所述背栅区的第一掩埋介电区，并且其中所述第一掩埋介电区在第一方向上具有至少1.5倍于后栅极区域的第二厚度的第一厚度。

64. 发明授权

US06867460B1 FinFET SRAM cell with chevron FinFET logic 失效
标题翻译： FinFET SRAM单元，采用V形FinFET逻辑
公开(公告)号：US06867460B1
公开(公告)日：2005-03-15
申请号：US10605907
申请日：2003-11-05
申请人： Brent A. Anderson , Andres Bryant , Edward J. Nowak
发明人： Brent A. Anderson , Andres Bryant , Edward J. Nowak
IPC分类号： H01L21/336 , H01L21/8244 , H01L21/84 , H01L27/02 , H01L27/11 , H01L27/12 , H01L29/04 , H01L29/786 , H01L27/01
CPC分类号： H01L29/785 , H01L21/845 , H01L27/0207 , H01L27/11 , H01L27/1104 , H01L27/1211 , H01L29/045 , H01L29/66795 , Y10S257/903
摘要： An electronic device, and SRAM and a method of forming the electronic device and SRAM. The semiconductor device including: a pass gate transistor having a fin body having opposing sidewalls aligned in a first direction and having a first majority carrier mobility and a gate adjacent to both sidewalls of the fin body; a pull down latch transistor having a fin body having opposing sidewalls aligned in a second direction and having a second majority carrier mobility and a gate adjacent to both sidewalls of thc fin body; a pull up latch transistor having a fin body having opposing sidewalls aligned in a third direction and having a third majority carrier mobility and a gate adjacent to both sidewalls of the fin body; and CMOS chevron logic circuits, wherein crystal planes of each fin body and of CMOS transistor of the chevron logic are co-aligned.
摘要翻译：一种电子设备，以及形成电子设备和SRAM的SRAM和方法。该半导体器件包括：通路栅极晶体管，其具有翅片体，其具有沿第一方向排列并且具有第一多数载流子迁移率的相对侧壁和与翅片本体的两个侧壁相邻的栅极; 下拉锁存晶体管，其具有翅片体，其具有沿第二方向对准的具有第二多数载流子迁移率的相对侧壁和与翅片本体的两个侧壁相邻的栅极; 上拉锁存晶体管具有翅片体，其具有在第三方向上对齐的具有第三多数载流子迁移率的相对侧壁和与翅片本体的两个侧壁相邻的栅极; 和CMOS V形逻辑电路，其中每个鳍体的晶面和人字纹逻辑的CMOS晶体管共对齐。

65. 发明授权

US09064974B2 Barrier trench structure and methods of manufacture 有权
标题翻译：阻隔沟槽结构和制造方法
公开(公告)号：US09064974B2
公开(公告)日：2015-06-23
申请号：US13108144
申请日：2011-05-16
申请人： Brent A. Anderson , Andres Bryant , Edward J. Nowak , Jed H. Rankin
发明人： Brent A. Anderson , Andres Bryant , Edward J. Nowak , Jed H. Rankin
IPC分类号： H01L27/092 , H01L21/84 , H01L21/762 , H01L27/12 , H01L21/8234
CPC分类号： H01L27/092 , H01L21/76283 , H01L21/823481 , H01L21/84 , H01L27/1203 , H01L29/0642
摘要： A method includes forming at least one shallow trench isolation structure in a substrate to isolate adjacent different type devices. The method further includes forming a barrier trench structure in the substrate to isolate diffusions of adjacent same type devices. The method further includes spanning the barrier trench structure with material to connect the diffusions of the adjacent same type device, on a same level as the adjacent same type devices.
摘要翻译：一种方法包括在衬底中形成至少一个浅沟槽隔离结构以隔离相邻的不同类型的器件。该方法还包括在衬底中形成阻挡沟槽结构以隔离相邻相同类型器件的扩散。该方法进一步包括将阻挡沟槽结构与材料连接，以将相邻相同类型器件的扩散连接在与相邻相同类型器件相同的水平上。

66. 发明申请

US20130154003A1 ASYMMETRIC ANTI-HALO FIELD EFFECT TRANSISTOR 审中-公开
标题翻译：不对称抗HALO场效应晶体管
公开(公告)号：US20130154003A1
公开(公告)日：2013-06-20
申请号：US13329440
申请日：2011-12-19
申请人： James W. Adkisson , Brent A. Anderson , Andres Bryant , Edward J. Nowak
发明人： James W. Adkisson , Brent A. Anderson , Andres Bryant , Edward J. Nowak
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/26586 , H01L29/1045 , H01L29/66492 , H01L29/66583 , H01L29/6659 , H01L29/66659 , H01L29/7835
摘要： A method of forming an integrated circuit structure implants a first compensating implant into a substrate. The method patterns a mask on the first compensating implant in the substrate. The mask includes an opening exposing a channel location of the substrate. The method implants a second compensating implant into the channel location of the substrate. The second compensating implant is made through the opening in the mask and at an angle that is offset from perpendicular to the top surface of the substrate. The second compensating implant is positioned closer to a first side of the channel location relative to an opposite second side of the channel location and the second compensating implant comprises a material having the same doping polarity as the semiconductor channel implant. Then, the method forms a gate conductor above the channel location of the substrate in the opening of the mask.
摘要翻译：形成集成电路结构的方法将第一补偿植入物植入衬底。该方法在衬底中的第一补偿植入物上形成掩模。掩模包括暴露基板的通道位置的开口。该方法将第二补偿植入物植入衬底的通道位置。第二补偿植入物通过掩模中的开口并以与衬底的顶表面垂直的角度形成。第二补偿植入件相对于沟道位置的相对的第二侧被定位成更靠近通道位置的第一侧，并且第二补偿植入物包括具有与半导体沟道植入物相同的掺杂极性的材料。然后，该方法在掩模的开口中在衬底的通道位置之上形成栅极导体。

67. 发明授权

US08217456B1 Low capacitance hi-K dual work function metal gate body-contacted field effect transistor 有权
标题翻译：低电容hi-K双功能金属门体接触场效应晶体管
公开(公告)号：US08217456B1
公开(公告)日：2012-07-10
申请号：US13046084
申请日：2011-03-11
申请人： Brent A. Anderson , Andres Bryant , Edward J. Nowak
发明人： Brent A. Anderson , Andres Bryant , Edward J. Nowak
IPC分类号： H01L29/778
CPC分类号： H01L29/78615 , H01L29/42384
摘要： Disclosed herein is a field effect transistor (FET), device including a FET, and a method of making the same. In embodiments of the disclosure, a semiconductor-on-insulator (SOI) substrate is provided. The SOI substrate includes a body having a first conductivity type formed in the semiconductor layer of the SOI substrate, the body including a first body region connecting a second body region to a third body region; and a source and a drain, each having a second conductivity type, disposed on opposite sides of the first body region. A first gate electrode having a second work function is disposed above the first body region; and a second gate electrode having a first work function disposed above the second and third body regions. A first gate dielectric layer may be disposed vertically between the first body region and the first gate electrode, and a second gate dielectric layer may be disposed vertically between the second and third body regions and the second gate electrode. The first and second gate electrodes have different work functions.
摘要翻译：本文公开了一种场效应晶体管（FET），包括FET的器件及其制造方法。在本公开的实施例中，提供绝缘体上半导体（SOI）衬底。 SOI衬底包括形成在SOI衬底的半导体层中的具有第一导电类型的主体，该主体包括将第二主体区域连接到第三主体区域的第一主体区域; 以及源极和漏极，每个具有第二导电类型，设置在第一体区的相对侧上。具有第二功函数的第一栅电极设置在第一体区的上方; 以及第二栅电极，其具有设置在第二和第三体区之上的第一功函数。第一栅极电介质层可以垂直地设置在第一体区域和第一栅电极之间，并且第二栅极电介质层可以垂直地设置在第二和第三体区域与第二栅电极之间。第一和第二栅电极具有不同的功函数。

68. 发明授权

US07981772B2 Methods of fabricating nanostructures 失效
标题翻译：制造纳米结构的方法
公开(公告)号：US07981772B2
公开(公告)日：2011-07-19
申请号：US12344696
申请日：2008-12-29
申请人： Brent A. Anderson , Andres Bryant , Edward J. Nowak , Jeffrey W. Sleight
发明人： Brent A. Anderson , Andres Bryant , Edward J. Nowak , Jeffrey W. Sleight
IPC分类号： H01L21/3213
CPC分类号： H01L29/0665 , B82Y10/00 , H01L29/0669 , H01L29/0673 , H01L29/16 , H01L29/161 , Y10S977/888
摘要： A method is shown for fabricating nanostructures, and more particularly, to methods of fabricating silicon nanowires. The method of manufacturing a nanowire includes forming a sandwich structure of SiX material and material Si over a substrate and etching the sandwich structure to expose sidewalls of the Si material and the SiX material. The method further includes etching the SiX material to expose portions of the Si material and etching the exposed portions of the Si material. The method also includes breaking away the Si material to form silicon nanowires.
摘要翻译：示出了制造纳米结构的方法，更具体地说，涉及制造硅纳米线的方法。制造纳米线的方法包括在衬底上形成SiX材料和材料Si的夹层结构，并蚀刻夹层结构以暴露Si材料和SiX材料的侧壁。该方法还包括蚀刻SiX材料以暴露Si材料的部分并蚀刻Si材料的暴露部分。该方法还包括分离Si材料以形成硅纳米线。

69. 发明授权

US07971158B2 Spacer fill structure, method and design structure for reducing device variation 失效
标题翻译：间隔填充结构，减少装置变化的方法和设计结构
公开(公告)号：US07971158B2
公开(公告)日：2011-06-28
申请号：US12144004
申请日：2008-06-23
申请人： Brent A. Anderson , Andres Bryant , Edward J. Nowak , Jed H. Rankin
发明人： Brent A. Anderson , Andres Bryant , Edward J. Nowak , Jed H. Rankin
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/12 , Y02P90/265
摘要： A design structure is provided for spacer fill structures and, more particularly, spacer fill structures, a method of manufacturing and a design structure for reducing device variation is provided. The structure includes a plurality of dummy fill shapes in different areas of a device which are configured such that gate perimeter to gate area ratio will result in a total perimeter density being uniform across a chip.
摘要翻译：提供了用于间隔物填充结构的设计结构，并且更具体地，提供了间隔件填充结构，制造方法和用于减小装置变化的设计结构。该结构包括在器件的不同区域中的多个虚拟填充形状，其被配置为使得栅极周边与栅极面积比将导致芯片上的总周长密度是均匀的。

70. 发明授权

US07943997B2 Fully-depleted low-body doping field effect transistor (FET) with reverse short channel effects (SCE) induced by self-aligned edge back-gate(s) 有权
标题翻译：具有由自对准边缘后栅极引起的反向短沟道效应（SCE）的全耗尽低体积掺杂场效应晶体管（FET）
公开(公告)号：US07943997B2
公开(公告)日：2011-05-17
申请号：US12104683
申请日：2008-04-17
申请人： James W. Adkisson , Brent A. Anderson , Andres Bryant , William F. Clark, Jr. , Edward J. Nowak
发明人： James W. Adkisson , Brent A. Anderson , Andres Bryant , William F. Clark, Jr. , Edward J. Nowak
IPC分类号： H01L27/12
CPC分类号： H01L29/78603 , H01L29/66621 , H01L29/78645 , H01L29/78648 , H01L29/78696
摘要： Disclosed are embodiments of a field effect transistor (FET) and, more particularly, a fully-depleted, thin-body (FDTB) FET that allows for scaling with minimal short channel effects, such as drain induced barrier lowering (DIBL) and saturation threshold voltage (Vtsat) roll-off, at shorter channel lengths. The FDTB FET embodiments are configured with either an edge back-gate or split back-gate that can be biased in order to selectively adjust the potential barrier between the source/drain regions and the channel region for minimizing off-state leakage current between the drain region and the source region and/or for varying threshold voltage. These unique back-gate structures avoid the need for halo doping to ensure linear threshold voltage (Vtlin) roll-up at smaller channel lengths and, thus, avoid across-chip threshold voltage variations due to random doping fluctuations. Also disclosed are method embodiments for forming such FETs.
摘要翻译：公开了场效应晶体管（FET）的具体实施例，更具体地说，是允许以最小的短沟道效应（例如漏极感应势垒降低（DIBL）和饱和阈值））进行缩放的完全耗尽的薄体（FDTB）FET 电压（Vtsat）滚降，通道长度较短。 FDTB FET实施例配置有可被偏置的边缘背栅极或分支反向栅极，以便选择性地调节源极/漏极区域和沟道区域之间的势垒，以最小化漏极之间的截止状态漏电流区域和源极区域和/或用于改变阈值电压。这些独特的背栅结构避免了对光晕掺杂的需要，以确保较小通道长度的线性阈值电压（Vtlin）汇总，从而避免由于随机掺杂波动引起的跨芯片阈值电压变化。还公开了用于形成这种FET的方法实施例。

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