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61. 发明申请

US20050236001A1 Bridle catheter with umbilical tape 有权
标题翻译： Bridle导管带脐带
公开(公告)号：US20050236001A1
公开(公告)日：2005-10-27
申请号：US11113471
申请日：2005-04-25
申请人： Derek Williams
发明人： Derek Williams
IPC分类号： A61J15/00 , A61M15/00 , A61M16/00 , A61M25/01 , A61M25/02
CPC分类号： A61M25/02 , A61M2025/0008 , A61M2025/0226 , A61M2210/0618
摘要： A nasal tube retaining system having a flexible member with a magnet attached to the first end for insertion into the first nostril of the patient, a tape portion attached to an end of the flexible member, a guide for guiding the tape portion through a portion or all of the flexible member, a rod, and a retrieving member with a magnetic distal end for insertion into the second nostril of the patient to retrieve the flexible member. The system further includes a fastening means to secure the nasal tube to the tape portion.
摘要翻译：一种具有柔性构件的鼻管保持系统，其具有附接到第一端的磁体，用于插入到患者的第一鼻孔中，附接到柔性构件的端部的带部分，用于引导带部分穿过部分的引导件所有柔性构件，杆和具有磁性远端的回收构件，用于插入到患者的第二鼻孔中以取回柔性构件。该系统还包括用于将鼻管固定到带部分的紧固装置。

62. 发明授权

US4390738A Process for the oxidation of olefinic compounds to olefine oxides or derivatives thereof 失效
标题翻译：将烯烃化合物氧化成烯烃氧化物或其衍生物的方法
公开(公告)号：US4390738A
公开(公告)日：1983-06-28
申请号：US274797
申请日：1981-06-18
申请人： Dhafir Y. Waddan , Derek Williams
发明人： Dhafir Y. Waddan , Derek Williams
IPC分类号： B01J31/00 , C07B61/00 , C07C27/00 , C07C29/03 , C07C29/48 , C07C29/50 , C07C31/20 , C07C33/035 , C07C67/00 , C07D301/06 , C07D301/08 , C07C33/04
CPC分类号： C07C29/03 , C07C29/50 , C07D301/06 , C07D301/08 , Y02P20/52
摘要： Olefine oxides or derivatives thereof such as glycols are produced by reacting an olefinic compound e.g. ethylene, propylene or butadiene with oxygen in the presence of a catalyst containing copper bonded to a peroxo group.
摘要翻译：烯烃氧化物或其衍生物如二醇是通过使烯属化合物例如乙烯，丙烯或丁二烯在含有键合至过氧基团的铜的催化剂存在下进行。

63. 发明授权

US4339234A Drive cam and follower for a liquid fuel injection pumping apparatus 失效
标题翻译：用于液体燃料喷射泵送装置的驱动凸轮和跟随器
公开(公告)号：US4339234A
公开(公告)日：1982-07-13
申请号：US165673
申请日：1980-07-03
申请人： Derek Williams
发明人： Derek Williams
IPC分类号： F02M59/26 , F02M59/10 , F02M59/44 , F04B39/00 , F16H25/14
CPC分类号： F02M59/102 , F02M59/44 , Y10T74/18296 , Y10T74/2101
摘要： A liquid fuel injection pumping apparatus comprises a reciprocable pump plunger operable by a tappet assembly and a rotary cam. The tappet assembly includes a cylindrical body slidable within a bore, the body carrying a cross pin which supports a roller engageable with the cam. The cross pin has reclined ends so that if it moves axially while exposed beyond the end of the bore it will engage the bore and move axially to its correct position. With cams designed to give maximum plunger movement the pin is exposed for an appreciable time and heavy wear of the pin and bore can occur. The cam is therefore designed to allow outward movement of the plunger but then to hold the plunger until just before inward movement of the plunger is required to take place. Whilst the plunger is held the filling port of the pump is at least partly uncovered. The cam has a trailing flank which comprises a first part during which the plunger can move outwardly, a second part during which the plunger is held against outward movement and a third part which allows the full outward movement.
摘要翻译：液体燃料喷射泵送装置包括由挺杆组件和旋转凸轮可操作的可往复运动的泵柱塞。挺杆组件包括可在孔内滑动的圆柱形主体，该主体承载支撑可与凸轮啮合的滚子的十字销。十字销具有倾斜的端部，使得如果其在暴露于孔的端部之前轴向移动，则其将接合孔并且轴向移动到其正确位置。通过设计用于提供最大柱塞移动的凸轮，销被暴露出可观的时间，并且可能发生销和孔的严重磨损。因此，凸轮被设计成允许柱塞的向外运动，然后保持柱塞，直到需要进行柱塞的向内运动之前。当柱塞保持时，泵的填充口至少部分地不被覆盖。凸轮具有后缘，其包括第一部分，在该第一部分期间柱塞可以向外移动;第二部分，其中柱塞被保持抵抗向外的运动;第三部分允许完全向外运动。

64. 发明申请

US20100024887A1 AIR PURGE COLLAR 有权
公开(公告)号：US20100024887A1
公开(公告)日：2010-02-04
申请号：US12183647
申请日：2008-07-31
申请人： Derek Williams , Gary Garnier , Kent Stemer , Paul Carlson
发明人： Derek Williams , Gary Garnier , Kent Stemer , Paul Carlson
IPC分类号： F15D1/10 , F24F7/007 , G05D7/01 , F15D1/00
CPC分类号： F15D1/00 , G01N2021/151 , Y10T137/0324 , Y10T137/2082 , Y10T137/2224
摘要： An air purge apparatus and method is presented to protect an imaging system from contamination by particulate matter and other substances in the ambient environment. The apparatus is adapted to be placed adjacent to a viewing window, lens or optics of an imaging system and to provide a protective flow of air. The apparatus includes a curved surface to direct air from a first plenum toward an imaging path in front of the apparatus. The apparatus also includes one or more openings nearer the lens to direct air from a second plenum into the imaging path. The air from the first plenum entrains air from the second plenum and ambient air to create a fluid stream away from the viewing window, lens, or optics and may form a fluid barrier to reduce contamination of a volume of air in the imaging path of the imaging sensor.
摘要翻译：提供了一种空气净化装置和方法，以保护成像系统免受周围环境中的颗粒物质和其他物质的污染。该装置适于放置成与成像系统的观察窗，透镜或光学元件相邻并且提供保护性空气流。该装置包括弯曲表面，用于将来自第一集气室的空气引向装置前面的成像路径。该设备还包括靠近透镜的一个或多个开口以将空气从第二增压室引导到成像路径中。来自第一增压室的空气带动来自第二增压室和环境空气的空气以产生远离观察窗，透镜或光学器件的流体流，并且可以形成流体屏障，以减少成像路径中的空气体积的污染成像传感器。

65. 发明申请

US20080098177A1 Data Processing System and Method for Efficient L3 Cache Directory Management 有权
标题翻译：数据处理系统和高效L3缓存目录管理方法
公开(公告)号：US20080098177A1
公开(公告)日：2008-04-24
申请号：US11956112
申请日：2007-12-13
申请人： Guy Guthrie , William Starke , Derek Williams , Philip Williams
发明人： Guy Guthrie , William Starke , Derek Williams , Philip Williams
IPC分类号： G06F12/00
CPC分类号： G06F12/0811 , G06F12/0831 , G06F12/128 , G06F2212/2542
摘要： A system and method for cache management in a data processing system having a memory hierarchy of upper memory and lower memory cache. A lower memory cache controller accesses a coherency state table to determine replacement policies of coherency states for cache lines present in the lower memory cache when receiving a cast-in request from one of the upper memory caches. The coherency state table implements a replacement policy that retains the more valuable cache coherency state information between the upper and lower memory caches for a particular cache line contained in both levels of memory at the time of cast-out from the upper memory cache.
摘要翻译：一种用于在具有上部存储器和下部存储器高速缓存的存储器层级的数据处理系统中的高速缓存管理的系统和方法。较低的存储器高速缓存控制器访问一致性状态表以确定当从上部存储器高速缓存中的一个接收到转入请求时存在于下部存储器高速缓存中的高速缓存行的一致性状态的替换策略。一致性状态表实现替换策略，其在从上部存储器高速缓存中拔出时，在包含在两个级别的存储器中的特定高速缓存行的上下存储器高速缓存之间保留更有价值的高速缓存一致性状态信息。

66. 发明申请

US20080077744A1 Reducing Number of Rejected Snoop Requests By Extending Time To Respond To Snoop Request 失效
标题翻译：通过延长响应Snoop请求的时间减少被拒绝的侦听请求数
公开(公告)号：US20080077744A1
公开(公告)日：2008-03-27
申请号：US11950717
申请日：2007-12-05
申请人： Benjiman Goodman , Guy Guthrie , William Starke , Jeffrey Stuecheli , Derek Williams
发明人： Benjiman Goodman , Guy Guthrie , William Starke , Jeffrey Stuecheli , Derek Williams
IPC分类号： G06F13/28
CPC分类号： G06F12/0831
摘要： A cache, system and method for reducing the number of rejected snoop requests. A “stall/reorder unit” in a cache receives a snoop request from an interconnect. Information, such as the address, of the snoop request is stored in a queue of the stall/reorder unit. The stall/reorder unit forwards the snoop request to a selector which also receives a request from a processor. An arbitration mechanism selects either the snoop request or the request from the processor. If the snoop request is denied by the arbitration mechanism, information, e.g., address, about the snoop request may be maintained in the stall/reorder unit. The request may be later resent to the selector. This process may be repeated up to “n” clock cycles. By providing the snoop request additional opportunities (n clock cycles) to be accepted by the arbitration mechanism, fewer snoop requests may ultimately be denied.
摘要翻译：用于减少拒绝的窥探请求数量的缓存，系统和方法。缓存中的“停止/重新排序单元”从互连中接收窥探请求。窥探请求的诸如地址的信息被存储在失速/重新排序单元的队列中。停止/重新排序单元将窥探请求转发到也从处理器接收请求的选择器。仲裁机制选择来自处理器的窥探请求或请求。如果侦听请求被仲裁机制拒绝，关于窥探请求的信息（例如地址）可以被保留在停止/重新排序单元中。请求可能会稍后重新发送到选择器。该过程可以重复直到“n”个时钟周期。通过提供窥探请求仲裁机制接受的额外机会（n个时钟周期），最终可能会拒绝更少的侦听请求。

67. 发明申请

US20080040556A1 Data processing system and method for efficient communication utilizing an Tn and Ten coherency states 有权
标题翻译：数据处理系统和利用Tn和10相关性状态的高效通信方法
公开(公告)号：US20080040556A1
公开(公告)日：2008-02-14
申请号：US11835984
申请日：2007-08-08
申请人： James Fields , Benjiman Goodman , Guy Guthrie , William Starke , Derek Williams
发明人： James Fields , Benjiman Goodman , Guy Guthrie , William Starke , Derek Williams
IPC分类号： G06F12/08
CPC分类号： G06F12/0817 , G06F12/0831 , G06F12/084
摘要： A cache coherent data processing system includes at least first and second coherency domains each including at least one processing unit. The first coherency domain includes a first cache memory and a second cache memory, and the second coherency domain includes a remote coherent cache memory. The first cache memory includes a cache controller, a data array including a data storage location for caching a memory block, and a cache directory. The cache directory includes a tag field for storing an address tag in association with the memory block and a coherency state field associated with the tag field and the data storage location. The coherency state field has a plurality of possible states including a state that indicates that the memory block is possibly shared with the second cache memory in the first coherency domain and cached only within the first coherency domain.
摘要翻译：高速缓存一致数据处理系统至少包括第一和第二相关域，每个域包括至少一个处理单元。第一相关域包括第一高速缓存存储器和第二高速缓冲存储器，并且第二相干域包括远程一致高速缓存存储器。第一高速缓存存储器包括高速缓存控制器，包括用于高速缓存存储器块的数据存储位置的数据阵列和高速缓存目录。缓存目录包括用于存储与存储器块相关联的地址标签的标签字段和与标签字段和数据存储位置相关联的一致性状态字段。相关性状态字段具有多个可能的状态，包括指示存储器块可能与第一相关域中的第二高速缓冲存储器共享并且仅在第一相干域内缓存的状态。

68. 发明申请

US20070226423A1 Processor, data processing system, and method for initializing a memory block in a data processing system having multiple coherency domains 有权
标题翻译：处理器，数据处理系统和用于初始化具有多个相干域的数据处理系统中的存储器块的方法
公开(公告)号：US20070226423A1
公开(公告)日：2007-09-27
申请号：US11388001
申请日：2006-03-23
申请人： Ravi Arimilli , Guy Guthrie , William Starke , Derek Williams
发明人： Ravi Arimilli , Guy Guthrie , William Starke , Derek Williams
IPC分类号： G06F13/28
CPC分类号： G06F12/0822 , G06F12/084
摘要： A data processing system includes at least first and second coherency domains, each including at least one processor core and a memory. In response to an initialization operation by a processor core that indicates a target memory block to be initialized, a cache memory in the first coherency domain determines a coherency state of the target memory block with respect to the cache memory. In response to the determination, the cache memory selects a scope of broadcast of an initialization request identifying the target memory block. A narrower scope including the first coherency domain and excluding the second coherency domain is selected in response to a determination of a first coherency state, and a broader scope including the first coherency domain and the second coherency domain is selected in response to a determination of a second coherency state. The cache memory then broadcasts an initialization request with the selected scope. In response to the initialization request, the target memory block is initialized within a memory of the data processing system to an initialization value.
摘要翻译：数据处理系统至少包括第一和第二相干域，每个域包括至少一个处理器核和存储器。响应于指示要初始化的目标存储器块的处理器核心的初始化操作，第一相干域中的高速缓存存储器确定目标存储器块相对于高速缓冲存储器的一致性状态。响应于该确定，高速缓存存储器选择识别目标存储器块的初始化请求的广播范围。响应于第一相关性状态的确定而选择包括第一相关域并且排除第二相关性域的较窄范围，并且响应于确定第一相关性域的第一相关性域和第二相关域第二一致性状态。然后，高速缓冲存储器播放具有所选范围的初始化请求。响应于初始化请求，将目标存储器块在数据处理系统的存储器内初始化为初始化值。

69. 发明申请

US20060265553A1 Processor, data processing system, and method for initializing a memory block 失效
标题翻译：处理器，数据处理系统以及初始化存储器块的方法
公开(公告)号：US20060265553A1
公开(公告)日：2006-11-23
申请号：US11130907
申请日：2005-05-17
申请人： Ravi Arimilli , Derek Williams
发明人： Ravi Arimilli , Derek Williams
IPC分类号： G06F13/28
CPC分类号： G06F12/0831
摘要： In response to receiving an initialization operation from an associated processor core that indicates a target memory block to be initialized, a cache memory determines a coherency state of the target memory block. In response to a determination that the target memory block has a data-invalid coherency state with respect to the cache memory, the cache memory issues on a interconnect a corresponding initialization request indicating the target memory block. In response to the initialization request, the target memory block is initialized within a memory of the data processing system to an initialization value. The target memory block may thus be initialized without the cache memory holding a valid copy of the target memory block.
摘要翻译：响应于从指示要初始化的目标存储器块的相关联的处理器核心接收到初始化操作，高速缓存存储器确定目标存储器块的一致性状态。响应于目标存储器块相对于高速缓冲存储器具有数据无效一致性状态的确定，高速缓冲存储器在互连上发出指示目标存储器块的对应的初始化请求。响应于初始化请求，将目标存储器块在数据处理系统的存储器内初始化为初始化值。因此，可以初始化目标存储器块，而不使高速缓冲存储器保持目标存储器块的有效副本。

70. 发明申请

US20060236037A1 Cache memory, processing unit, data processing system and method for assuming a selected invalid coherency state based upon a request source 有权
标题翻译：高速缓冲存储器，处理单元，数据处理系统和方法，用于基于请求源假设所选择的无效一致性状态
公开(公告)号：US20060236037A1
公开(公告)日：2006-10-19
申请号：US11109085
申请日：2005-04-19
申请人： Guy Guthrie , Aaron Sawdey , William Starke , Derek Williams
发明人： Guy Guthrie , Aaron Sawdey , William Starke , Derek Williams
IPC分类号： G06F13/28
CPC分类号： G06F12/0811 , G06F12/0813 , G06F12/0831
摘要： At a first cache memory affiliated with a first processor core, an exclusive memory access operation is received via an interconnect fabric coupling the first cache memory to second and third cache memories respectively affiliated with second and third processor cores. The exclusive memory access operation specifies a target address. In response to receipt of the exclusive memory access operation, the first cache memory detects presence or absence of a source indication indicating that the exclusive memory access operation originated from the second cache memory to which the first cache memory is coupled by a private communication network to which the third cache memory is not coupled. In response to detecting presence of the source indication, a coherency state field of the first cache memory that is associated with the target address is updated to a first data-invalid state. In response to detecting absence of the source indication, the coherency state field of the first cache memory is updated to a different second data-invalid state.
摘要翻译：在与第一处理器核心相关联的第一高速缓冲存储器处，通过将第一高速缓冲存储器耦合到分别隶属于第二和第三处理器核的第二和第三高速缓冲存储器的互连结构接收独占存储器存取操作。独占内存访问操作指定目标地址。响应于独占存储器访问操作的接收，第一高速缓存存储器检测是否存在指示来自第一高速缓存存储器的专用存储器访问操作的源指示由第一高速缓冲存储器通过专用通信网络耦合到第三缓存存储器未被耦合。响应于检测到源指示的存在，与目标地址相关联的第一高速缓冲存储器的一致性状态字段被更新为第一数据无效状态。响应于检测到不存在源指示，将第一高速缓冲存储器的一致性状态字段更新为不同的第二数据无效状态。

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