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61. 发明授权

US06458662B1 Method of fabricating a semiconductor device having an asymmetrical dual-gate silicon-germanium (SiGe) channel MOSFET and a device thereby formed 有权
标题翻译：制造具有非对称双栅硅锗（SiGe）沟道MOSFET的半导体器件的方法和由此形成的器件
公开(公告)号：US06458662B1
公开(公告)日：2002-10-01
申请号：US09826551
申请日：2001-04-04
申请人： Bin Yu
发明人： Bin Yu
IPC分类号： H01L21336
CPC分类号： H01L29/78687 , H01L29/66795 , H01L29/785
摘要： A method of fabricating a semiconductor device, having an asymmetrical dual-gate MOSFET with a silicon-germanium (SiGe) channel, involving: patterning a silicon-on-insulator (SOI) wafer with a photoreist layer, wherein the SOI structure comprises a silicon dioxide (SiO2) layer, a silicon (Si) layer deposited on the SiO2 layer, and a silicon nitride (Si3N4) layer deposited on the Si layer; initiating formation of a SiGe/Si/SiGe sandwich fin structure from the SOI structure; completing formation of the SiGe/Si/SiGe sandwich fin structure; depositing a thick gate material layer on the SiGe/Si/SiGe sandwich fin structure; forming an asymmetrical dual-gate; and completing fabrication of the semiconductor device, and a device thereby formed.
摘要翻译：一种制造具有硅 - 锗（SiGe）沟道的非对称双栅极MOSFET的半导体器件的方法，包括：利用光刻层构图绝缘体上硅（SOI）晶片，其中SOI结构包括硅二氧化硅（SiO 2）层，沉积在SiO 2层上的硅（Si）层和沉积在Si层上的氮化硅（Si 3 N 4）层; 从SOI结构开始形成SiGe / Si / SiGe夹层结构; 完成SiGe / Si / SiGe夹层结构的形成; 在SiGe / Si / SiGe夹层结构上沉积厚栅极材料层; 形成不对称双门; 并完成半导体器件的制造，以及由此形成的器件。

62. 发明授权

US06451656B1 CMOS inverter configured from double gate MOSFET and method of fabricating same 有权
标题翻译：由双栅MOSFET配置的CMOS反相器及其制造方法
公开(公告)号：US06451656B1
公开(公告)日：2002-09-17
申请号：US09796283
申请日：2001-02-28
申请人： Bin Yu , William G. En
发明人： Bin Yu , William G. En
IPC分类号： H01L21336
CPC分类号： H01L29/66742 , H01L21/84 , H01L27/1203
摘要： A method of forming a semiconductor line from a semiconductor-on-insulator (SOI) wafer, the SOI wafer having a substrate with a buried oxide (BOX) layer disposed thereon and a semiconductor active layer disposed on the BOX layer. The method includes the steps of (a) forming a dummy island on the active layer; (b) forming a sidewall spacer adjacent the dummy island; (c) removing the dummy island; (d) removing semiconductor material of the active layer left exposed by the sidewall spacer; and (e) removing the sidewall spacer.
摘要翻译：一种从绝缘体上半导体（SOI）晶片形成半导体线的方法，SOI晶片具有设置在其上的掩埋氧化物（BOX）层的基板和设置在BOX层上的半导体有源层。该方法包括以下步骤：（a）在有源层上形成虚拟岛; （b）形成靠近所述假岛的侧壁间隔物; （c）去除虚岛; （d）去除由侧壁间隔物露出的有源层的半导体材料; 和（e）去除侧壁间隔物。

63. 发明授权

US06423647B1 Formation of dielectric regions of different thicknesses at selective location areas during laser thermal processes 失效
标题翻译：在激光热处理期间在选择性位置区域形成不同厚度的电介质区域
公开(公告)号：US06423647B1
公开(公告)日：2002-07-23
申请号：US09734291
申请日：2000-12-11
申请人： Bin Yu
发明人： Bin Yu
IPC分类号： H01L2131
CPC分类号： H01L21/823462 , H01L21/31662
摘要： For fabricating regions of dielectric material on a semiconductor substrate, a first layer of metal is deposited on the semiconductor substrate, and a first opening is etched through the first layer of metal at a first location area on the semiconductor substrate. First laser beams having a first laser power are directed toward the semiconductor substrate to form a first region of dielectric material having a first thickness at the first location area on the semiconductor substrate. The first layer of metal reflects the first laser beams away from the semiconductor substrate except at the first location area, and the first thickness of the first region of dielectric material is determined by the first laser power of the first laser beams. The first layer of metal is removed from the semiconductor substrate. A second layer of metal is then deposited on the semiconductor substrate, and a second opening is etched through the second layer of metal at a second location area on the semiconductor substrate. Second laser beams having a second laser power is directed toward the semiconductor substrate to form a second region of dielectric material having a second thickness at the second location area on the semiconductor substrate. The second layer of metal reflects the second laser beams away from the semiconductor substrate except at the second location area, and the second thickness of the second region of dielectric material is determined by the second laser power of the second laser beams. The second layer of metal is then removed from the semiconductor substrate. The present invention may be used to particular advantage when the first thickness of the first region of dielectric material is different from the second thickness of the second region of dielectric material.
摘要翻译：为了在半导体衬底上制造介电材料区域，在半导体衬底上沉积第一金属层，并且在半导体衬底上的第一位置区域，通过第一金属层蚀刻第一开口。具有第一激光功率的第一激光束被引向半导体衬底，以在半导体衬底上的第一位置区域形成具有第一厚度的介电材料的第一区域。第一金属层将第一激光束反射离开第一位置区域之外的半导体衬底，并且第一区域的第一厚度由第一激光束的第一激光功率决定。从半导体衬底去除第一金属层。然后在半导体衬底上沉积第二层金属，并且在半导体衬底上的第二位置区域，通过第二金属层蚀刻第二开口。具有第二激光功率的第二激光束指向半导体衬底，以在半导体衬底上的第二位置区域形成具有第二厚度的介电材料的第二区域。第二层金属将第二激光束反射离开第二位置区域以外的半导体衬底，并且第二区域的第二厚度由第二激光束的第二激光功率决定。然后从半导体衬底去除第二层金属。当电介质材料的第一区域的第一厚度不同于介电材料的第二区域的第二厚度时，本发明可被用于特别有利。

64. 发明授权

US06423599B1 Method for fabricating a field effect transistor having dual gates in SOI (semiconductor on insulator) technology 有权
标题翻译：在SOI（绝缘体上半导体）技术中制造具有双栅极的场效应晶体管的方法
公开(公告)号：US06423599B1
公开(公告)日：2002-07-23
申请号：US09846793
申请日：2001-05-01
申请人： Bin Yu
发明人： Bin Yu
IPC分类号： H01L21336
CPC分类号： H01L29/66772 , H01L29/78648
摘要： For fabricating a field effect transistor having dual gates, on a buried insulating layer in SOI (semiconductor on insulator) technology, a first layer of first semiconductor material is deposited on the buried insulating material. The first layer of first semiconductor material is patterned to form a first semiconductor island having a first top surface and a second semiconductor island having a second top surface. The first and second semiconductor islands are comprised of the first semiconductor material. An insulating material is deposited to surround the first and second semiconductor islands, and the insulating material is polished down until the first and second top surfaces of the first and second semiconductor islands are exposed such that sidewalls of the first and second semiconductor islands are surrounded by the insulating material. A gate dopant is implanted into the second semiconductor island. A layer of back gate dielectric material is deposited on the first and second top surfaces of the first and second semiconductor islands. An opening is patterned through the layer of back gate dielectric material above the first semiconductor island such that a bottom wall of the opening is formed by the first top surface of the first semiconductor island. A second layer of second semiconductor material is grown from the exposed first top surface of the first semiconductor island and onto the layer of back gate dielectric material. A front gate dielectric is formed over a portion of the second layer of second semiconductor material disposed over the second semiconductor island. A front gate electrode is formed over the front gate dielectric. The second semiconductor island forms a back gate electrode, and a portion of the layer of back gate dielectric material under the front gate dielectric forms a back gate dielectric.
摘要翻译：为了制造具有双栅极的场效应晶体管，在SOI（绝缘体上半导体）技术的掩埋绝缘层上，第一半导体材料层沉积在掩埋绝缘材料上。第一层第一半导体材料被图案化以形成具有第一顶表面的第一半导体岛和具有第二顶表面的第二半岛。第一和第二半导体岛由第一半导体材料组成。沉积绝缘材料以包围第一和第二半导体岛，并且绝缘材料被抛光直到第一和第二半导体岛的第一和第二顶表面被暴露，使得第一和第二半导体岛的侧壁被绝缘材料。将栅极掺杂剂注入第二半导体岛。一层背栅介质材料沉积在第一和第二半导体岛的第一和第二顶表面上。通过第一半导体岛上方的背栅介质材料层图案化开口，使得开口的底壁由第一半导体岛的第一顶表面形成。第二层第二半导体材料从第一半导体岛的暴露的第一顶表面生长到背栅电介质材料层上。在位于第二半导体岛上的第二半导体材料的第二层的一部分上形成前栅极电介质。前栅电极形成在前栅极电介质上。第二半导体岛形成背栅电极，并且在前栅极电介质下方的背栅介质材料层的一部分形成背栅电介质。

65. 发明授权

US06420767B1 Capacitively coupled DTMOS on SOI 有权
标题翻译：在SOI上电容耦合DTMOS
公开(公告)号：US06420767B1
公开(公告)日：2002-07-16
申请号：US09605920
申请日：2000-06-28
申请人： Srinath Krishnan , John C. Holst , Bin Yu
发明人： Srinath Krishnan , John C. Holst , Bin Yu
IPC分类号： H01L2976
CPC分类号： H01L29/78621 , H01L29/7841 , H01L29/78612
摘要： A transistor structure is provided comprising a source region having a N+ source region and a N− lightly doped source region. The structure also comprises a drain region having a N+ drain region and a N− lightly doped drain region. A P++ heavily doped region is provided. The P++ region resides alongside at least a portion of at least one of the N− lightly doped source region and N− lightly doped drain region. A P+ body region resides below a gate of the device and between the source and drain regions. The P+⇄ heavily doped region provides a capacitive coupling between a body region and the gate of the device and form a capacitive voltage divider with the junction capacitance of the device.
摘要翻译：提供一种晶体管结构，其包括具有N +源极区域和N-轻掺杂源极区域的源极区域。该结构还包括具有N +漏极区域和N-轻掺杂漏极区域的漏极区域。提供了P ++重掺杂区域。 P ++区域与N-轻掺杂源区域和N-轻掺杂漏极区域中的至少一个的至少一部分一起存在。 P +体区域位于器件的栅极之下以及源极和漏极区域之间。 P +⇄重掺杂区域在器件区域和器件的栅极之间提供电容耦合，并与器件的结电容形成电容分压器。

66. 发明授权

US06403981B1 Double gate transistor having a silicon/germanium channel region 有权
标题翻译：具有硅/锗沟道区的双栅极晶体管
公开(公告)号：US06403981B1
公开(公告)日：2002-06-11
申请号：US09633209
申请日：2000-08-07
申请人： Bin Yu
发明人： Bin Yu
IPC分类号： H01L2904
CPC分类号： H01L29/66916 , H01L29/66742 , H01L29/78639 , H01L29/78648 , H01L29/78687 , H01L29/802
摘要： A method of manufacturing an integrated circuit with a channel region containing germanium. The method includes providing an amorphous semiconductor material including germanium, crystallizing the amorphous semiconductor material, and doping to form a source location and a drain location. The semiconductor material containing germanium can increase the charge mobility associated with the transistor. A double gate structure can also be formed.
摘要翻译：一种制造具有含有锗的沟道区的集成电路的方法。该方法包括提供包括锗的非晶半导体材料，使非晶半导体材料结晶，并掺杂以形成源极位置和漏极位置。含锗的半导体材料可以增加与晶体管相关的电荷迁移率。也可以形成双栅极结构。

67. 发明授权

US06372659B1 Fabrication of metal oxide structure for a gate dielectric of a field effect transistor 有权
标题翻译：用于场效应晶体管的栅极电介质的金属氧化物结构的制造
公开(公告)号：US06372659B1
公开(公告)日：2002-04-16
申请号：US09661041
申请日：2000-09-14
申请人： Bin Yu
发明人： Bin Yu
IPC分类号： H01L2131
CPC分类号： H01L29/517 , H01L21/26506 , H01L21/2807 , H01L21/28079 , H01L21/28211 , H01L21/2822 , H01L21/31683 , H01L29/66583
摘要： For fabricating a metal oxide structure on a semiconductor substrate, an active device area is formed to be surrounded by at least one STI (shallow trench isolation) structure in the semiconductor substrate. A layer of metal is deposited on the semiconductor substrate, and the layer of metal contacts the active device area of the semiconductor substrate. A layer of oxygen blocking material is deposited on the layer of metal, and an opening is etched through the layer of oxygen blocking material to expose an area of the layer of metal on top of the active device area. An interfacial dopant is implanted through the layer of metal to the semiconductor substrate adjacent the layer of metal in the area of the opening where the layer of metal is exposed. A thermal oxidation process is performed to form a metal oxide structure from reaction of oxygen with the area of the opening where the layer of metal is exposed. A thickness of the metal oxide structure is determined by a thickness of the layer of metal, and the layer of oxygen blocking material prevents contact of oxygen with the layer of metal such that the metal oxide structure is formed localized at the area of the opening where the layer of metal is exposed. The interfacial dopant implanted in to the semiconductor substrate adjacent the layer of metal promotes adhesion of the metal oxide structure to the semiconductor substrate. In this manner, the metal oxide structure is formed by localized thermal oxidation of the layer of metal such that a deposition or sputtering process or an etching process is not necessary for formation of the metal oxide structure. In addition, the thickness of the metal oxide structure is determined by controlling the thickness of the layer of metal used for forming the metal oxide structure.
摘要翻译：为了在半导体衬底上制造金属氧化物结构，有源器件区域形成为被半导体衬底中的至少一个STI（浅沟槽隔离）结构包围。一层金属沉积在半导体衬底上，金属层与半导体衬底的有源器件区接触。一层氧阻塞材料沉积在金属层上，并且通过氧气阻挡材料层蚀刻开口以暴露有源器件区域顶部的金属层的区域。将界面掺杂剂通过金属层注入邻近金属层的金属层的暴露金属层的区域中的半导体衬底。进行热氧化处理以由氧与金属层暴露的开口区域的反应形成金属氧化物结构。金属氧化物结构的厚度由金属层的厚度确定，并且阻氧材料层防止氧与金属层的接触，使得金属氧化物结构形成在开口的区域金属层被暴露。注入到与金属层相邻的半导体衬底中的界面掺杂物促进了金属氧化物结构对半导体衬底的粘附。以这种方式，通过金属层的局部热氧化形成金属氧化物结构，使得形成金属氧化物结构不需要沉积或溅射工艺或蚀刻工艺。此外，通过控制用于形成金属氧化物结构的金属层的厚度来确定金属氧化物结构的厚度。

68. 发明授权

US06362055B1 Method of gate doping by ion implantation 失效
公开(公告)号：US06362055B1
公开(公告)日：2002-03-26
申请号：US09144527
申请日：1998-08-31
申请人： Ming-Ren Lin , Bin Yu
发明人： Ming-Ren Lin , Bin Yu
IPC分类号： H01L218234
摘要： A semiconductor device includes a first gate stack and a second gate stack, each gate stack corresponding to a gate of a FET formed on the semiconductor device. The first gate stack includes a gate material formed from one of poly-silicon, poly-SiGe, and amorphous silicon. The gate material is implanted with a dopant of a first conductivity type at a first concentration. A metal silicide layer is formed over the doped gate material. The second gate stack includes a gate material formed from one of poly-silicon, poly-Si—Ge, and amorphous silicon. The gate material of the second gate stack is implanted with a dopant of a second conductivity type at a second concentration.

69. 发明授权

US06361874B1 Dual amorphization process optimized to reduce gate line over-melt 有权
标题翻译：双非晶化工艺优化，以减少栅极线过熔
公开(公告)号：US06361874B1
公开(公告)日：2002-03-26
申请号：US09597623
申请日：2000-06-20
申请人： Bin Yu
发明人： Bin Yu
IPC分类号： H01L21336
CPC分类号： H01L21/26506 , H01L21/26513 , H01L21/268 , H01L29/6659 , Y10T428/31906
摘要： A method of fabricating an integrated circuit with ultra-shallow source/drain junctions utilizes a dual amorphization technique. The technique creates a shallow amorphous region and a deep amorphous region 300 nm thick. The shallow amorphous region can be between 10-15 nm below the top surface of the substrate, and the deep amorphous region can be between 150-200 nm below the top surface of the substrate. The process can reduce gate over-melting effects. The process can be utilized for P-channel or N-channel metal oxide semiconductor field effect transistors (MOSFETs).
摘要翻译：制造具有超浅源极/漏极结的集成电路的方法采用双非晶化技术。该技术产生了300nm厚的浅非晶区和深非晶区。浅非晶区域可以在衬底的顶表面之下10-15nm之间，并且深非晶区域可以在衬底顶表面之下的150-200nm之间。该过程可以减少栅极过熔效应。该过程可用于P沟道或N沟道金属氧化物半导体场效应晶体管（MOSFET）。

70. 发明授权

US06339017B1 Hard mask for integrated circuit fabrication 有权
标题翻译：用于集成电路制造的硬掩模
公开(公告)号：US06339017B1
公开(公告)日：2002-01-15
申请号：US09596993
申请日：2000-06-20
申请人： Bin Yu
发明人： Bin Yu
IPC分类号： H01L214763
CPC分类号： H01L29/6659 , H01L21/0337 , H01L21/0338 , H01L21/28035 , H01L21/28123 , H01L29/7833
摘要： A method of manufacturing small structures or narrow structures on an ultra-large scale integrated circuit utilizes a hard mask. A mask layer can be deposited over a top surface of a material above a semiconductor substrate. A mask layer can be lithographically patterned to have a feature. The side walls of the feature can be oxidized. The oxidized side walls can be removed to reduce the size of the feature below one lithographic feature. The material underneath mask layer can be etched in accordance with the feature without the oxidized side walls.
摘要翻译：在超大规模集成电路上制造小结构或窄结构的方法利用硬掩模。掩模层可沉积在半导体衬底上方的材料的顶表面上。掩模层可以光刻图案化以具有特征。特征的侧壁可以被氧化。可以去除氧化的侧壁以将特征的尺寸减小到低于一个光刻特征。掩模层下面的材料可以根据没有氧化侧壁的特征进行蚀刻。

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