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61. 发明授权

US09007077B2 Flexible current and voltage sensor 有权
标题翻译：灵活的电流和电压传感器
公开(公告)号：US09007077B2
公开(公告)日：2015-04-14
申请号：US13596658
申请日：2012-08-28
申请人： Wael El-Essawy , Alexandre Peixoto Ferreira , Thomas Walter Keller , Karthick Rajamani , Juan C. Rubio , Michael A. Schappert
发明人： Wael El-Essawy , Alexandre Peixoto Ferreira , Thomas Walter Keller , Karthick Rajamani , Juan C. Rubio , Michael A. Schappert
IPC分类号： G01R27/08 , G01R15/20 , G01R1/22
CPC分类号： G01R15/205 , G01R1/22 , G01R15/207
摘要： A flexible current and voltage sensor provides ease of installation of a current sensor, and optionally a voltage sensor in application such as AC branch circuit wire measurements, which may require installation in dense wiring conditions and/or in live panels where insulating gloves must be worn. The sensor includes at least one flexible ferromagnetic strip that is affixed to a current sensing device at a first end. The second end is secured to the other side of the current sensing device or to another flexible ferromagnetic strip extending from the other side of the current sensing device to form a loop providing a closed pathway for magnetic flux. A voltage sensor may be provided by metal foil affixed to the inside of the flexible ferromagnetic strip. A clamp body, which can be a spring loaded handle operated clamp or a locking fastener, can secure the ferromagnetic strip around the wire.
摘要翻译：灵活的电流和电压传感器可以方便地安装电流传感器，以及可选的应用中的电压传感器，例如AC分支电路线测量，其可能需要在密集布线条件下安装，和/或在必须佩戴绝缘手套的实际面板中。传感器包括至少一个柔性铁磁条，其在第一端附接到电流感测装置。第二端固定到电流感测装置的另一侧，或固定到从电流感测装置的另一侧延伸的另一个柔性铁磁条，以形成提供用于磁通的闭合通路的环。电压传感器可以由固定在柔性铁磁条的内部的金属箔提供。可以是弹簧加载手柄操作的夹具或锁定紧固件的夹具体可以将铁磁条固定在线材周围。

62. 发明授权

US08779846B2 Performance of digital circuits using current management 失效
标题翻译：使用当前管理的数字电路的性能
公开(公告)号：US08779846B2
公开(公告)日：2014-07-15
申请号：US13549748
申请日：2012-07-16
申请人： Malcolm Scott Allen-Ware , John Bruce Carter , Heather Lynn Hanson , Wei Huang , Charles Robert Lefurgy , Karthick Rajamani
发明人： Malcolm Scott Allen-Ware , John Bruce Carter , Heather Lynn Hanson , Wei Huang , Charles Robert Lefurgy , Karthick Rajamani
IPC分类号： G06F1/10 , G06F3/02 , H03K17/16 , H03K19/003
CPC分类号： G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： A method for improving the performance of a digital circuit is provided in the illustrative embodiments. A real frequency of operation of the digital circuit is adjusted using a control loop in the digital circuit, the adjusting the real frequency being responsive to a change in an operating condition of the digital circuit. A measurement of a current drawn by the digital circuit is received from a voltage regulator supplying electrical power to the digital circuit. An over-current target current value is received. A voltage output from the voltage regulator to the digital circuit is adjusted such that the current drawn by the digital circuit does not exceed the over-current target current value.
摘要翻译：在说明性实施例中提供了一种用于改善数字电路的性能的方法。使用数字电路中的控制环来调整数字电路的实际工作频率，响应于数字电路的工作状态的变化来调整实际频率。从向数字电路提供电力的电压调节器接收由数字电路汲取的电流的测量值。接收过电流目标电流值。调整从电压调节器到数字电路的输出电压，使得由数字电路汲取的电流不超过过电流目标电流值。

63. 发明授权

US08645640B2 Method and apparatus for supporting memory usage throttling 失效
标题翻译：支持内存使用限制的方法和装置
公开(公告)号：US08645640B2
公开(公告)日：2014-02-04
申请号：US13166054
申请日：2011-06-22
申请人： Michael S. Floyd , Guy L. Guthrie , Karthick Rajamani , Gregory S. Still , Jeffrey A. Stuecheli , Malcolm S. Ware
发明人： Michael S. Floyd , Guy L. Guthrie , Karthick Rajamani , Gregory S. Still , Jeffrey A. Stuecheli , Malcolm S. Ware
IPC分类号： G06F12/00
CPC分类号： G06Q50/10
摘要： An apparatus for providing system memory usage throttling within a data processing system having multiple chiplets is disclosed. The apparatus includes a system memory, a memory access collection module, a memory credit accounting module and a memory throttle counter. The memory access collection module receives a first set of signals from a first cache memory within a chiplet and a second set of signals from a second cache memory within the chiplet. The memory credit accounting module tracks the usage of the system memory on a per user virtual partition basis according to the results of cache accesses extracted from the first and second set of signals from the first and second cache memories within the chiplet. The memory throttle counter for provides a throttle control signal to prevent any access to the system memory when the system memory usage has exceeded a predetermined value.
摘要翻译：公开了一种用于在具有多个小灯的数据处理系统内提供系统存储器使用限制的装置。该装置包括系统存储器，存储器访问收集模块，存储器信用计费模块和存储器调节计数器。存储器访问收集模块从小数点内的第一高速缓冲存储器接收来自第一高速缓冲存储器的第一组信号和来自第二高速缓冲存储器的第二组信号。存储器信用计费模块根据从小巧的第一和第二高速缓存存储器的第一和第二组信号中提取的高速缓存访问的结果来跟踪每用户虚拟分区上的系统存储器的使用情况。存储器油门计数器用于提供节气门控制信号，以防止当系统存储器使用量超过预定值时对系统存储器的访问。

64. 发明申请

US20130325378A1 Predicting Energy Savings 有权
标题翻译：预测节能
公开(公告)号：US20130325378A1
公开(公告)日：2013-12-05
申请号：US13488822
申请日：2012-06-05
申请人： Malcolm S. Allen-Ware , Wei Huang , Fadi M. Kassem , Karthick Rajamani , Todd J. Rosedahl , Guillermo J. Silva
发明人： Malcolm S. Allen-Ware , Wei Huang , Fadi M. Kassem , Karthick Rajamani , Todd J. Rosedahl , Guillermo J. Silva
IPC分类号： G06F19/00 , G01R21/133
CPC分类号： G06F1/329 , Y02D10/24
摘要： A mechanism is provided for estimating energy/power consumption of a fixed-frequency operating mode while system is running in dynamic power management mode. For each time interval in a plurality of time intervals within a time period: a first processor identifies a modeled total nominal power value for at least one second processor during a current time interval, stores the modeled total nominal power value for the current time interval in a storage, identifies a dynamic power management mode power value for the at least one second processor in the data processing system during the current interval, and stores the dynamic power management mode power value for the current time interval in the storage. Responsive to the time period expiring, a comparison is produced of a plurality of modeled total nominal power values and a plurality of dynamic power management mode power values over the time period.
摘要翻译：提供了一种用于在系统以动态功率管理模式运行时估计固定频率操作模式的能量/功率消耗的机制。对于在一段时间段内的多个时间间隔中的每个时间间隔：第一处理器在当前时间间隔期间识别至少一个第二处理器的建模总额定功率值，将建模的总额定功率值存储在当前时间间隔中存储器，在当前间隔期间识别数据处理系统中的至少一个第二处理器的动态功率管理模式功率值，并将当前时间间隔的动态功率管理模式功率值存储在存储器中。响应于时间段到期，在该时间段内产生多个建模的总额定功率值和多个动态功率管理模式功率值的比较。

65. 发明授权

US08589665B2 Instruction set architecture extensions for performing power versus performance tradeoffs 失效
标题翻译：用于执行功率与性能折衷的指令集架构扩展
公开(公告)号：US08589665B2
公开(公告)日：2013-11-19
申请号：US12788940
申请日：2010-05-27
申请人： John B. Carter , Jian Li , Karthick Rajamani , William E. Speight , Lixin Zhang
发明人： John B. Carter , Jian Li , Karthick Rajamani , William E. Speight , Lixin Zhang
IPC分类号： G06F9/00
CPC分类号： G06F9/30083 , G06F1/3203 , G06F9/3013 , G06F9/30181 , G06F9/3836 , G06F9/3869 , G06F9/3885 , G06F11/302 , G06F11/3062 , G06F11/3096
摘要： Mechanisms are provided for processing an instruction in a processor of a data processing system. The mechanisms operate to receive, in a processor of the data processing system, an instruction, the instruction including power/performance tradeoff information associated with the instruction. The mechanisms further operate to determine power/performance tradeoff priorities or criteria, specifying whether power conservation or performance is prioritized with regard to execution of the instruction, based on the power/performance tradeoff information. Moreover, the mechanisms process the instruction in accordance with the power/performance tradeoff priorities or criteria identified based on the power/performance tradeoff information of the instruction.
摘要翻译：提供了用于处理数据处理系统的处理器中的指令的机制。这些机制操作以在数据处理系统的处理器中接收指令，该指令包括与指令相关联的功率/性能权衡信息。这些机制进一步操作以基于功率/性能折衷信息来确定功率/性能折衷优先级或标准，指定功率节省或关于指令的执行是否优先的性能。此外，机构根据功率/性能折衷优先级或基于指令的功率/性能折衷信息识别的标准处理指令。

66. 发明授权

US08566618B2 Reliable setting of voltage and frequency in a microprocessor 有权
标题翻译：微处理器中电压和频率的可靠设置
公开(公告)号：US08566618B2
公开(公告)日：2013-10-22
申请号：US12573284
申请日：2009-10-05
申请人： Michael S. Floyd , Karthick Rajamani , Juan C. Rubio , Malcolm S. Ware
发明人： Michael S. Floyd , Karthick Rajamani , Juan C. Rubio , Malcolm S. Ware
IPC分类号： G06F1/00 , G06F1/26
CPC分类号： G06F1/3296 , G06F1/3203 , G06F1/324 , Y02D10/126 , Y02D10/172
摘要： Managing operations associated with one or more voltage changes and one or more frequency changes. A voltage change request and a frequency change request are associated with dynamic voltage and frequency scaling (DVFS) operations. The DVFS operations are transmitted by the processors to be executed by one or more direct current assemblies. A sequence associated with the one or more voltage changes and a sequence associated with the one or more frequency changes are detected by the system. The sequences are dynamically modified to enable insertion of an additional voltage change, whereby the additional voltage change indicates completion of one or more previous voltage change requests. Completion of the voltage change request enables one or more subsequent voltage change requests to be processed. When a voltage change request is not successfully completed one or more future voltage changes are suspended.
摘要翻译：管理与一个或多个电压变化和一个或多个频率变化相关联的操作。电压变化请求和频率变化请求与动态电压和频率缩放（DVFS）操作相关联。 DVFS操作由处理器发送以由一个或多个直流组件执行。与该一个或多个电压变化相关联的序列和与一个或多个频率变化相关联的序列由系统检测。这些序列被动态地修改以允许插入额外的电压变化，由此额外的电压变化指示完成一个或多个先前的电压变化请求。完成电压变化请求使得能够处理一个或多个后续电压变化请求。当电压变化请求未成功完成时，一个或多个未来的电压变化被暂停。

67. 发明授权

US08381002B2 Transparently increasing power savings in a power management environment 失效
公开(公告)号：US08381002B2
公开(公告)日：2013-02-19
申请号：US12821789
申请日：2010-06-23
申请人： Naresh Nayar , Karthick Rajamani , Freeman L. Rawson, III
发明人： Naresh Nayar , Karthick Rajamani , Freeman L. Rawson, III
IPC分类号： G06F1/32
CPC分类号： G06F1/3203 , G06F9/5077 , G06F9/5094 , Y02D10/22 , Y02D10/36
摘要： A mechanism is provided for transparently consolidating resources of logical partitions. Responsive to the existence of the non-folded resource on an originating resource chip, the virtualization mechanism determines whether there is a destination resource chip to either exchange operations of the non-folded resource with a folded resource on the destination chip or migrate operations of the non-folded resource to a non-folded resource on the destination chip. Responsive to the existence of the folded resource on the destination resource chip, the virtualization mechanism transparently exchanges the operations of the non-folded resource from the originating resource chip to the folded resource on the destination resource chip, where the folded resource remains folded on the originating resource chip after the exchange. Responsive to the absence of another non-folded resource on the originating resource chip, the vitalization mechanism places the originating resource chip into a deeper power saving mode.

68. 发明授权

US08341628B2 Controlling depth and latency of exit of a virtual processor's idle state in a power management environment 失效
标题翻译：在电源管理环境中控制虚拟处理器空闲状态退出的深度和延迟
公开(公告)号：US08341628B2
公开(公告)日：2012-12-25
申请号：US12645597
申请日：2009-12-23
申请人： Richard Louis Arndt , Christopher Francois , Naresh Nayar , Karthick Rajamani , Freeman Leigh Rawson, III , Randal Craig Swanberg
发明人： Richard Louis Arndt , Christopher Francois , Naresh Nayar , Karthick Rajamani , Freeman Leigh Rawson, III , Randal Craig Swanberg
IPC分类号： G06F9/455 , G06F1/00
CPC分类号： G06F9/45533 , G06F9/45541 , G06F2009/45575
摘要： A mechanism is provided in a logically partitioned data processing system for controlling depth and latency of exit of a virtual processor's idle state. A virtualization layer generates a cede latency setting information (CLSI) data. Responsive to booting a logical partition, the virtualization layer communicates the CLSI data to an operating system (OS) of the logical partition. The OS determines, based on the CLSI data, a particular idle state of a virtual processor under a control of the OS. Responsive to the OS calling the virtualization layer, the OS communicates the particular idle state of the virtual processor to the virtualization layer for assigning the particular idle state and wake-up characteristics to the virtual processor.
摘要翻译：在逻辑分区的数据处理系统中提供一种机制，用于控制虚拟处理器的空闲状态的退出的深度和等待时间。一个虚拟化层产生一个雪松延迟设置信息（CLSI）数据。响应于引导逻辑分区，虚拟化层将CLSI数据传送到逻辑分区的操作系统（OS）。 OS根据CLSI数据确定在OS控制下的虚拟处理器的特定空闲状态。响应于调用虚拟化层的OS，OS将虚拟处理器的特定空闲状态传送到虚拟化层，以将特定的空闲状态和唤醒特性分配给虚拟处理器。

69. 发明申请

US20120324264A1 Priority-Based Power Capping in Data Processing Systems 有权
公开(公告)号：US20120324264A1
公开(公告)日：2012-12-20
申请号：US13593717
申请日：2012-08-24
申请人： Heather L. Hanson , Charles R. Lefurgy , Karthick Rajamani , Freeman L. Rawson, III , Malcolm S. Ware
发明人： Heather L. Hanson , Charles R. Lefurgy , Karthick Rajamani , Freeman L. Rawson, III , Malcolm S. Ware
IPC分类号： G06F1/26
CPC分类号： G06F9/5061 , G06F9/5094 , Y02D10/22 , Y02D10/36
摘要： A mechanism is provided for priority-based power capping. A power management controller identifies a set of priorities for a set of partitions of the data processing system. The power management controller determines whether a measured power of the data processing system exceeds a power cap for the data processing system. Responsive to the measured power exceeding the power cap, the power management controller sends a set of commands to a set of component actuators to adjust one or more of a set of operation parameters for a set of components associated with the set of partitions using the set of priorities. The set of component actuators adjust the one or more of the set of operational parameters associated with the set of component in order to reduce a power consumption of the data processing system.

70. 发明授权

US08261112B2 Optimizing power consumption by tracking how program runtime performance metrics respond to changes in operating frequency 失效
标题翻译：通过跟踪程序运行时性能指标如何响应运行频率的变化来优化功耗
公开(公告)号：US08261112B2
公开(公告)日：2012-09-04
申请号：US12330284
申请日：2008-12-08
申请人： John B. Carter , Heather L. Hanson , Karthick Rajamani , Freeman L. Rawson, III , Malcolm S. Ware
发明人： John B. Carter , Heather L. Hanson , Karthick Rajamani , Freeman L. Rawson, III , Malcolm S. Ware
IPC分类号： G06F1/32 , G06F1/26 , G06F1/08
CPC分类号： G06F1/3203 , G06F1/324 , Y02D10/126
摘要： A method, system, and computer program product for optimizing power consumption of an executing processor executing. The method includes determining a first sensitivity relationship (SR) based on a first and a second performance metric value (PMV) measured at a first and second operating frequency (OF), respectively. The first SR predicts workload performance over a range of OFs. A third OF is determined based on the first SR and a specified workload performance floor. A third PMV is measured by executing the processor operating at the third OF. A second SR based on the second and third PMVs is then determined. The first and second SRs are logically combined to generate a third SR. Based on the third SR, a fourth OF is outputted.
摘要翻译：一种用于优化执行中的执行处理器的功耗的方法，系统和计算机程序产品。该方法包括分别基于在第一和第二操作频率（OF）下测量的第一和第二性能量度值（PMV）来确定第一灵敏度关系（SR）。第一个SR预测一系列OFs的工作负载性能。基于第一个SR和指定的工作负载性能底线确定三分之一。通过执行在第三个OF操作的处理器来测量第三个PMV。然后确定基于第二和第三PMV的第二SR。逻辑上组合第一和第二SR以产生第三SR。基于第三SR，输出第四个OF。

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