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61. 发明授权

US06633496B2 Symmetric architecture for memory cells having widely spread metal bit lines 有权
标题翻译：具有广泛扩展的金属位线的存储单元的对称架构
公开(公告)号：US06633496B2
公开(公告)日：2003-10-14
申请号：US09727781
申请日：2000-12-04
申请人： Eduardo Maayan , Boaz Eitan
发明人： Eduardo Maayan , Boaz Eitan
IPC分类号： G11C506
CPC分类号： H01L27/11568 , G11C7/18 , G11C11/5671 , G11C16/0475 , G11C16/0491 , G11C16/24 , H01L27/112 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A memory array includes a first plurality of metal lines, a second plurality of diffusion bit lines and a third plurality of select transistors. There are more than two diffusion bit lines per metal bit line. The memory also includes a cell area formed of four segmented cell bit lines an even select area and an odd select area. The even select area is located at one end of the cell area and includes a segmented even contact bit line and two select transistors connecting the even contact bit line with the even cell bit lines of the segment. The odd select area is located at the opposite end of the cell area and includes a segmented odd contact bit line and two select transistors connecting the odd contact bit line with the odd cell bit lines of the segment.
摘要翻译：存储器阵列包括第一多个金属线，第二多个扩散位线和第三多个选择晶体管。每个金属位线有两个以上的扩散位线。存储器还包括由四个分段单元位线形成偶数选择区域和奇数选择区域的单元区域。偶数选择区域位于单元区域的一端，并且包括分段的偶数位线以及将偶数接触位线与该段的偶数单元位线连接的两个选择晶体管。奇数选择区域位于单元区域的相对端，并且包括分段的奇数接触位线和将奇数接触位线与该段的奇数单元位线连接的两个选择晶体管。

62. 发明授权

US06429063B1 NROM cell with generally decoupled primary and secondary injection 有权
标题翻译： NROM电池具有一般去耦的初级和次级注入
公开(公告)号：US06429063B1
公开(公告)日：2002-08-06
申请号：US09519745
申请日：2000-03-06
申请人： Boaz Eitan
发明人： Boaz Eitan
IPC分类号： H01L218238
CPC分类号： H01L29/66833 , G11C11/5671 , G11C16/0475 , H01L29/792
摘要： A method of creating a nitride, programmable read only memory (NROM) cell includes the step of decoupling injection of channel hot electrons into a charge trapping layer of the NROM cell from injection of non-channel electrons into the charge trapping layer. The step of decoupling can include the step of minimizing the injection of the non-channel electrons into the charge trapping layer. Alternatively, it includes the step of minimizing the generation of the non-channel electrons. The present invention includes cells which have minimal injection of non-channel electrons therein.
摘要翻译：创建氮化物可编程只读存储器（NROM）单元的方法包括将通道热电子注入到NROM单元的电荷捕获层中以将非沟道电子注入到电荷俘获层中的步骤。去耦的步骤可以包括最小化非沟道电子注入电荷捕获层的步骤。或者，它包括最小化非沟道电子的产生的步骤。本发明包括其中非通道电子注入量最小的电池。

63. 发明授权

US06396741B1 Programming of nonvolatile memory cells 有权
标题翻译：非易失性存储单元的编程
公开(公告)号：US06396741B1
公开(公告)日：2002-05-28
申请号：US09563923
申请日：2000-05-04
申请人： Ilan Bloom , Boaz Eitan , Zeev Cohen , David Finzi , Eduardo Maayan
发明人： Ilan Bloom , Boaz Eitan , Zeev Cohen , David Finzi , Eduardo Maayan
IPC分类号： G11C1606
CPC分类号： G11C16/3481 , G11C11/5671 , G11C16/0475 , G11C16/3454 , G11C16/3468
摘要： A method for programming an NROM cell which includes the steps of applying a drain, a source and a gate voltage to the cell and verifying a programmed of a non-programmed state of the cell. If the cell is in the non-programmed state, the method includes the steps of increasing the drain voltage and maintaining the gate voltage at a constant level during at least a part of the step of increasing. The steeps of applying, verifying, increasing and maintaining are repeated until the cell reaches the programmed state.
摘要翻译：一种用于对NROM单元进行编程的方法，其包括以下步骤：向所述单元施加漏极，源极和栅极电压，并验证编程的所述单元的非编程状态。如果电池处于非编程状态，则该方法包括以下步骤：在增加的步骤的至少一部分期间增加漏极电压并将栅极电压保持在恒定水平。重复施加，验证，增加和维护的陡峭度，直到单元达到编程状态。

64. 发明授权

US5963465A Symmetric segmented memory array architecture 失效
公开(公告)号：US5963465A
公开(公告)日：1999-10-05
申请号：US989690
申请日：1997-12-12
申请人： Boaz Eitan
发明人： Boaz Eitan
IPC分类号： H01L21/8247 , G11C7/18 , G11C11/56 , G11C16/04 , H01L27/02 , H01L27/115 , H01L29/788 , H01L29/792 , G11C5/06
CPC分类号： H01L27/115 , G11C11/5671 , G11C16/0475 , G11C16/0491 , G11C7/18 , H01L27/0207 , G11C16/24
摘要： A symmetric memory array includes a multiplicity of repeating segments formed into rows and columns. Each segment includes a cell area formed of four segmented cell bit lines an even select area and an odd select area. The even select area is located at one end of the cell area and includes a segmented even contact bit line and two select transistors connecting the even contact bit line with the even cell bit lines of the segment. The odd select area is located at the opposite end of the cell area and includes a segmented odd contact bit line and two select transistors connecting the odd contact bit line with the odd cell bit lines of the segment. The array additionally includes one even contact connected to the even contact bit lines of two neighboring even select areas, one odd contact connected to the odd contact bit lines of two neighboring odd select areas and alternating even and odd metal lines connecting to the even and odd contacts, respectively.

65. 发明授权

US5796313A Low power programmable ring oscillator 失效
标题翻译：低功耗可编程环形振荡器
公开(公告)号：US5796313A
公开(公告)日：1998-08-18
申请号：US639281
申请日：1996-04-25
申请人： Boaz Eitan
发明人： Boaz Eitan
IPC分类号： H03K3/03 , H03L1/00 , H03L3/00 , H03B5/04 , H03L5/00
CPC分类号： H03K3/0315 , H03L1/00 , H03L3/00
摘要： A novel ring oscillator integrated circuit whose frequency of oscillation is independent of supply voltage, temperature and process technology is described. In addition, the ring oscillator circuit consumes low power and its frequency of oscillation is programmable. The ring oscillator comprises one or more inverter sections cascaded together in series. The output of the final inverter stage is coupled to the input of the first inverter stage. Inserted in the feedback loop is feedback control circuitry which functions to control the start/stop operation of the oscillator. Each inverter section includes a p-channel transistor coupled to a parallel combination of impedance and capacitance, which gives the inverter section asymmetric operating characteristics. This asymmetry helps to achieve a frequency of oscillation independent of supply voltage. A plurality of transistors having predetermined impedance's are coupled in series with the p-channel transistor to form the current limiting impedance. An output buffer provides large drive capability and achieves low power consumption by eliminating normally present crowbar current during switching. Pull-down control circuitry provides individual gate control of each of the transistors making up the current limiter in each inverter section. Process independence is achieved by trimming the plurality of pull-down current limiting transistor so as to attain a particular frequency of oscillation.
摘要翻译：描述了一种新颖的环形振荡器集成电路，其振荡频率与电源电压，温度和工艺技术无关。此外，环形振荡器电路消耗低功耗，其振荡频率可编程。环形振荡器包括串联在一起的一个或多个逆变器部分。最后的逆变器级的输出耦合到第一逆变器级的输入端。插入反馈回路中的是反馈控制电路，其用于控制振荡器的启动/停止操作。每个逆变器部分包括耦合到阻抗和电容的并联组合的p沟道晶体管，这使得逆变器部分具有不对称的工作特性。这种不对称有助于实现独立于电源电压的振荡频率。具有预定阻抗的多个晶体管与p沟道晶体管串联耦合以形成限流阻抗。输出缓冲器提供大的驱动能力，通过消除切换期间正常出现的撬棒电流来实现低功耗。下拉控制电路在每个逆变器部分中提供构成电流限制器的每个晶体管的单独栅极控制。通过修整多个下拉限流晶体管以获得特定的振荡频率来实现过程独立性。

66. 发明授权

US5768192A Non-volatile semiconductor memory cell utilizing asymmetrical charge trapping 失效
标题翻译：利用不对称电荷捕获的非易失性半导体存储单元
公开(公告)号：US5768192A
公开(公告)日：1998-06-16
申请号：US681430
申请日：1996-07-23
申请人： Boaz Eitan
发明人： Boaz Eitan
IPC分类号： G11C16/02 , G11C11/56 , G11C16/04 , H01L29/792 , G11C11/34
CPC分类号： H01L29/792 , G11C11/5671 , G11C16/0475
摘要： A novel apparatus for and method of programming and reading a programmable read only memory (PRON) having a trapping dielectric sandwiched between two silicon dioxide layers is disclosed that greatly reduces the programming time of conventional PROM devices. Examples of the trapping dielectric are silicon oxide-silicon nitride-silicon oxide (ONO) and silicon dioxide with buried polysilicon islands. A nonconducting dielectric layer functions as an electrical charge trapping medium. This charge trapping layer is sandwiched between two layers of silicon dioxide acting as an electrical insulator. A conducting gate layer is placed over the upper silicon dioxide layer. The memory device is programmed in the conventional manner, using hot electron programming, by applying programming voltages to the gate and the drain while the source is grounded. Hot electrons are accelerated sufficiently to be injected into the region of the trapping dielectric layer near the drain. The device, however, is read in the opposite direction from which it was written, meaning voltages are applied to the gate and the source while the drain is grounded. For the same applied gate voltage, reading in the reverse direction greatly reduces the potential across the trapped charge region. This permits much shorter programming times by amplifying the effect of the charge trapped in the localized trapping region.
摘要翻译：公开了一种用于编程和读取具有夹在两个二氧化硅层之间的捕获电介质的可编程只读存储器（PRON）的新型装置和方法，其大大降低了常规PROM器件的编程时间。捕获电介质的实例是氧化硅 - 氮化硅 - 氧化硅（ONO）和具有埋多晶硅岛的二氧化硅。非导电介电层用作电荷捕获介质。该电荷捕获层被夹在作为电绝缘体的两层二氧化硅之间。导电栅极层放置在上部二氧化硅层上。存储器件以常规方式使用热电子编程通过在源极接地时向栅极和漏极施加编程电压来编程。热电子被充分加速以注入漏极附近的捕获电介质层的区域。然而，器件的读取方向与写入的方向相反，意味着在漏极接地时，电压被施加到栅极和源极。对于相同的施加栅极电压，在相反方向的读数大大降低了被俘获电荷区域的电位。这允许通过放大俘获在局部捕获区域中的电荷的效应来缩短编程时间。

67. 发明授权

US5696730A First read cycle circuit for semiconductor memory 失效
标题翻译：半导体存储器的第一个读周期电路
公开(公告)号：US5696730A
公开(公告)日：1997-12-09
申请号：US665191
申请日：1996-06-13
申请人： Yaron Slezak , Boaz Eitan
发明人： Yaron Slezak , Boaz Eitan
IPC分类号： G11C11/41 , G11C7/22 , G11C8/18 , G11C16/06 , G11C7/00
CPC分类号： G11C7/22 , G11C8/18
摘要： A novel circuit for initiating a first read cycle when power is first applied to the memory device is disclosed. The circuit compares the ramping up of the word line voltage signal to a stable reference voltage using a comparator. Once the word line voltage reaches a predetermined level, but before it reaches its maximum value, the comparator trips. The transition of the comparator output is sensed by an address transition detection circuit which subsequently triggers a read cycle of the memory, thus creating a dummy read access without any requirement that the input address actually make a transition. A memory access time later, valid data is available at the output of the memory array. A voltage divider is used to divide the word line voltage to a suitable level for input to the comparator. The stable reference voltage serves as the source of the word line signal, besides being input to the comparator. A voltage multiplier is utilized to generate the word line signal from the voltage reference. Alternatively, the word line voltage may be supplied by an external source such as the supply voltage. Both the voltage multiplier and the voltage divider include programmable trimming transistors which allow tuning of their respective outputs. In addition, enable circuitry is included which disables the first read cycle circuitry in order to reduce power consumption after the first read cycle is initiated.
摘要翻译：公开了一种用于在首次向存储器件施加电力时启动第一读取周期的新型电路。该电路使用比较器将字线电压信号的上升与稳定的参考电压进行比较。一旦字线电压达到预定电平，但在达到其最大值之前，比较器跳闸。比较器输出的转换由地址转换检测电路感测，随后触发存储器的读取周期，从而创建虚拟读取访问，而不需要输入地址实际上进行转换。存储器访问时间之后，存储器阵列的输出端提供有效的数据。分压器用于将字线电压分成适当的电平以供输入到比较器。除了输入到比较器之外，稳定的参考电压也用作字线信号的源。利用电压倍增器从电压基准产生字线信号。或者，字线电压可以由诸如电源电压的外部源提供。电压倍增器和分压器都包括可调谐其各自输出的可编程微调晶体管。此外，包括启用电路，其禁用第一读取周期电路，以便在启动第一读取周期之后降低功耗。

68. 发明授权

US5034786A Opaque cover for preventing erasure of an EPROM 失效
标题翻译：用于防止擦除EPROM的不透明盖
公开(公告)号：US5034786A
公开(公告)日：1991-07-23
申请号：US214562
申请日：1988-07-01
申请人： Boaz Eitan
发明人： Boaz Eitan
IPC分类号： H01L29/788
CPC分类号： H01L29/7885
摘要： A structure for preventing light from reaching and erasing a floating gate comprises a control gate which covers not only the floating gate, but the portion of the semiconductor substrate laterally surrounding the floating gate. In accordance with one novel feature of my invention, a conductive structure also laterally surrounds the floating gate and extends between the semiconductor substrate and the control gate. In one embodiment, the conductive structure is electrically shorted to ground and is constructed from the same layer of material as the floating gate. Of importance, the conductive structure both serves as an additional light blocking structure and also serves as a field plate so that it is not necessary to form a thick field oxide layer surrounding the transistor. Because the conductive structure and the control gate are used as the light blocking structure and the contact metallization layer is not used to form the opaque cover, it is possible to extend contact metallization over the covered floating gate transistor.
摘要翻译：用于防止光到达和擦除浮动栅极的结构包括不仅覆盖浮动栅极而且半导体衬底的横向围绕浮动栅极的部分的控制栅极。根据本发明的一个新颖特征，导电结构还横向围绕浮动栅极并且在半导体衬底和控制栅极之间延伸。在一个实施例中，导电结构被电短路接地，并由与浮动栅极相同的材料层构成。重要的是，导电结构都用作附加的光阻挡结构，并且还用作场板，使得不需要形成围绕晶体管的厚的场氧化物层。由于导电结构和控制栅极用作遮光结构，并且接触金属化层不用于形成不透明盖，所以可以在覆盖的浮栅晶体管上扩展接触金属化。

69. 发明授权

US4649520A Single layer polycrystalline floating gate 失效
标题翻译：单层多晶浮栅
公开(公告)号：US4649520A
公开(公告)日：1987-03-10
申请号：US669198
申请日：1984-11-07
申请人： Boaz Eitan
发明人： Boaz Eitan
IPC分类号： H01L29/788 , G11C11/40
CPC分类号： H01L29/7885
摘要： A programmable read only memory includes a transistor having an N type source, an N type drain, and a polysilicon floating gate extending over the channel between the source and drain. The floating gate also extends over and is capacitively coupled to an N well. By applying an electric potential to the N well, the potential on the floating gate above the channel is altered.Within the N well is a P region, which mitigates the decrease in capacitive coupling between the N well and the floating gate caused by carrier depletion.
摘要翻译：可编程只读存储器包括具有在源极和漏极之间的沟道上延伸的N型源极，N型漏极和多晶硅浮动栅极的晶体管。浮动栅极也延伸并且电容耦合到N阱。通过向N阱施加电位，通道上方的浮动栅极上的电位被改变。在N阱内是P区，其减轻由载波耗尽引起的N阱和浮栅之间的电容耦合的减小。

70. 发明授权

US4639893A Self-aligned split gate EPROM 失效
标题翻译：自对准分裂门EPROM
公开(公告)号：US4639893A
公开(公告)日：1987-01-27
申请号：US610369
申请日：1984-05-15
申请人： Boaz Eitan
发明人： Boaz Eitan
IPC分类号： H01L21/8247 , H01L21/28 , H01L27/115 , H01L29/788 , H01L29/792 , G11C11/40
CPC分类号： H01L21/28273 , H01L27/115 , H01L29/7881
摘要： A self-aligned split gate single transistor memory cell structure is formed by a process which self aligns the drain region to one edge of a floating gate. The portion of the channel underneath the floating gate is accurately defined by using one edge of the floating gate to align the drain region. The control gate formed over the floating gate controls the portion of the channel region between the floating gate and the source to provide split gate operation. The source region is formed sufficiently far from the floating gate so that the channel length between the source region and the closest edge of the floating gate is controlled by the control gate but does not have to be accurately defined.
摘要翻译：通过使漏极区域与浮动栅极的一个边缘自对准的工艺来形成自对准的分离栅极单晶体管存储单元结构。通过使用浮置栅极的一个边缘来精确地限定浮动栅极下面的沟道部分，以对准漏极区域。形成在浮置栅极上的控制栅极控制浮置栅极和源极之间的沟道区域的部分以提供分流栅极操作。源极区域形成为足够远离浮置栅极，使得源极区域和浮动栅极的最近边缘之间的沟道长度由控制栅极控制，但不必被精确地限定。

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