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61. 发明授权

US08442982B2 Extended database search 有权
公开(公告)号：US08442982B2
公开(公告)日：2013-05-14
申请号：US12941026
申请日：2010-11-05
申请人： Eric Jacobson , Les Thomas , Gang Zhang
发明人： Eric Jacobson , Les Thomas , Gang Zhang
IPC分类号： G06F17/30
CPC分类号： G06F17/30336 , G06F17/30533 , G06F17/30566 , G06F17/30657
摘要： Methods, program products, and systems implementing integrated repository of structured and unstructured data are disclosed. An integrated environment is provided for accessing structured data (e.g., data of a relational database) and unstructured data (e.g., data stored in a text or binary file), including creating, managing, modifying, and searching the structured data and unstructured data. The integrated environment can include an integrated user interface, a set of commands and application programming interface (API), and storage for a relational database and a document repository. The integrated environment can include a database abstraction layer that allows database operations on both the structured data and the unstructured data.

62. 发明授权

US08410658B2 Multi-layer electrostatic energy harvester and method of making the same 有权
标题翻译：多层静电收割机及其制作方法
公开(公告)号：US08410658B2
公开(公告)日：2013-04-02
申请号：US12473439
申请日：2009-05-28
申请人： Gang Zhang
发明人： Gang Zhang
IPC分类号： H02N1/00
CPC分类号： H02N1/08 , B81B3/0021
摘要： An electrostatic energy harvester comprises at least a plurality of variable capacitor layers. In one embodiment, at least two of the variable capacitor layers are directly bonded together. In another embodiment, at least two of the variable capacitor layers are bonded together with at least one moving mass layer. Still in another embodiment, at least two of the variable capacitor layers are located at different heights and are located separately from each other. A method of making such a device is also disclosed.
摘要翻译：静电收集器包括至少多个可变电容器层。在一个实施例中，至少两个可变电容器层直接接合在一起。在另一个实施例中，至少两个可变电容器层与至少一个移动质量层结合在一起。仍然在另一个实施例中，至少两个可变电容器层位于不同的高度并且彼此分开定位。还公开了制造这种装置的方法。

63. 发明授权

US08216931B2 Methods for forming multi-layer three-dimensional structures 有权
标题翻译：形成多层三维结构的方法
公开(公告)号：US08216931B2
公开(公告)日：2012-07-10
申请号：US11548207
申请日：2006-10-10
申请人： Gang Zhang
发明人： Gang Zhang
IPC分类号： H01L21/4763
CPC分类号： B81C1/0019 , B81C2201/019
摘要： Embodiments are directed to the formation of multi-layer three-dimensional structures by forming and attaching a plurality of layers where each of the plurality of layers comprises at least one structural material forming a pattern and where at least one of the plurality of layers comprises at least one sacrificial material. In one embodiment, the formation of a multi-layer three-dimensional structure comprises (1) forming a plurality of individual layers and (2) attaching at least the formed plurality of individual layers together. In another embodiment, the formation of a multi-layer three-dimensional structure comprises (1) attaching an individual layer onto a substrate or onto a previously formed layer; (2) processing the attached individual layer to form a new layer comprising at least one material forming a pattern; and (3) repeating the steps of (1) and (2) one or more times.
摘要翻译：实施例涉及通过形成和附接多个层来形成多层三维结构，其中多个层中的每个层包括形成图案的至少一个结构材料，并且其中至少一个层包括在至少一种牺牲材料。在一个实施例中，多层三维结构的形成包括（1）形成多个单独的层和（2）至少将形成的多个单独的层附接在一起。在另一个实施方案中，多层三维结构的形成包括（1）将单独的层附着在基底上或先前形成的层上; （2）处理附着的单独层以形成包含形成图案的至少一种材料的新层; 和（3）重复步骤（1）和（2）一次或多次。

64. 发明申请

US20120071472A1 RIMINOPHENAZINES WITH 2-(HETEROARYL)AMINO SUBSTITUENTS AND THEIR ANTI-MICROBIAL ACTIVITY 有权
标题翻译：具有2-（杂芳族）氨基取代基的咪唑啉酮及其抗微生物活性
公开(公告)号：US20120071472A1
公开(公告)日：2012-03-22
申请号：US13171102
申请日：2011-06-28
申请人： Kai Liu , Christopher B. Cooper , Haihong Huang , Chun Li , Binna Liu , Yang Liu , Zhenkun Ma , Jingbin Wang , Dali Yin , Dongfeng Zhang , Gang Zhang , Hao Zhang
发明人： Kai Liu , Christopher B. Cooper , Haihong Huang , Chun Li , Binna Liu , Yang Liu , Zhenkun Ma , Jingbin Wang , Dali Yin , Dongfeng Zhang , Gang Zhang , Hao Zhang
IPC分类号： A61K31/498 , A61K31/506 , C07D401/12 , C07D401/14 , A61P31/06 , A61K31/5377 , C07D405/14 , C07D409/14 , A61P31/04 , C07D403/12 , C07D413/14
CPC分类号： C07D409/14 , A61K31/498 , A61K31/506 , A61K31/5377 , A61K45/06 , C07D401/12 , C07D401/14 , C07D403/12 , C07D405/12 , C07D407/14 , C07D409/12
摘要： The present invention relates to riminophenazines having heteroaromatic substitutions, including those with 2-heteroaryl-amino substituents, to their preparation, and to their use as drugs for treating Mycobacterium tuberculosis and other microbial infections, either alone or in combination with other anti-infective treatments.
摘要翻译：本发明涉及具有杂芳香取代基，包括具有2-杂芳基 - 氨基取代基的那些，其制备方法及其用作治疗结核分枝杆菌和其它微生物感染的药物，其单独使用或与其它抗感染治疗组合。

65. 发明授权

US08043931B1 Methods for forming multi-layer silicon structures 有权
标题翻译：形成多层硅结构的方法
公开(公告)号：US08043931B1
公开(公告)日：2011-10-25
申请号：US11855906
申请日：2007-09-14
申请人： Gang Zhang
发明人： Gang Zhang
IPC分类号： H01L21/00 , H01L21/331 , H01L21/76
CPC分类号： B81C1/00119 , B81C1/00357 , B81C2201/019 , H01L21/187
摘要： The embodiments of the present invention are directed to the formation of multi-layer silicon structures by forming and attaching a plurality of individual layers or structures where each of the layers or the structures comprises at least silicon forming a desired pattern. In some embodiments or some applications of some embodiments, at least one of the plurality of individual layers or the structures comprises a plurality of discrete silicon features that are combined together with at least one sacrificial material. In some embodiments or some applications of some embodiments, at least one of the plurality of individual layers or the structures comprises a plurality of discrete silicon features that are supported by a temporary substrate. Still in some embodiments or some applications of some embodiments, at least one of the plurality of individual layers or the structures needs to be machined after it is attached to a receiver such as a substrate or an another layer or structure. The present invention also discloses various fabrication methods for making required silicon layers or structures and attaching methods for forming multi-layer silicon structures.
摘要翻译：本发明的实施例涉及通过形成和附接多个单独的层或结构来形成多层硅结构，其中每个层或结构至少包括形成期望图案的硅。在一些实施例或某些实施例的一些应用中，多个单独层或结构中的至少一个包括与至少一种牺牲材料组合在一起的多个离散硅特征。在一些实施例或一些实施例的一些应用中，多个单独层或结构中的至少一个包括由临时衬底支撑的多个离散硅特征。仍然在一些实施例或某些实施例的一些应用中，多个独立层或结构中的至少一个在其附接到例如基板或另一层或结构的接收器之后需要被加工。本发明还公开了制造所需硅层或结构的各种制造方法以及用于形成多层硅结构的附着方法。

66. 发明授权

US08022849B2 Phase to digital converter in all digital phase locked loop 有权
标题翻译：所有数字锁相环中的相数转换器
公开(公告)号：US08022849B2
公开(公告)日：2011-09-20
申请号：US12102768
申请日：2008-04-14
申请人： Gang Zhang , Abhishek Jajoo , Yiping Han
发明人： Gang Zhang , Abhishek Jajoo , Yiping Han
IPC分类号： H03M1/00
CPC分类号： H03L7/085 , H03L7/089 , H03L7/1976 , H03L2207/50
摘要： A phase to digital converter, all digital phase locked loop, and apparatus having an all digital phase locked loop are described herein. The phase to digital converter includes a phase to frequency converter driving a time to digital converter. The time to digital converter determines a magnitude and sign of the phase differences output by the phase to frequency converter. The time to digital converter utilizes tapped delay lines and looped feedback counters to enable measurement of small timing differences typical of a loop tracking process and large timing differences typical of an loop acquisition process. The tapped delay lines permit the measurement of fractions of a reference period and enable lower power operation of the phase to digital converter by reducing requirements on the speed of the reference clock.
摘要翻译：这里描述了一个相数转换器，全数字锁相环和具有全数字锁相环的装置。相数转换器包括驱动时间到数字转换器的相位到频率转换器。数字转换器的时间决定了相位变频器输出的相位差的大小和符号。数字转换器的时间利用抽头延迟线和环路反馈计数器来测量环路跟踪过程中典型的小时序差异以及循环采集过程的典型时间差。抽头延迟线允许测量参考周期的分数，并通过减少对参考时钟速度的要求，实现相位数字转换器的低功耗操作。

67. 发明申请

US20110137631A1 SIMULATION METHOD, SYSTEM AND PROGRAM PRODUCT 有权
标题翻译：模拟方法，系统和程序产品
公开(公告)号：US20110137631A1
公开(公告)日：2011-06-09
申请号：US12961479
申请日：2010-12-06
申请人： Hideaki Komatsu , Hitomi Takahashi , Gang Zhang
发明人： Hideaki Komatsu , Hitomi Takahashi , Gang Zhang
IPC分类号： G06F17/50
CPC分类号： G06F17/5009 , G05B13/04 , G05B17/00 , G05B19/406 , G05B19/4061 , G05B19/4063 , G05B23/0205 , G05B23/0243 , G06F1/03 , G06F8/34 , G06F11/3668 , G06F17/10
摘要： A system, program product and related method is provided for simulating operational processes of a machine having a plurality of operational functional blocks including nonlinear blocks. The method steps comprise converting a plurality of functional blocks into linear blocks such that the nonlinear blocks are divided into a plurality of states through switched linearization. The plurality of states generated by said switched linearization is then transitioned selectively based on a predetermined operational scenario. Each state is then tested separately to ensure that implementation of the states are safe. A first guard block is provided when a state is deemed unsafe such that the first guard block is enabled to cause a system shutdown so as to prevent further processing that can cause an unsafe result.
摘要翻译：提供了一种用于模拟具有包括非线性块的多个操作功能块的机器的操作过程的系统，程序产品和相关方法。方法步骤包括将多个功能块转换成线性块，使得非线性块通过切换线性化被分成多个状态。然后，基于预定的操作场景选择性地转换由所述切换线性化产生的多个状态。然后单独测试每个状态，以确保状态的实现是安全的。当状态被视为不安全时，提供第一保护块，使得第一保护块能够使系统关闭，以防止可能导致不安全结果的进一步处理。

68. 发明申请

US20110090998A1 ADC-BASED MIXED-MODE DIGITAL PHASE-LOCKED LOOP 失效
标题翻译：基于ADC的混合模式数字锁相环
公开(公告)号：US20110090998A1
公开(公告)日：2011-04-21
申请号：US12582661
申请日：2009-10-20
申请人： Gang Zhang
发明人： Gang Zhang
IPC分类号： H04L7/00 , H03D3/24
CPC分类号： H03L7/1072 , H03L7/093 , H03L7/1976
摘要： A Phase-Locked Loop (PLL) includes a Phase-to-Digital Converter (PDC), a programmable digital loop filter, a Digitally-Controlled Oscillator (DCO), and a loop divider. Within the PDC, phase information is converted into a stream of digital values by a charge pump and an Analog-to-Digital Converter (ADC). The stream of digital values is supplied to the digital loop filter which in turn supplies digital tuning words to the DCO. A number of types of ADCs can be used for the ADC including a continuous-time delta-sigma oversampling Digital ADC and a Successive Approximation ADC. The voltage signal on the charge pump output is a small amplitude midrange voltage signal. The small voltage amplitude of the signal leads to numerous advantages including improved charge pump linearity, reduced charge pump noise, and lower supply voltage operation of the overall PLL.
摘要翻译：锁相环（PLL）包括一个相位数转换器（PDC），一个可编程数字环路滤波器，一个数字控制振荡器（DCO）和一个环路分频器。在PDC中，相位信息由电荷泵和模数转换器（ADC）转换成数字值流。数字值流被提供给数字环路滤波器，数字环路滤波器又向DCO提供数字调谐字。 ADC可以使用多种类型的ADC，包括连续时间Δ-sigma过采样数字ADC和逐次逼近ADC。电荷泵输出上的电压信号是一个小幅度的中频电压信号。信号的小电压幅度导致许多优点，包括改善电荷泵线性度，降低电荷泵噪声，以及整个PLL的较低电源电压操作。

69. 发明授权

US07911247B2 Delta-sigma modulator clock dithering in a fractional-N phase-locked loop 有权
$Delta-sigma modulator clock dithering in a fractional-N phase-locked loop$
标题翻译： Delta-sigma调制器时钟在分数N锁相环中抖动
公开(公告)号：US07911247B2
公开(公告)日：2011-03-22
申请号：US12037503
申请日：2008-02-26
申请人： Yang Xu , Gang Zhang , Prasad S. Gudem
发明人： Yang Xu , Gang Zhang , Prasad S. Gudem
IPC分类号： H03L7/06
CPC分类号： H03L7/1974
摘要： The clock signal supplied to the delta-sigma modulator in a fractional-N phase-locked loop is dithered. In one example, the PLL includes a novel programmable clock dithering circuit. The programmable clock dithering circuit is controllable via a serial bus to dither the phase of the clock signal in a selected one of several ways. If the clock signal is dithered in a first way (pseudo-random phase dithering), then the power of digital noise generated by the delta-sigma modulator is spread over a frequency band, thereby reducing the degree to which the noise interferes with other circuitry. If the clock signal is dithered in a second way (rotational phase dithering), then the power of digital noise is frequency shifted such that the degree to which the noise interferes with the other circuitry is reduced. The programmable clock dithering circuit can be controlled in other ways. For example, dithering can be programmably disabled.
摘要翻译：在分数N锁相环中提供给Δ-Σ调制器的时钟信号被抖动。在一个示例中，PLL包括新颖的可编程时钟抖动电路。可编程时钟抖动电路可通过串行总线进行控制，以选择的几种方式对时钟信号的相位进行抖动。如果时钟信号以第一种方式抖动（伪随机相位抖动），则由Δ-Σ调制器产生的数字噪声的功率在频带上扩展，从而降低噪声干扰其他电路的程度。如果时钟信号以第二种方式抖动（旋转相位抖动），则数字噪声的功率被频移，使得噪声干扰另一电路的程度降低。可编程时钟抖动电路可以以其他方式进行控制。例如，抖动可以可编程地禁用。

70. 发明授权

US07876871B2 Linear phase frequency detector and charge pump for phase-locked loop 有权
标题翻译：用于锁相环的线性相位频率检测器和电荷泵
公开(公告)号：US07876871B2
公开(公告)日：2011-01-25
申请号：US11565062
申请日：2006-11-30
申请人： Gang Zhang
发明人： Gang Zhang
IPC分类号： H03D3/24
CPC分类号： H03L7/1976 , H03L7/0891
摘要： Techniques for achieving linear operation for a phase frequency detector and a charge pump in a phase-locked loop (PLL) are described. The phase frequency detector receives a reference signal and a clock signal, generates first and second signals based on the reference and clock signals, and resets the first and second signals based on only the first signal. The first and second signals may be up and down signals, respectively, or may be down and up signals, respectively. The phase frequency detector may delay the first signal by a predetermined amount, generate a reset signal based on the delayed first signal and the second signal, and reset the first and second signals with the reset signal. The charge pump receives the first and second signals and generates an output signal indicative of phase error between the reference and clock signals.
摘要翻译：描述了在锁相环（PLL）中实现相位频率检测器和电荷泵的线性操作的技术。相位频率检测器接收参考信号和时钟信号，基于参考和时钟信号产生第一和第二信号，并且仅基于第一信号复位第一和第二信号。第一和第二信号可以分别是上下信号，也可以分别是下降信号。相位频率检测器可以将第一信号延迟预定量，基于延迟的第一信号和第二信号产生复位信号，并用复位信号复位第一和第二信号。电荷泵接收第一和第二信号，并产生指示参考和时钟信号之间的相位误差的输出信号。

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