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61. 发明授权

US06704154B2 Decoding apparatus and decoding method 失效
标题翻译：解码装置和解码方法
公开(公告)号：US06704154B2
公开(公告)日：2004-03-09
申请号：US09986597
申请日：2001-11-09
申请人： Akihiko Hirano , Seiichi Mita , Yoshiju Watanabe
发明人： Akihiko Hirano , Seiichi Mita , Yoshiju Watanabe
IPC分类号： G11B2014
CPC分类号： G11B20/1833 , G11B5/012 , G11B5/09 , G11B20/10009 , H03M5/145 , H03M13/31
摘要： In a coding method which does not restrict a run length of “1” while data is recorded/reproduced, there are such a drawback that when an error correction is carried out, a total number of error data to be corrected is increased, and also errors of not-detectable data are increased. While data is coded, a continuous number of “1” contained in a code word is limited, and then an error correction is carried out inside a coding/decoding process operation. Thus, a recording/reproducing apparatus having a small number of decoding errors is available.
摘要翻译：在数据被记录/再现时不限制游程长度为“1”的编码方法存在这样的缺点：当执行错误校正时，增加要纠正的错误数据的总数，并且还不可检测数据的错误增加。在对数据进行编码的同时，对码字中包含的连续数“1”进行限制，然后在编码/解码处理动作中进行纠错。因此，具有少量解码错误的记录/再现装置是可用的。

62. 发明授权

US06661594B2 Signal processing circuit and information recording/reproducing apparatus using the same, and method for optimizing coefficients of equalizer circuit 有权
标题翻译：信号处理电路和使用该信号的信息记录/再现装置，以及用于优化均衡器电路的系数的方法
公开(公告)号：US06661594B2
公开(公告)日：2003-12-09
申请号：US10277695
申请日：2002-10-23
申请人： Naoki Satoh , Seiichi Mita , Shoichi Miyazawa , Terumi Takashi , Yosuke Hori , Yoshiju Watanabe , Akihiko Hirano , Satoshi Minoshima , Hideki Miyasaka , Toshihiro Nitta , Tomoaki Hirai , Ryushi Shimokawa , Koji Shida , Yasuhide Ouchi
发明人： Naoki Satoh , Seiichi Mita , Shoichi Miyazawa , Terumi Takashi , Yosuke Hori , Yoshiju Watanabe , Akihiko Hirano , Satoshi Minoshima , Hideki Miyasaka , Toshihiro Nitta , Tomoaki Hirai , Ryushi Shimokawa , Koji Shida , Yasuhide Ouchi
IPC分类号： G11B535
CPC分类号： G11B20/10055 , G11B5/035 , G11B5/09 , G11B20/10009 , G11B20/10481
摘要： A signal processing circuit for a magnetic recording/reproducing apparatus, including at least an AGC, a PLL, a LPF, an equalizer circuit and a detection circuit, wherein a coefficient compensation circuit is formed by defining a constitution of the equalizer circuit, an error detection circuit is provided which operates by receiving input from the detection circuit, and the LSI is formed by a plurality of analog and digital chips, and the analog and digital chips are connected by current-output type D/A converters connected to at least the AGC and the PLL.
摘要翻译：一种用于至少包括AGC，PLL，LPF，均衡器电路和检测电路的磁记录/再现装置的信号处理电路，其中通过定义均衡器电路的结构形成系数补偿电路，错误提供检测电路，其通过接收来自检测电路的输入而工作，并且LSI由多个模拟和数字芯片形成，并且模拟和数字芯片通过电流输出型D / A转换器连接至少至少 AGC和PLL。

63. 发明授权

US06334201B1 Decoding circuit and information processing apparatus 失效
标题翻译：解码电路和信息处理装置
公开(公告)号：US06334201B1
公开(公告)日：2001-12-25
申请号：US09093931
申请日：1998-06-09
申请人： Hideki Sawaguchi , Akihiko Hirano , Seiichi Mita , Terumi Takashi
发明人： Hideki Sawaguchi , Akihiko Hirano , Seiichi Mita , Terumi Takashi
IPC分类号： H03M1341
CPC分类号： G11B20/10296 , G11B20/10009 , H03M13/3961 , H03M13/41 , H03M13/6343 , H03M13/6502
摘要： A maximum likelihood decoding circuit is arranged to reduce power consumption through the effect of a Viterbi algorithm. A plurality of storing elements located vertically in a column and for storing each state survivor path information at the same time point are treated as storing element blocks in a manner to correspond to the combination (state) of intracode interferences. The outputs from the storing elements are again applied into the inputs of the corresponding storing elements contained in the same storing element block through path history selecting circuits. Each of the storing blocks is periodically started on the input timing of a receiving signal at each processing time point by starting signals (pointers) outputted from a starting signal (pointer) generated circuit. A storing element block output circuit and storing element block output terminals are provided in each of the storing element blocks so that a path memory circuit output may be outputted through an OR circuit.
摘要翻译：布置最大似然解码电路以通过维特比算法的效果来降低功耗。垂直定位在列中并用于在同一时间点存储每个状态幸存者路径信息的多个存储元件被视为对应于帧内干扰的组合（状态）的存储元件块。来自存储元件的输出通过路径历史选择电路再次应用于包含在相同存储元件块中的相应存储元件的输入。通过开始从起始信号（指针）产生电路输出的信号（指针），在每个处理时间点，通过接收信号的输入定时周期性地开始每个存储块。存储元件块输出电路和存储元件块输出端子设置在每个存储元件块中，使得路径存储器电路输出可以通过OR电路输出。

64. 发明授权

US6034998A Method of and apparatus for detecting phase 失效
标题翻译：检测相位的方法和装置
公开(公告)号：US6034998A
公开(公告)日：2000-03-07
申请号：US674864
申请日：1996-07-03
申请人： Terumi Takashi , Akihiko Hirano
发明人： Terumi Takashi , Akihiko Hirano
IPC分类号： G11B20/14 , G11B20/18 , H03L7/091 , H04L7/02 , H04L7/04 , H04L7/10 , H04L25/49
CPC分类号： H04L7/0062 , G11B20/1403 , H03L7/091 , H04L7/041 , H04L7/10
摘要： A phase-locked loop included in a reproduce signal processing circuit which as a magnetic recording and reproducing device or the like. The phase-locked loop accurately detects a phase and can be operated at high speed. The phase-locked loop includes a data determining circuit for judging data at individual times from sampled data in a plurality of samples and an estimated data string generating circuit for examining the correlation between each data string and each known phase-locked data string and sequentially generating the known phase-locked data string closet to the data string. A sampling phase is detected by performing an arithmetic operation on the data string estimated by the estimated data string generating circuit and the sampled data.
摘要翻译：包括在作为磁记录和再现装置等的再现信号处理电路中的锁相环。锁相环准确地检测相位并可以高速运行。锁相环包括数据确定电路，用于根据多个采样中的采样数据在单个时间判断数据，以及估计数据串产生电路，用于检查每个数据串与每个已知的锁相数据串之间的相关性，并依次产生已知的锁相数据串连接到数据串。通过对由估计数据串生成电路估计的数据串和采样数据执行算术运算来检测采样相位。

65. 发明授权

US5940416A Digital signal decoding apparatus and a decoding method used therein 失效
标题翻译：数字信号解码装置及其中使用的解码方法
公开(公告)号：US5940416A
公开(公告)日：1999-08-17
申请号：US881508
申请日：1997-06-24
申请人： Takushi Nishiya , Hideyuki Yamakawa , Shoichi Miyazawa, deceased , Seiichi Mita , Yoichi Uehara , Takashi Nara , Akihiko Hirano
发明人： Takushi Nishiya , Hideyuki Yamakawa , Shoichi Miyazawa, deceased , Seiichi Mita , Yoichi Uehara , Takashi Nara , Akihiko Hirano
IPC分类号： G11B20/18 , G11B20/10 , H03M13/23 , H03M13/41 , H04L25/497 , H03M13/00
CPC分类号： H03M13/6505 , G11B20/10009 , H03M13/3961 , H03M13/4107
摘要： A calculation concerning the input of a signal is removed from a branch metric calculation processing on a trellis diagram of an extended partial response class, and the calculation of branch metrics and the selection of survivor paths can be carried out by the subtraction of the survivor paths and the comparison of constants.
摘要翻译：关于信号输入的计算从扩展部分响应类的格状图上的分支度量计算处理中去除，并且分支度量的计算和幸存路径的选择可以通过减去幸存路径来执行和常数的比较。

66. 发明授权

US5633766A Magnetic disk storage apparatus with phase sync circuit having controllable response characteristics 失效
标题翻译：具有相位同步电路的磁盘存储装置具有可控的响应特性
公开(公告)号：US5633766A
公开(公告)日：1997-05-27
申请号：US360426
申请日：1994-12-21
申请人： Kenichi Hase , Syoichi Miyazawa , Ryutaro Horita , Shinichi Kojima , Akihiko Hirano , Akira Uragami
发明人： Kenichi Hase , Syoichi Miyazawa , Ryutaro Horita , Shinichi Kojima , Akihiko Hirano , Akira Uragami
IPC分类号： G11B5/012 , G11B20/14 , H03K3/282 , H03L7/089 , H03L7/093 , H03L7/095 , H03L7/099 , H03L7/107 , H04L7/033 , G11B5/09 , G11B15/04
CPC分类号： H03L7/093 , G11B20/1403 , G11B5/012 , H03K3/2821 , H03L7/089 , H03L7/0895 , H03L7/0898 , H03L7/095 , H03L7/099 , H03L7/107 , G11B2020/10916 , H03L2207/06 , H04L7/033
摘要： A magnetic disk storage apparatus provides with a phase locked loop or a phase sync circuit including a phase comparator, a charge pump, a filter and a voltage-controlled oscillator. The phase sync circuit includes a register which is connected to an information processing system and adapted to store therein the response characteristics of the phase comparator, the charge pump, the filter and the voltage-controlled oscillator as instructed from the information processing system. In this way, in accordance with the information on the response characteristics from the information processing system, the phase sync circuit is controlled thereby to assure a stable operation even in the case of the data transfer speed varying between inner and outer track such as occurs in a magnetic disk.
摘要翻译：磁盘存储装置提供锁相环或包括相位比较器，电荷泵，滤波器和压控振荡器的相位同步电路。相位同步电路包括连接到信息处理系统并适合于从信息处理系统指示的其中存储相位比较器，电荷泵，滤波器和压控振荡器的响应特性的寄存器。以这种方式，根据关于来自信息处理系统的响应特性的信息，控制相位同步电路，从而即使在内外轨道之间变化的数据传输速度的情况下也可以确保稳定的操作，例如发生在磁盘。

67. 发明授权

US5448424A AGC circuit and recording and reproducing apparatus using AGC circuit 失效
标题翻译： AGC电路和使用AGC电路的记录和再现设备
公开(公告)号：US5448424A
公开(公告)日：1995-09-05
申请号：US196478
申请日：1994-02-15
申请人： Akihiko Hirano , Terumi Takashi , Kazunori Iwabuchi , Hideyuki Yamakawa , Yoshiteru Ishida , Minoru Kosuge
发明人： Akihiko Hirano , Terumi Takashi , Kazunori Iwabuchi , Hideyuki Yamakawa , Yoshiteru Ishida , Minoru Kosuge
IPC分类号： G11B5/09 , G11B20/04 , G11B20/10 , G11B20/12 , G11B20/14 , H03G3/00 , H03G3/20 , H03G3/30 , H03G11/00 , G11B5/035
CPC分类号： G11B20/10055 , G11B20/10009 , G11B20/1403 , H03G3/001 , G11B20/1252
摘要： An AGC circuit is provided with a variable gain amplifier which changes an amplification gain of an input signal in accordance with an instruction; an extraction unit for extracting a value of an output of the variable gain amplifier at a predetermined interval; and a variable gain control unit for instructing the amplification gain of the variable gain amplifier in a manner such that the amplitude of the input signal is equal to a predetermined amplitude on the basis of the value extracted by the extraction unit. The variable gain control unit is provided with an error signal output device for squaring the value extracted by the extraction unit and for generating an error signal to instruct the amplification gain of the variable gain amplifier in a manner such that the amplitude of the input signal is equal to a predetermined amplitude on the basis of the square value and a square value just before it; and an integrating device for integrating the error signal from the error signal output device and for instructing the amplification gain of the variable gain amplifier.
摘要翻译： AGC电路设置有根据指令改变输入信号的放大增益的可变增益放大器; 提取单元，用于以预定间隔提取可变增益放大器的输出值; 以及可变增益控制单元，用于以使得输入信号的幅度基于由提取单元提取的值等于预定幅度的方式来指示可变增益放大器的放大增益。可变增益控制单元设置有误差信号输出装置，用于对由提取单元提取的值进行平方，并产生误差信号，以使得输入信号的振幅为基于正方形值等于预定幅度和刚好在其前的平方值; 以及用于积分来自误差信号输出装置的误差信号并用于指示可变增益放大器的放大增益的积分装置。

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