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61. 发明申请

US20060272921A1 Banknote acceptor using ultraviolet ray for verification 审中-公开
标题翻译：钞票受理人使用紫外线进行验证
公开(公告)号：US20060272921A1
公开(公告)日：2006-12-07
申请号：US11501108
申请日：2006-08-09
申请人： Tien-Yuan Chien , Shoe-Po Chan , Yueh-Ping Hsu
发明人： Tien-Yuan Chien , Shoe-Po Chan , Yueh-Ping Hsu
IPC分类号： G07D7/00 , G07F7/04 , G06K9/00 , G06K7/00
CPC分类号： G07D7/121 , G07D11/12 , G07D11/14 , G07F7/04
摘要： A banknote acceptor is disclosed to have a banknote verification assembly detachably mounted in a housing for verifying the authenticity of the inserted banknote by means of an optical transmitter module, which uses an UV LED to emit UV light through the inserted banknote, and an optical receiver module, which uses a phototransistor to receive light passed from the UV LED through the banknote and to produce a corresponding output signal indicative of the fluorescent reaction of the fluorescent characteristics of fluorescent filaments of the paper material or the fluorescent reaction of the ink of the inserted banknote for enabling a control unit to verify the authenticity of the inserted banknote and for enabling a banknote holding down mechanism to force the verified banknote into a money box and hold it in place.
摘要翻译：公开了一种纸币接收器，其具有可拆卸地安装在壳体中的钞票验证组件，用于通过使用UV LED通过插入的纸币发射UV光的光发送器模块来验证插入的纸币的真实性;以及光接收器模块，其使用光电晶体管来接收从UV LED通过纸币的光，并产生指示纸材料的荧光灯丝的荧光特性的荧光反应的相应输出信号或所插入的油墨的荧光反应纸币，用于使得控制单元能够验证所插入的纸币的真实性，并且能够使钞票保持机构将验证的纸币强制在货币箱中并将其保持在适当位置。

62. 发明申请

US20060252348A1 METHOD AND APPARATUS TO ENABLE ACCURATE WAFER PREDICTION 有权
标题翻译：使用准确的波形预测的方法和装置
公开(公告)号：US20060252348A1
公开(公告)日：2006-11-09
申请号：US11120896
申请日：2005-05-03
申请人： Chun-Hsien Lin , Ping-Hsu Chen , Sunny Wu , Francis Ko
发明人： Chun-Hsien Lin , Ping-Hsu Chen , Sunny Wu , Francis Ko
IPC分类号： B24B51/00 , B24B7/30 , B24B1/00
CPC分类号： G05B23/0297
摘要： A method for monitoring a processing tool in a semiconductor manufacturing facility includes selecting key hardware parameters for a virtual sensor system based on manufacturing data associated with a fabrication tool and collecting manufacturing data associated with the fabrication tool. The method further includes dynamically maintaining the virtual sensor system during the manufacture of a plurality of semiconductor products and using the virtual sensor system and the collected manufacturing data for predicting a condition of a semiconductor product after being processed by the fabrication tool.
摘要翻译：一种用于监测半导体制造设备中的处理工具的方法包括：基于与制造工具相关联的制造数据选择虚拟传感器系统的关键硬件参数并收集与制造工具相关联的制造数据。该方法还包括在多个半导体产品的制造期间动态地维持虚拟传感器系统，并且使用虚拟传感器系统和所收集的制造数据来预测由制造工具处理之后的半导体产品的状况。

63. 发明授权

US07129117B2 Method of embedding semiconductor chip in support plate and embedded structure thereof 有权
标题翻译：将半导体芯片嵌入支撑板及其嵌入结构的方法
公开(公告)号：US07129117B2
公开(公告)日：2006-10-31
申请号：US11008964
申请日：2004-12-13
申请人： Shih-Ping Hsu
发明人： Shih-Ping Hsu
IPC分类号： H01L21/48
CPC分类号： H01L21/56 , H01L23/3107 , H01L23/5389 , H01L24/19 , H01L24/20 , H01L24/24 , H01L24/82 , H01L25/50 , H01L2224/24227 , H01L2224/82039 , H01L2924/01029 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/14
摘要： A method of embedding a semiconductor chip in a support plate and an embedded structure thereof are proposed. A first dielectric layer having a reinforced filling material is provided, and a semiconductor chip is mounted on the first dielectric layer. A support plate having an opening and a second dielectric layer having a reinforced filling material are provided. The first dielectric layer mounted with the semiconductor chip, the support plate, and the second dielectric layer are pressed together, such that the semiconductor chip is received in the opening of the support plate, and the dielectric layers fill in a gap between the semiconductor chip and the opening of the support plate. The reinforced filling material of the dielectric layers can maintain flatness and consistency of the semiconductor chip embedded in the support plate, and fine circuits can be fabricated on the support plate by build-up and electroplating processes.
摘要翻译：提出了一种将半导体芯片嵌入支撑板及其嵌入结构中的方法。提供具有增强填充材料的第一电介质层，并且半导体芯片安装在第一电介质层上。提供具有开口的支撑板和具有增强填充材料的第二介电层。将安装有半导体芯片，支撑板和第二电介质层的第一电介质层压在一起，使得半导体芯片被接收在支撑板的开口中，并且电介质层填充在半导体芯片和支撑板的开口。电介质层的增强填充材料可以保持嵌入在支撑板中的半导体芯片的平坦度和一致性，并且可以通过堆积和电镀工艺在支撑板上制造精细的电路。

64. 发明申请

US20060228829A1 Method for fabricating a flip chip package 有权
标题翻译：制造倒装芯片封装的方法
公开(公告)号：US20060228829A1
公开(公告)日：2006-10-12
申请号：US11162328
申请日：2005-09-07
申请人： Shih-Ping Hsu
发明人： Shih-Ping Hsu
IPC分类号： H01L21/48 , H01L21/50 , H01L21/44
CPC分类号： H01L24/16 , H01L23/49894 , H01L24/81 , H01L24/97 , H01L2224/13099 , H01L2224/131 , H01L2224/13111 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/136 , H01L2224/16225 , H01L2224/16235 , H01L2224/16237 , H01L2224/32225 , H01L2224/73104 , H01L2224/73204 , H01L2224/81136 , H01L2224/8114 , H01L2224/81193 , H01L2224/81801 , H01L2224/83192 , H01L2224/83193 , H01L2224/97 , H01L2924/00013 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/15174 , H01L2924/15311 , H01L2924/30107 , H01L2224/81 , H01L2924/00014 , H01L2924/00
摘要： A flip chip packaging method is disclosed. First, a substrate is provided, in which the substrate comprises a plurality of integrated circuit (IC) package substrate units therein and the surface of each IC package substrate unit comprises a plurality of connecting pads. Next, an insulating layer with patterns is formed on the substrate and the connecting pads and a plurality of openings by partially exposing the upper surface of the connecting pads. Next, a conductive material is disposed within each opening. Next, a plurality of chips is provided, in which a plurality of conductive bumps is formed over the bottom surface of the chip. Lastly, the chips are mounted over the surface of the IC package substrate unit and the substrate is separated into a plurality of flip chip package structures, in which the surface of each flip chip package structure includes at least one chip.
摘要翻译：公开了一种倒装芯片封装方法。首先，提供基板，其中基板在其中包括多个集成电路（IC）封装基板单元，并且每个IC封装基板单元的表面包括多个连接焊盘。接下来，通过部分地暴露连接焊盘的上表面，在衬底和连接焊盘和多个开口上形成具有图案的绝缘层。接下来，在每个开口内设置导电材料。接下来，提供多个芯片，其中在芯片的底表面上形成多个导电凸块。最后，将芯片安装在IC封装基板单元的表面上，并且将基板分离成多个倒装芯片封装结构，其中每个倒装芯片封装结构的表面包括至少一个芯片。

65. 发明授权

US07112524B2 Substrate for pre-soldering material and fabrication method thereof 有权
标题翻译：预焊材料用基板及其制造方法
公开(公告)号：US07112524B2
公开(公告)日：2006-09-26
申请号：US10769451
申请日：2004-01-29
申请人： Shih-Ping Hsu , Chu-Chin Hu
发明人： Shih-Ping Hsu , Chu-Chin Hu
IPC分类号： H01L21/44
CPC分类号： H01L24/81 , H01L24/11 , H01L2224/0401 , H01L2224/05568 , H01L2224/11334 , H01L2224/11462 , H01L2224/1147 , H01L2224/11849 , H01L2224/13099 , H01L2224/13144 , H01L2224/13147 , H01L2224/16 , H01L2224/1607 , H01L2224/16225 , H01L2224/81191 , H01L2224/81192 , H01L2224/81193 , H01L2224/81801 , H01L2224/83102 , H01L2224/92125 , H01L2924/0002 , H01L2924/01006 , H01L2924/01012 , H01L2924/01015 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/0104 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01051 , H01L2924/01052 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/12042 , H01L2924/14 , H01L2924/1433 , H01L2924/15311 , H01L2924/15787 , H01L2924/351 , H05K3/3473 , H05K3/3484 , H05K2203/054 , H01L2924/00 , H01L2224/05552
摘要： A substrate for a pre-soldering material and a fabrication method of the substrate are proposed. The substrate having at least one surface formed with a plurality of conductive pads is provided. An insulating layer is formed over the surface of the substrate in such a way that a top surface of each of the conductive pads is exposed. Next, a conductive film and a resist layer are formed in sequence on the insulating layer and the conductive pads, wherein a plurality of openings are formed in the resist layer to expose a part of the conductive film above the conductive pad. Then, a pre-soldering material is deposited over the conductive pad by stencil printing or electroplating process.
摘要翻译：提出了一种用于预焊材料的衬底和该衬底的制造方法。提供具有形成有多个导电焊盘的至少一个表面的衬底。在衬底的表面上形成绝缘层，使得每个导电焊盘的顶表面露出。接下来，在绝缘层和导电焊盘上依次形成导电膜和抗蚀剂层，其中在抗蚀剂层中形成多个开口以暴露导电膜上方的导电膜的一部分。然后，通过模板印刷或电镀工艺将预焊材料沉积在导电焊盘上。

66. 发明申请

US20060177968A1 Method for fabricating semiconductor packages with semiconductor chips 审中-公开
标题翻译：制造具有半导体芯片的半导体封装的方法
公开(公告)号：US20060177968A1
公开(公告)日：2006-08-10
申请号：US11200009
申请日：2005-08-10
申请人： Shih-Ping Hsu
发明人： Shih-Ping Hsu
IPC分类号： H01L23/02 , H01L21/50 , H01L21/48 , H01L21/44
CPC分类号： H01L24/19 , H01L23/16 , H01L23/3128 , H01L23/36 , H01L24/97 , H01L2224/04105 , H01L2224/12105 , H01L2224/20 , H01L2224/7965 , H01L2224/97 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/15153 , H01L2924/1517 , H01L2924/15311 , H01L2924/19041 , H01L2924/19043 , H01L2224/82
摘要： A method for fabricating semiconductor packages with semiconductor chips includes: providing a reel tape capable of being rolled up, the reel tape for accommodating at least one row of carriers; mounting at least one semiconductor chip in each of the carriers, wherein a plurality of electrode pads are provided on an upper surface of the semiconductor chip; and forming a dielectric layer and a circuit layer on each set of the carriers and the semiconductor chips, wherein the circuit layer is electrically connected to the electrode pads of the semiconductor chip, so as to package the semiconductor chip in each of the carriers to form a package. The above method can continuously fabricate packages, and prevent imprecise positional alignment on a large carrier panel, as well as avoid the necessity of fabricating conductive bumps on the semiconductor chip for electrical connection, such that the fabrication costs can be reduced.
摘要翻译：一种用于制造具有半导体芯片的半导体封装的方法，包括：提供能够卷起的卷带，用于容纳至少一行载体的卷带; 在每个所述载体中安装至少一个半导体芯片，其中在所述半导体芯片的上表面上设置多个电极焊盘; 以及在每组载体和半导体芯片上形成电介质层和电路层，其中电路层电连接到半导体芯片的电极焊盘，以将半导体芯片封装在每个载体中以形成一套。上述方法可以连续地制造封装，并且防止在大载体面板上的不精确的位置对准，并且避免在用于电连接的半导体芯片上制造导电凸块的必要性，从而可以降低制造成本。

67. 发明申请

US20060145328A1 Three dimensional package structure with semiconductor chip embedded in substrate and method for fabricating the same 审中-公开
标题翻译：具有嵌入基板的半导体芯片的三维封装结构及其制造方法
公开(公告)号：US20060145328A1
公开(公告)日：2006-07-06
申请号：US11270945
申请日：2005-11-10
申请人： Shih-Ping Hsu
发明人： Shih-Ping Hsu
IPC分类号： H01L23/48
CPC分类号： H01L23/5389 , H01L24/19 , H01L24/20 , H01L24/24 , H01L24/25 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/16225 , H01L2224/20 , H01L2224/211 , H01L2224/24227 , H01L2224/2518 , H01L2224/73267 , H01L2924/01029 , H01L2924/01033 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/1517 , H01L2924/15311 , H01L2924/351 , H05K1/185 , H05K3/4602 , H05K2201/10674 , H01L2924/00
摘要： A three dimensional package structure with semiconductor chip embedded in substrate and a method for fabricating the same are proposed. A carrier with at least one cavity is mounted on a first insulating layer, and at least one semiconductor chip is mounted on the first insulating layer and received in the cavity of the carrier. A second insulating layer is formed on the carrier and the semiconductor chip. By performing a pressing process on both of the first insulating layer and the second insulating layer, a gap between the carrier and the semiconductor chip is filled. A circuit layer may be formed on the second insulating layer and is electrically connected to the semiconductor chip. Heat dissipating vias are formed in the first insulating layer and are connected to the semiconductor chip and a heat dissipating circuit so as to facilitate dissipation of heat generated from the semiconductor chip.
摘要翻译：提出了一种具有嵌入基板的半导体芯片的三维封装结构及其制造方法。具有至少一个空腔的载体安装在第一绝缘层上，并且至少一个半导体芯片安装在第一绝缘层上并被接收在载体的空腔中。在载体和半导体芯片上形成第二绝缘层。通过对第一绝缘层和第二绝缘层进行压制处理，填充载体和半导体芯片之间的间隙。电路层可以形成在第二绝缘层上并与半导体芯片电连接。散热通孔形成在第一绝缘层中并连接到半导体芯片和散热电路，以便于散发从半导体芯片产生的热量。

68. 发明申请

US20060131176A1 Multi-layer circuit board with fine pitches and fabricating method thereof 有权
公开(公告)号：US20060131176A1
公开(公告)日：2006-06-22
申请号：US11160413
申请日：2005-06-22
申请人： Shih-Ping Hsu
发明人： Shih-Ping Hsu
IPC分类号： C25D5/02
CPC分类号： C25D5/022 , H05K3/0023 , H05K3/045 , H05K3/107 , H05K3/421 , H05K3/423 , H05K3/4602 , H05K3/465 , H05K2201/0195 , H05K2201/09563 , H05K2203/0723 , Y10T29/53174
摘要： A method for fabricating a multi-layer circuit board with fine pitch is provided. First, a plurality of contact pads is disposed on a core substrate. Next, a first dielectric layer, a second dielectric layer, and a third dielectric layer are formed on the core circuit board, in which a plurality of patterned openings are formed in the third dielectric layer and a plurality of vias is formed in the first and second dielectric layer, and the vias are located at the openings corresponding to the contact pads. Next, a conductive seed layer is disposed on the patterned openings and vias and a conductive layer is disposed on the conductive seed layer for forming circuit in each patterned opening and conductive via. Finally, removing the conductive layers and the conductive seed layer on the surface of third dielectric layer and forming a separation for each conductive circuit at each opening.

69. 发明申请

US20060129257A1 Novel method and apparatus for integrating fault detection and real-time virtual metrology in an advanced process control framework 审中-公开
标题翻译：用于在先进的过程控制框架中集成故障检测和实时虚拟计量的新方法和装置
公开(公告)号：US20060129257A1
公开(公告)日：2006-06-15
申请号：US11011950
申请日：2004-12-13
申请人： Ping-Hsu Chen , Sunny Wu , Bing-Hung Chen , Francis Ko , Chun-Hsien Lin
发明人： Ping-Hsu Chen , Sunny Wu , Bing-Hung Chen , Francis Ko , Chun-Hsien Lin
IPC分类号： G06F19/00
CPC分类号： G05B19/4188 , G05B19/4184 , G05B2219/31357 , G05B2219/45031 , Y02P90/14 , Y02P90/24
摘要： A semiconductor manufacturing information framework to operate a processing tool includes a data acquisition system (DAS), a virtual metrology (VM) system, a fault detection and classification (FDC) system and an advanced process control (APC) system. The DAS is operable to receive data related to the processing of a workpiece by the processing tool or sensors coupled on tool. The VM system is operable to receive the data from the DAS and predict results of the workpiece processed by the processing tool or sensors. The VM system generates at least one first output indicative of the results. The FDC system is operable to receive the data and generate at least one second output indicative of an operating status of the processing tool. The APC system is operable to receive the at least one first or second outputs, and, in response, generate at least one third output to control the processing tool.
摘要翻译：用于操作处理工具的半导体制造信息框架包括数据采集系统（DAS），虚拟测量（VM）系统，故障检测和分类（FDC）系统以及高级过程控制（APC）系统）。 DAS可操作以通过耦合在工具上的处理工具或传感器接收与工件的处理有关的数据。 VM系统可操作以从DAS接收数据并预测由处理工具或传感器处理的工件的结果。 VM系统生成指示结果的至少一个第一输出。 FDC系统可操作以接收数据并产生指示处理工具的操作状态的至少一个第二输出。 APC系统可操作以接收至少一个第一或第二输出，并且作为响应，生成至少一个第三输出以控制处理工具。

70. 发明申请

US20060051952A1 Method for fabricating conductive bump of circuit board 有权
标题翻译：电路板导电凸块的制造方法
公开(公告)号：US20060051952A1
公开(公告)日：2006-03-09
申请号：US11079389
申请日：2005-03-15
申请人： Shih-Ping Hsu , Sao-Hsia Tang , Ying-Tung Wang , Wen-Hung Hu , Chao-Wen Shih , Meng-Da Chou
发明人： Shih-Ping Hsu , Sao-Hsia Tang , Ying-Tung Wang , Wen-Hung Hu , Chao-Wen Shih , Meng-Da Chou
IPC分类号： H01L21/44
CPC分类号： H05K3/3473 , H01L21/4853 , H01L23/49816 , H01L2224/0554 , H01L2224/05568 , H01L2224/05573 , H01L2224/16225 , H01L2924/00014 , H05K3/242 , H05K3/4602 , H05K2201/0352 , H05K2201/09436 , H05K2201/096 , H05K2203/043 , H05K2203/054 , H05K2203/0574 , H05K2203/1476 , H05K2203/1572 , H05K2203/1581 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A method for fabricating conductive bumps of a circuit board is proposed. First of all, a circuit board having a first surface and a corresponding second surface is provided. A circuit structure having a plurality of conductive pads is formed on each of the first surface and the second surface, and conductive structures are formed in the circuit board for electrically connecting the circuit structures. Also, an insulating layer having a plurality of openings penetrating therethrough is formed on the circuit board for exposing the conductive pad. Then, a conductive layer is formed on a surface of the insulating layer having the opening formed on the first surface of the circuit board. An electroplating process is performed via the conductive layer and the conductive structure, such that a conductive bump is formed on the conductive pad located on the second surface of the circuit board. Subsequently, a resist layer is formed on the second surface of the circuit board to cover the conductive bump, and another resist layer having openings penetrating therethrough is formed on the first surface of the circuit board to expose the conductive pad. Finally, a conductive bump is formed on the conductive pad located on the first surface of the circuit board by an electroplating process. By such arrangement, the conductive bumps are successively formed on the first surface and the second surface of the circuit board.
摘要翻译：提出了一种用于制造电路板的导电凸块的方法。首先，提供具有第一表面和相应的第二表面的电路板。在所述第一表面和所述第二表面中的每一个上形成具有多个导电焊盘的电路结构，并且在所述电路板中形成导电结构以电连接所述电路结构。此外，在电路板上形成具有贯穿其中的多个开口的绝缘层，用于暴露导电焊盘。然后，在具有形成在电路板的第一表面上的开口的绝缘层的表面上形成导电层。通过导电层和导电结构进行电镀处理，使得在位于电路板的第二表面上的导电焊盘上形成导电凸块。随后，在电路板的第二表面上形成抗蚀剂层以覆盖导电凸块，并且在电路板的第一表面上形成具有贯穿其中的开口的另一个抗蚀剂层，以露出导电焊盘。最后，通过电镀工艺在位于电路板的第一表面上的导电焊盘上形成导电凸块。通过这种布置，导电凸块依次形成在电路板的第一表面和第二表面上。

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