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61. 发明授权

US5827761A Method of making NMOS and devices with sequentially formed gates having different gate lengths 失效
标题翻译：制造具有不同栅极长度的具有顺序形成的栅极的NMOS和器件的方法
公开(公告)号：US5827761A
公开(公告)日：1998-10-27
申请号：US805537
申请日：1997-02-25
申请人： H. Jim Fulford, Jr. , Robert Dawson , Mark I. Gardner , Frederick N. Hause , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
发明人： H. Jim Fulford, Jr. , Robert Dawson , Mark I. Gardner , Frederick N. Hause , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
IPC分类号： H01L21/8238
CPC分类号： H01L21/82385
摘要： A method of making NMOS and PMOS devices with different gate lengths includes providing a semiconductor substrate with first and second active regions, forming a first gate over a portion of the first active region and a second gate over a portion of the second active region, wherein the first and second gates are formed in sequence and have different lengths, and forming a source and drain in the first active region and a source and drain in the second active region. Preferably, the first gate is defined by a first photoresist layer patterned with a first exposure time, the second gate is defined by a second photoresist layer patterned with a second exposure time, and the difference in gate lengths is due primarily to a difference between the first and second exposure times.
摘要翻译：制造具有不同栅极长度的NMOS和PMOS器件的方法包括：提供具有第一和第二有源区的半导体衬底，在第一有源区的一部分上形成第一栅极，在第二有源区的一部分上形成第二栅极，其中第一和第二栅极依次形成并且具有不同的长度，并且在第一有源区中形成源极和漏极以及在第二有源区中形成源极和漏极。优选地，第一栅极由以第一曝光时间图案化的第一光致抗蚀剂层限定，第二栅极由以第二曝光时间图案化的第二光致抗蚀剂层限定，并且栅极长度的差异主要是由于第一和第二曝光时间。

62. 发明授权

US5792706A Interlevel dielectric with air gaps to reduce permitivity 失效
标题翻译：具有气隙的层间电介质以降低介电常数
公开(公告)号：US5792706A
公开(公告)日：1998-08-11
申请号：US658457
申请日：1996-06-05
申请人： Mark W. Michael , Robert Dawson , Fred N. Hause , Basab Bandyopadhyay , H. Jim Fulford, Jr. , William S. Brennan
发明人： Mark W. Michael , Robert Dawson , Fred N. Hause , Basab Bandyopadhyay , H. Jim Fulford, Jr. , William S. Brennan
IPC分类号： H01L21/768 , H01L23/522 , H01L21/31
CPC分类号： H01L21/7682 , H01L23/5222 , H01L2924/0002
摘要： A reduced permittivity interlevel dielectric is provided. The interlevel dielectric is formed between two levels of interconnect. The interlevel dielectric comprises a first dielectric layer formed from a TEOS source deposited on a first level interconnect. The first dielectric contains air gaps at spaced intervals across the first dielectric. A second dielectric, preferably from a silane source is deposited upon said first dielectric. A second interconnect level is then placed on the second dielectric.
摘要翻译：提供了一种降低介电常数的层间电介质。层间电介质形成在两层互连之间。层间电介质包括由沉积在第一层互连上的TEOS源形成的第一介质层。第一电介质以间隔开的间隔跨越第一电介质。第二电介质，优选由硅烷源沉积在所述第一电介质上。然后将第二互连电平放置在第二电介质上。

63. 发明授权

US5767012A Method of forming a recessed interconnect structure 失效
标题翻译：形成凹陷互连结构的方法
公开(公告)号：US5767012A
公开(公告)日：1998-06-16
申请号：US660674
申请日：1996-06-05
申请人： H. Jim Fulford, Jr. , Basab Bandyopadhyay , Robert Dawson , Fred N. Hause , Mark W. Michael , William S. Brennan
发明人： H. Jim Fulford, Jr. , Basab Bandyopadhyay , Robert Dawson , Fred N. Hause , Mark W. Michael , William S. Brennan
IPC分类号： H01L21/302 , H01L21/3065 , H01L21/316 , H01L21/3205 , H01L21/768 , H01L21/822 , H01L23/52 , H01L23/522 , H01L27/04 , H01L21/283
CPC分类号： H01L23/5222 , H01L21/768 , H01L2924/0002
摘要： A method of forming a recessed interconnect structure is provided. The interconnect structure includes several levels of conductors, wherein conductors on one level are staggered with respect to conductors on another level. In densely spaced interconnect areas, interposed conductors are drawn to dissimilar elevational levels to lessen the capacitive coupling between the interconnects. By staggering every other interconnect line in the densely patterned areas, the interconnects are capable of carrying a larger amount of current with minimal capacitive coupling therebetween. The method of forming a recessed interconnect structure comprises forming a substantially coplanar set of the first conductors upon a semiconductor substrate, depositing a first dielectric layer on said first conductors, forming a trench in the first dielectric layer, depositing a conductive material in the trench, planarizing the conductive material an upper surface of the conductive material is substantially coplanar with an upper surface of the first dielectric, etching the conductive material until the upper surface of the conductive material is displaced below the upper surface of the first dielectric, forming a second dielectric on the conductive material and the first dielectric layer.
摘要翻译：提供一种形成凹陷互连结构的方法。互连结构包括多个级别的导体，其中一个层上的导体相对于另一层上的导体交错。在密集间隔的互连区域中，插入的导体被拉至不同的高度级以减小互连之间的电容耦合。通过交错密集图案化区域中的每隔一个互连线，互连能够承载更大量的电流并且在其间具有最小的电容耦合。形成凹陷互连结构的方法包括在半导体衬底上形成基本共面的第一导体组，在第一导体上沉积第一电介质层，在第一电介质层中形成沟槽，在沟槽中沉积导电材料，对导电材料进行平面化，导电材料的上表面与第一电介质的上表面基本共面，蚀刻导电材料，直到导电材料的上表面位于第一电介质的上表面以下，形成第二电介质在导电材料和第一介电层上。

64. 发明授权

US5766803A Mask generation technique for producing an integrated circuit with optimal metal interconnect layout for achieving global planarization 失效
公开(公告)号：US5766803A
公开(公告)日：1998-06-16
申请号：US659165
申请日：1996-06-05
申请人： Mark W. Michael , Robert Dawson , Fred N. Hause , Basab Bandyopadhyay , H. Jim Fulford, Jr. , William S. Brennan
发明人： Mark W. Michael , Robert Dawson , Fred N. Hause , Basab Bandyopadhyay , H. Jim Fulford, Jr. , William S. Brennan
IPC分类号： H01L21/033 , H01L21/3105 , H01L21/768 , G03F9/00
CPC分类号： H01L21/0334 , H01L21/31051 , H01L21/76819
摘要： A photolithography mask derivation process is provided for improving the overall planarity of interlevel dielectric deposited upon conductors formed by the derived photolithography mask. The photolithography mask is derived such that non-operational conductors are spaced a minimum distance from each other and from operational conductors to present a regular spaced arrangement of conductors upon which a dielectric layer can be deposited and readily planarized using, for example, chemical-mechanical polishing techniques. The resulting interlevel dielectric upper surface is globally planarized to an even elevational level across the entire semiconductor topography. The operational conductors are dissimilar from non-operational conductors in that the operational conductors are connected within a circuit path of an operational integrated circuit. Non-operational conductors are not connected within the integrated circuit path and generally are floating or are connected to a power supply. The non-operational conductors thereby do not contribute to the integrated circuit functionality other than to provide structural planarity to the overlying interlevel dielectric. The mask derivation process is applicable to either a metal interconnect photolithography mask or a polysilicon interconnect photolithography mask.

65. 发明授权

US5733798A Mask generation technique for producing an integrated circuit with optimal polysilicon interconnect layout for achieving global planarization 失效
公开(公告)号：US5733798A
公开(公告)日：1998-03-31
申请号：US655247
申请日：1996-06-05
申请人： Mark W. Michael , Robert Dawson , Fred N. Hause , Basab Bandyopadhyay , H. Jim Fulford, Jr. , William S. Brennan
发明人： Mark W. Michael , Robert Dawson , Fred N. Hause , Basab Bandyopadhyay , H. Jim Fulford, Jr. , William S. Brennan
IPC分类号： H01L21/3105 , H01L21/768 , H01L23/528 , H01L21/44 , H01L21/48
CPC分类号： H01L21/76819 , H01L21/31053 , H01L23/528 , H01L2924/0002
摘要： A photolithography mask derivation process is provided for improving the overall planarity of interlevel dielectric deposited upon conductors formed by the derived photolithography mask. The photolithography mask is derived such that non-operational conductors are spaced a minimum distance from each other and from operational conductors to present a regular spaced arrangement of conductors upon which a dielectric layer can be deposited and readily planarized using, for example, chemical-mechanical polishing techniques. The resulting interlevel dielectric upper surface is globally planarized to an even elevational level across the entire semiconductor topography. The operational conductors are dissimilar from non-operational conductors in that the operational conductors are connected within a circuit path of an operational integrated circuit. Non-operational conductors are not connected within the integrated circuit path and generally are floating or are connected to a power supply. The non-operational conductors thereby do not contribute to the integrated circuit functionality other than to provide structural planarity to the overlying interlevel dielectric. The mask derivation process is applicable to either a metal interconnect photolithography mask or a polysilicon interconnect photolithography mask.

66. 发明授权

US5723238A Inspection of lens error associated with lens heating in a photolithographic system 失效
标题翻译：在光刻系统中检查与透镜加热相关的透镜误差
公开(公告)号：US5723238A
公开(公告)日：1998-03-03
申请号：US760028
申请日：1996-12-04
申请人： Bradley T. Moore , Robert Dawson , H. Jim Fulford, Jr. , Mark I. Gardner , Frederick N. Hause , Mark W. Michael , Derick J. Wristers
发明人： Bradley T. Moore , Robert Dawson , H. Jim Fulford, Jr. , Mark I. Gardner , Frederick N. Hause , Mark W. Michael , Derick J. Wristers
IPC分类号： G03F7/20 , G03C5/00
CPC分类号： G03F7/70058 , G03F7/70591 , G03F7/70891
摘要： A method of inspecting a lens includes projecting a first amount of radiation through a first test pattern and the lens to provide a first lens error associated with a first heating of the lens, projecting a second amount of radiation through a second test pattern and the lens to provide a second lens error associated with a second heating of the lens, and using the first and second lens errors to provide image displacement data that varies as a function of heating the lens. In this manner, corrections can be made for localized lens heating that is unique to a given reticle. The method is well-suited for photolithographic systems such as step and repeat systems.
摘要翻译：检查透镜的方法包括：通过第一测试图案和透镜投射第一量的辐射，以提供与透镜的第一加热相关联的第一透镜误差，通过第二测试图案投射第二数量的辐射，并且透镜以提供与透镜的第二加热相关联的第二透镜误差，并且使用第一和第二透镜误差来提供作为加热透镜的函数而变化的图像位移数据。以这种方式，可以对给定掩模版特有的局部透镜加热进行校正。该方法非常适合于光刻系统，如步进和重复系统。

67. 发明授权

US5717242A Integrated circuit having local interconnect for reduing signal cross coupled noise 失效
公开(公告)号：US5717242A
公开(公告)日：1998-02-10
申请号：US633473
申请日：1996-04-17
申请人： Mark W. Michael , Robert Dawson , Basab Bandyopadhyay , H. Jim Fulford, Jr. , Fred N. Hause , William S. Brennan
发明人： Mark W. Michael , Robert Dawson , Basab Bandyopadhyay , H. Jim Fulford, Jr. , Fred N. Hause , William S. Brennan
IPC分类号： H01L21/768 , H01L23/522 , H01L23/528 , H01L27/11 , H01L29/76 , H01L29/94
CPC分类号： H01L23/5222 , H01L21/76895 , H01L23/5286 , H01L27/11 , H01L2924/0002
摘要： An integrated circuit is provided having an improved interconnect structure. The interconnect structure includes a power-coupled local interconnect which is always retained at VDD or VSS (i.e., ground) level. The local interconnect resides a dielectric-spaced distance below critical runs of overlying interconnect. The powered local interconnect serves to sink noise transients from the critical conductors to ensure that circuits connected to the conductors do not inoperably function. Accordingly, the local interconnect extends along a substantial portion of the conductor length, and is either wider or narrower than the conductor under which it extends. The local interconnect can either be polysilicon, doped polysilicon, polycide, refractory metal silicide, or multi-level refractory metal.

68. 发明申请

US20080104550A1 COMPENSATING FOR LAYOUT DIMENSION EFFECTS IN SEMICONDUCTOR DEVICE MODELING 失效
标题翻译：补偿半导体器件建模中的布局尺寸效应
公开(公告)号：US20080104550A1
公开(公告)日：2008-05-01
申请号：US11537390
申请日：2006-09-29
申请人： Akif Sultan , Jian Chen , Mark W. Michael , Jingrong R. Zhou
发明人： Akif Sultan , Jian Chen , Mark W. Michael , Jingrong R. Zhou
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A method includes receiving design data associated with an integrated circuit device. The integrated circuit device includes a first element having a corner defined therein and a second element overlapping the first element. A dimension specified for the first element in the design data is adjusted based on a distance between the second element and the corner. The integrated circuit device is simulated based on the adjusted dimension.
摘要翻译：一种方法包括接收与集成电路装置相关联的设计数据。集成电路装置包括具有限定在其中的角部的第一元件和与第一元件重叠的第二元件。基于第二元件和拐角之间的距离来调整为设计数据中的第一元件指定的尺寸。基于经调整的尺寸模拟集成电路器件。

69. 发明申请

US20080003789A1 PROVIDING STRESS UNIFORMITY IN A SEMICONDUCTOR DEVICE 有权
标题翻译：在半导体器件中提供应力均匀性
公开(公告)号：US20080003789A1
公开(公告)日：2008-01-03
申请号：US11428022
申请日：2006-06-30
申请人： Jian Chen , Mark W. Michael
发明人： Jian Chen , Mark W. Michael
IPC分类号： H01L21/3205
CPC分类号： H01L21/823418 , H01L21/823814 , H01L29/7843 , H01L29/7848
摘要： A method includes forming a plurality of functional features on a semiconductor layer in a first region. A non-functional feature corresponding to the functional feature is formed adjacent at least one of the functional features disposed on a periphery of the region. A stress-inducing layer is formed over at least a portion of the functional features and the non-functional feature. A device includes a semiconductor layer, a first dummy gate electrode, and a stress-inducing layer. The plurality of transistor gate electrodes is formed above the semiconductor layer. The plurality includes at least a first end gate electrode, a second end gate electrode, and at least one interior gate electrode. The first dummy gate electrode is disposed proximate the first end gate electrode. The stress-inducing layer is disposed over at least a portion of the plurality of transistor gate electrodes and the first dummy gate electrode.
摘要翻译：一种方法包括在第一区域中的半导体层上形成多个功能特征。相邻于功能特征的非功能特征形成在邻近设置在区域周边的功能特征中的至少一个功能特征。在功能特征和非功能特征的至少一部分上形成应力诱导层。一种器件包括半导体层，第一伪栅电极和应力诱导层。多个晶体管栅电极形成在半导体层的上方。多个至少包括第一端栅极电极，第二端栅极电极和至少一个内部栅极电极。第一虚拟栅电极设置在第一端栅电极附近。应力感应层设置在多个晶体管栅极电极和第一虚拟栅电极的至少一部分上。

70. 发明授权

US06353253B2 Semiconductor isolation region bounded by a trench and covered with an oxide to improve planarization 有权
标题翻译：由沟槽限定并被氧化物覆盖以改善平坦化的半导体隔离区
公开(公告)号：US06353253B2
公开(公告)日：2002-03-05
申请号：US09227914
申请日：1999-01-08
申请人： Fred N. Hause , Basab Bandyopadhyay , H. Jim Fulford, Jr. , Robert Dawson , Mark W. Michael , William S. Brennan
发明人： Fred N. Hause , Basab Bandyopadhyay , H. Jim Fulford, Jr. , Robert Dawson , Mark W. Michael , William S. Brennan
IPC分类号： H01L2900
CPC分类号： H01L21/76205 , H01L21/76229
摘要： An isolation technique is provided for improving the overall planarity of isolation regions relative to adjacent active area silicon mesas. The isolation process results in a trench formed in field regions immediately adjacent the active regions. The trench, however, does not extend entirely across the field region. By preventing large area trenches, substantial dielectric fill material and the problems of subsequent planarization of that fill material is avoided. Accordingly, the present isolation technique does not require conventional fill dielectric normally associated with a shallow trench process. While it achieves the advantages of forming silicon mesas, the present process avoids having to rework dielectric surfaces in large area field regions using conventional sacrificial etchback, block masking and chemical-mechanical polishing. The improved isolation technique hereof utilizes trenches of minimal width etched into the silicon substrate at the periphery of field regions, leaving a field mesa. A field dielectric, preferably oxide, is formed upon the field mesa and fills trenches between the field mesa and active mesas, leaving a substantially planar field dielectric commensurate with the upper surface of adjacent active mesas.
摘要翻译：提供隔离技术用于改善隔离区域相对于相邻有源区硅台面的整体平面度。隔离过程导致在紧邻有源区域的场区域中形成沟槽。然而，这个沟槽并不完全穿过田野区域。通过防止大面积沟槽，避免了大量的介电填充材料以及该填充材料随后的平坦化问题。因此，本发明的隔离技术不需要通常与浅沟槽工艺相关联的常规填充电介质。虽然它实现了形成硅台面的优点，但是本方法避免了使用常规的牺牲回蚀，块掩模和化学机械抛光在大面积场区域中的电介质表面的返修。其改进的隔离技术利用在场区周边蚀刻到硅衬底中的最小宽度的沟槽，留下场台面。在场台面上形成场电介质，优选氧化物，并填充场台面和有源台面之间的沟槽，留下与相邻活性台面的上表面相当的基本上平面的场电介质。

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