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61. 发明申请

US20130323898A1 METHOD OF LITHOGRAPHY PROCESS WITH AN UNDER ISOLATION MATERIAL LAYER 有权
标题翻译：具有隔离材料层的沉积工艺的方法
公开(公告)号：US20130323898A1
公开(公告)日：2013-12-05
申请号：US13486050
申请日：2012-06-01
申请人： Chung-Ming Wang , Yu Lun Liu , Chia-Chu Liu , Ya Hui Chang , Kuei-Shun Chen
发明人： Chung-Ming Wang , Yu Lun Liu , Chia-Chu Liu , Ya Hui Chang , Kuei-Shun Chen
IPC分类号： H01L21/28 , H01L21/336
CPC分类号： H01L29/78606 , H01L21/02118 , H01L21/02282 , H01L21/0271 , H01L21/2652 , H01L21/31144 , H01L27/1292 , H01L29/6659
摘要： A method of forming a integrated circuit pattern. The method includes forming gate stacks on a substrate, two adjacent gate stacks of the gate stacks being spaced away by a dimension G; forming a nitrogen-containing layer on the gate stacks and the substrate; forming a dielectric material layer on the nitrogen-containing layer, the dielectric material layer having a thickness T substantially less than G/2; coating a photoresist layer on the dielectric material layer; and patterning the photoresist layer by a lithography process.
摘要翻译：一种形成集成电路图案的方法。该方法包括在衬底上形成栅极堆叠，门堆叠的两个相邻栅堆叠被尺寸G间隔开; 在栅叠层和衬底上形成含氮层; 在所述含氮层上形成介电材料层，所述电介质材料层的厚度T大致小于G / 2; 在介电材料层上涂覆光致抗蚀剂层; 并通过光刻工艺图案化光致抗蚀剂层。

62. 发明申请

US20130320451A1 SEMICONDUCTOR DEVICE HAVING NON-ORTHOGONAL ELEMENT 审中-公开
标题翻译：具有非正交元素的半导体器件
公开(公告)号：US20130320451A1
公开(公告)日：2013-12-05
申请号：US13486185
申请日：2012-06-01
申请人： Chia-Chu Liu , Shiao-Chian Yeh , Hong-Jang Wu , Kuei-Shun Chen
发明人： Chia-Chu Liu , Shiao-Chian Yeh , Hong-Jang Wu , Kuei-Shun Chen
IPC分类号： H01L27/088 , H01L21/336
CPC分类号： H01L23/522 , H01L21/76895 , H01L27/0207 , H01L29/4238 , H01L29/66545 , H01L2924/0002 , H01L2924/00
摘要： The present disclosure provides a device includes a first gate structure segment and a collinear second gate structure segment, as well as a third gate structure segment and a collinear fourth gate structure segment. An interconnection extends from the first gate structure segment to the fourth gate structure segment. The interconnection is disposed above the first gate structure segment and the fourth gate structure segment. The interconnection may be formed on or co-planar with a contact layer of the semiconductor device.
摘要翻译：本公开提供了一种器件，包括第一栅极结构段和共线第二栅极结构段，以及第三栅极结构段和共线第四栅极结构段。互连从第一栅极结构段延伸到第四栅极结构段。互连设置在第一栅极结构段和第四栅极结构段之上。互连可以形成在半导体器件的接触层上或与其共面。

63. 发明申请

US20130256809A1 ELECTRICAL-FREE DUMMY GATE 有权
标题翻译：电动门
公开(公告)号：US20130256809A1
公开(公告)日：2013-10-03
申请号：US13431072
申请日：2012-03-27
申请人： Chia-Chu Liu , Kuei Shun Chen , Chiang Mu-Chi
发明人： Chia-Chu Liu , Kuei Shun Chen , Chiang Mu-Chi
IPC分类号： H01L29/423 , H01L27/088 , H01L21/283
CPC分类号： H01L21/28123 , H01L29/42372 , H01L29/78
摘要： The present disclosure provides a semiconductor device. The semiconductor device includes an electrical-free dummy gate formed over a substrate. The dummy gate has an elongate shape and is oriented along a first direction. The semiconductor device includes a first functional gate formed over the substrate. The first functional gate has an elongate shape and is oriented along the first direction. The first functional gate is separated from the dummy gate in a second direction perpendicular to the first direction. A first conductive contact is formed on the first functional gate. The semiconductor device includes a second functional gate formed over the substrate. The second functional gate has an elongate shape and is oriented along the first direction. The second functional gate is aligned with and physically separated from the dummy gate in the first direction. A second conductive contact is formed on the second functional gate.
摘要翻译：本发明提供一种半导体器件。半导体器件包括形成在衬底上的无电虚拟栅极。虚拟门具有细长形状并且沿着第一方向定向。半导体器件包括形成在衬底上的第一功能栅极。第一功能门具有细长形状并且沿着第一方向定向。第一功能门在垂直于第一方向的第二方向上与虚拟栅极分离。在第一功能栅极上形成第一导电接触。半导体器件包括形成在衬底上的第二功能栅极。第二功能门具有细长形状并且沿着第一方向定向。第二功能门与第一方向上的虚拟栅极对准并在物理上分离。在第二功能栅极上形成第二导电接触。

64. 发明授权

US08178289B2 System and method for photolithography in semiconductor manufacturing 有权
标题翻译：半导体制造中的光刻系统及方法
公开(公告)号：US08178289B2
公开(公告)日：2012-05-15
申请号：US12362316
申请日：2009-01-29
申请人： Kuei Shun Chen , Chin-Hsiang Lin , David Ding-Chung Lu
发明人： Kuei Shun Chen , Chin-Hsiang Lin , David Ding-Chung Lu
IPC分类号： G03F7/20 , G03F7/26
CPC分类号： G03F7/70341 , G03F7/203 , G03F7/70466
摘要： A method for producing a pattern on a substrate includes providing at least one exposure of the pattern onto a layer of the substrate by a higher-precision lithography mechanism and providing at least one exposure of the pattern onto a layer of the substrate by a lower-precision lithography mechanism. The exposures can be done in either order, and additional exposures can be included. The higher-precision lithography mechanism can be immersion lithography and the lower-precision lithography mechanism can be dry lithography.
摘要翻译：用于在衬底上产生图案的方法包括通过更高精度的光刻机构将图案的至少一次曝光提供到衬底的层上，并且通过较低精度的光刻机提供图案的至少一次曝光到衬底的层上，精密光刻机制。曝光可以以任一顺序完成，并可以包括额外的曝光。高精度光刻机构可以是浸没式光刻技术，较低精度的光刻机构可以是干式光刻技术。

65. 发明申请

US20110241119A1 SYSTEM AND METHOD FOR PROVIDING ALIGNMENT MARK FOR HIGH-K METAL GATE PROCESS 有权
标题翻译：用于提供高K金属栅工艺的对准标记的系统和方法
公开(公告)号：US20110241119A1
公开(公告)日：2011-10-06
申请号：US12835415
申请日：2010-07-13
申请人： Kuei Shun Chen , Meng-Wei Chen , George Liu , Jiann Yuan Huang , Chia-Ching Lin
发明人： Kuei Shun Chen , Meng-Wei Chen , George Liu , Jiann Yuan Huang , Chia-Ching Lin
IPC分类号： H01L23/544 , H01L21/762
CPC分类号： G03F9/7084 , G03F9/7076 , G03F9/708 , H01L21/76229
摘要： The alignment mark and method for making the same are described. In one embodiment, a semiconductor structure includes a substrate having a device region and an alignment region; a first shallow trench isolation (STI) feature in the alignment region and having a first depth D1; a second STI feature in the device region and having a second depth D2; an alignment mark with patterned features overlying the first STI in the alignment region; and a gate stack formed on an active region in the device region.
摘要翻译：对准标记及其制作方法进行说明。在一个实施例中，半导体结构包括具有器件区域和对准区域的衬底; 在对准区域中的第一浅沟槽隔离（STI）特征并且具有第一深度D1; 在设备区域中具有第二深度D2的第二STI特征; 具有覆盖对准区域中的第一STI的图案特征的对准标记; 以及形成在器件区域中的有源区上的栅极堆叠。

66. 发明授权

US07811720B2 Utilizing compensation features in photolithography for semiconductor device fabrication 有权
标题翻译：利用光刻中的补偿特性进行半导体器件制造
公开(公告)号：US07811720B2
公开(公告)日：2010-10-12
申请号：US11044517
申请日：2005-01-27
申请人： Kuei Shun Chen , Chin-Hsiang Lin , Chih-Cheng Chiu
发明人： Kuei Shun Chen , Chin-Hsiang Lin , Chih-Cheng Chiu
IPC分类号： G03F1/00
CPC分类号： G03F1/36 , G03F1/70
摘要： A photomask set includes at least two masks that combine to form a device pattern in a semiconductor device. Orthogonal corners may be produced in a semiconductor device pattern to include one edge defined by a first mask and an orthogonal edge defined by a second mask. The mask set may include a first mask with compensation features and a second mask with void areas overlaying the compensation features when the first and second masks are aligned with one another, such that the compensation features are removed when patterns are successfully formed from the first and second masks. The compensation features alleviate proximity effects during the formation of device features.
摘要翻译：光掩模组包括组合以在半导体器件中形成器件图案的至少两个掩模。可以在半导体器件图案中产生正交角，以包括由第一掩模限定的一个边缘和由第二掩模限定的正交边缘。掩模组可以包括具有补偿特征的第一掩模和当第一和第二掩模彼此对准时覆盖补偿特征的空隙区域的第二掩模，使得当从第一和第二掩模成功形成图案时，补偿特征被去除第二个面具补偿功能可以减轻设备特征形成过程中的邻近效应。

67. 发明授权

US07767570B2 Dummy vias for damascene process 有权
标题翻译：用于大马士革过程的虚拟通孔
公开(公告)号：US07767570B2
公开(公告)日：2010-08-03
申请号：US11457032
申请日：2006-07-12
申请人： Kuei Shun Chen , Chin-Hsiang Lin , Vencent Chang , Lawrence Lin , Lai Chien Wen , Jhun Hua Chen
发明人： Kuei Shun Chen , Chin-Hsiang Lin , Vencent Chang , Lawrence Lin , Lai Chien Wen , Jhun Hua Chen
IPC分类号： H01L21/00
CPC分类号： H01L21/76811 , H01L21/76807 , H01L21/76813 , H01L21/7684 , H01L23/522 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： A method of making an integrated circuit includes providing a low-k dielectric layer on a substrate, the low-k dielectric layer including or adjacent to a plurality of conductive features; patterning the low-k dielectric layer to form trenches; patterning the low-k dielectric layer to form conductive vias and dummy vias, wherein each of the conductive vias is aligned with at least one of the plurality of the conductive features and at least one of the trenches, and each of the dummy vias is a distance above the plurality of conductive features; filling the trenches, conductive vias, and dummy vias using one or more conductive materials; and planarizing the conductive material(s).
摘要翻译：制造集成电路的方法包括在衬底上提供低k电介质层，低k电介质层包括或邻近多个导电特征; 图案化低k电介质层以形成沟槽; 图案化低k电介质层以形成导电通孔和虚拟通孔，其中每个导电通孔与多个导电特征和至少一个沟槽中的至少一个对准，并且每个虚拟通孔为在多个导电特征之上的距离; 使用一种或多种导电材料填充沟槽，导电通孔和虚拟通孔; 并平坦化导电材料。

68. 发明授权

US07642101B2 Semiconductor device having in-chip critical dimension and focus patterns 失效
标题翻译：具有芯片临界尺寸和聚焦图案的半导体器件
公开(公告)号：US07642101B2
公开(公告)日：2010-01-05
申请号：US11567055
申请日：2006-12-05
申请人： George Liu , Vencent Chang , Chin-Hsiang Lin , Kuei Shun Chen , Norman Chen
发明人： George Liu , Vencent Chang , Chin-Hsiang Lin , Kuei Shun Chen , Norman Chen
IPC分类号： H01L21/66 , G01R31/26
CPC分类号： H01L23/544 , G03F7/70625 , G03F7/70641 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device is fabricated to include one or more sets of calibration patterns used to measure line pitch and line focus.
摘要翻译：制造半导体器件以包括用于测量线间距和线焦点的一组或多组校准图案。

69. 发明申请

US20090053899A1 METHOD OF PATTERN FORMATION IN SEMICONDUCTOR FABRICATION 有权
标题翻译：半导体制造中图案形成的方法
公开(公告)号：US20090053899A1
公开(公告)日：2009-02-26
申请号：US11841485
申请日：2007-08-20
申请人： George Liu , Kuei Shun Chen , Vencent Chang , Shang-Wen Chang
发明人： George Liu , Kuei Shun Chen , Vencent Chang , Shang-Wen Chang
IPC分类号： H01L21/311 , G03C5/00
CPC分类号： H01L21/32139 , G03F7/091 , G03F7/095 , H01L21/0273 , Y10S438/952
摘要： Provided is a method of fabricating a semiconductor device. The method includes providing a substrate, forming a photo acid generator (PAG) layer on the substrate, exposing the PAG layer to radiation, and forming a photoresist layer on the exposed PAG layer. The exposed PAG layer generates an acid. The acid decomposes a portion of the formed photoresist layer. In one embodiment, the PAG layer includes organic BARC. The decomposed portion of the photoresist layer may be used as a masking element.
摘要翻译：提供一种制造半导体器件的方法。该方法包括提供衬底，在衬底上形成光酸产生剂（PAG）层，将PAG层暴露于辐射，以及在曝光的PAG层上形成光致抗蚀剂层。暴露的PAG层产生酸。酸分解形成的光致抗蚀剂层的一部分。在一个实施例中，PAG层包括有机BARC。光致抗蚀剂层的分解部分可以用作掩模元件。

70. 发明授权

US07387969B2 Top patterned hardmask and method for patterning 有权
标题翻译：顶部图案化硬掩模和图案化方法
公开(公告)号：US07387969B2
公开(公告)日：2008-06-17
申请号：US11084495
申请日：2005-03-18
申请人： George Liu , Vencent Chang , Norman Chen , Yao-Ching Ku , Chin-Hsiang Lin , Kuei Shun Chen
发明人： George Liu , Vencent Chang , Norman Chen , Yao-Ching Ku , Chin-Hsiang Lin , Kuei Shun Chen
IPC分类号： H01L21/302
CPC分类号： H01L21/31144 , G03F7/11 , H01L21/0274 , H01L21/0332 , H01L21/76807
摘要： A patterned hardmask and method for forming the same, the method including providing a substrate comprising an overlying resist sensitive to activating radiation; forming an overlying hardmask insensitive to the activating radiation; exposing the resist through the hardmask to the activating radiation; baking the resist and the hardmask; and, developing the hardmask and resist to form a patterned resist and patterned hardmask.
摘要翻译：一种图案化硬掩模及其形成方法，所述方法包括提供包含对活化辐射敏感的上覆抗蚀剂的基底; 形成对激活辐射不敏感的上覆硬掩模; 将抗蚀剂通过硬掩模暴露于活化辐射; 烘烤抗蚀剂和硬掩模; 并开发硬掩模和抗蚀剂以形成图案化的抗蚀剂和图案化的硬掩模。

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