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61. 发明授权

US08553445B2 Semiconductor memory device having stacked structure including resistor-switched based logic circuit and method of manufacturing the same 有权
标题翻译：具有堆叠结构的半导体存储器件，包括基于电阻开关的逻辑电路及其制造方法
公开(公告)号：US08553445B2
公开(公告)日：2013-10-08
申请号：US13224410
申请日：2011-09-02
申请人： In-gyu Baek , Hong-sun Hwang , Hak-soo Yu , Chul-woo Park
发明人： In-gyu Baek , Hong-sun Hwang , Hak-soo Yu , Chul-woo Park
IPC分类号： G11C11/00
CPC分类号： H01L45/147 , G11C5/025 , G11C13/0002 , G11C2213/71 , G11C2213/72 , H01L27/2409 , H01L27/2481 , H01L45/14
摘要： Semiconductor memory device having a stacking structure including resistor switch based logic circuits. The semiconductor memory device includes a first conductive line that includes a first line portion and a second line portion, wherein the first line portion and the second line portion are electrically separated from each other by an intermediate region disposed between the first and second line portions, a first variable resistance material film that is connected to the first line portion and stores data, and a second variable resistance material film that controls an electrical connection between the first line portion and the second line portion.
摘要翻译：具有包括基于电阻器开关的逻辑电路的堆叠结构的半导体存储器件。半导体存储器件包括第一导线，其包括第一线部分和第二线部分，其中第一线部分和第二线部分通过布置在第一线部分和第二线部分之间的中间区域彼此电分离，连接到第一线部分并存储数据的第一可变电阻材料膜和控制第一线部分和第二线部分之间的电连接的第二可变电阻材料膜。

62. 发明申请

US20120230139A1 SEMICONDUCTOR MEMORY DEVICE HAVING A HIERARCHICAL BIT LINE SCHEME 有权
标题翻译：具有分层位线方案的半导体存储器件
公开(公告)号：US20120230139A1
公开(公告)日：2012-09-13
申请号：US13413938
申请日：2012-03-07
申请人： Jong-pil Son , Chul-woo Park , Young-hyun Jun , Hong-sun Hwang , Hak-soo Yu
发明人： Jong-pil Son , Chul-woo Park , Young-hyun Jun , Hong-sun Hwang , Hak-soo Yu
IPC分类号： G11C7/06 , G11C7/12
CPC分类号： G11C11/419 , G11C11/4091 , G11C11/4094 , G11C11/4097
摘要： A semiconductor memory device including a bit line connected to a memory cell and a sense amplifier configured to drive a voltage level of a global bit line in response to a voltage level of the bit line. The sense amplifier provides data that is complementary to data stored in the memory cell to the global bit line and provides the complementary data of the global bit line to the memory cell during an active operation of the memory cell.
摘要翻译：一种半导体存储器件，包括连接到存储单元的位线和被配置为响应于位线的电压电平驱动全局位线的电压电平的读出放大器。感测放大器提供与存储在存储器单元中的数据互补的数据到全局位线，并且在存储器单元的有效操作期间将全局位线的互补数据提供给存储单元。

63. 发明申请

US20120212989A1 MEMORY CORE AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME 有权
标题翻译：存储核心和半导体存储器件，包括它们
公开(公告)号：US20120212989A1
公开(公告)日：2012-08-23
申请号：US13304851
申请日：2011-11-28
申请人： Hak-Soo YU , Su-A Kim , Hong-Sun Hwang , Chul-Woo Park
发明人： Hak-Soo YU , Su-A Kim , Hong-Sun Hwang , Chul-Woo Park
IPC分类号： G11C5/02
CPC分类号： G11C7/02 , G11C7/062 , H01L27/10882 , H01L27/10885 , H01L27/10891 , H01L27/10897
摘要： A semiconductor memory device is disclosed. The semiconductor memory device includes a memory array block, a first word line and a second word line. The memory array block includes a plurality of adjacent columns of memory cells, each column of memory cells including a plurality of consecutive memory cells having a plurality of respective consecutive cell transistors that comprise at least a first group of cell transistors and a second group of cell transistors. The first word line is disposed above the plurality of respective consecutive cell transistors and electrically connected to the first group of cell transistors, and the second word line is disposed below the plurality of respective consecutive cell transistors and electrically connected to the second group of cell transistors.
摘要翻译：公开了一种半导体存储器件。半导体存储器件包括存储器阵列块，第一字线和第二字线。存储器阵列块包括多个相邻列的存储器单元，每列存储器单元包括多个连续的存储单元，其具有多个相应的连续单元晶体管，其包括至少第一组单元晶体管和第二组单元晶体管。第一字线设置在多个相应的连续单元晶体管的上方并电连接到第一组单元晶体管，第二字线设置在多个相应的连续单元晶体管的下方，并电连接到第二组单元晶体管。

64. 发明申请

US20120020142A1 RESISTIVE MEMORY 有权
标题翻译：电阻记忆
公开(公告)号：US20120020142A1
公开(公告)日：2012-01-26
申请号：US13184795
申请日：2011-07-18
申请人： Hak Soo Yu , In Gyu Baek , Hong Sun Hwang , Su A. Kim , Mu Jin Seo
发明人： Hak Soo Yu , In Gyu Baek , Hong Sun Hwang , Su A. Kim , Mu Jin Seo
IPC分类号： G11C11/00
CPC分类号： G11C8/14 , G11C8/10 , G11C13/0004 , G11C13/0007 , G11C13/0023 , G11C13/0026 , G11C13/0028 , G11C2213/71
摘要： Provided is a semiconductor resistive memory device. The resistive memory device includes a plurality of unit cells. A source line and a data input/output line of the unit cells may be selectively connected to have a substantially same voltage level for equalization when the unit cells are in inactive or unselected state. The equalization may decrease current consumption and protect write error, and protect leakage current.
摘要翻译：提供了半导体电阻式存储器件。电阻式存储器件包括多个单元电池。单位单元的源极线和数据输入/输出线可以被选择性地连接以具有基本上相同的电压电平以用于在单位电池处于非活动状态或未选择状态时进行均衡。均衡可能会降低电流消耗并保护写入错误，并保护漏电流。

65. 发明申请

US20110305100A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20110305100A1
公开(公告)日：2011-12-15
申请号：US13152316
申请日：2011-06-03
申请人： Hak-soo YU , In-gyu BAEK , Hong-sun Hwang , Young-kug MOON
发明人： Hak-soo YU , In-gyu BAEK , Hong-sun Hwang , Young-kug MOON
IPC分类号： G11C5/14
CPC分类号： G11C5/063 , G11C5/025
摘要： A semiconductor memory device including a plurality of layers each including a memory cell array and which are stacked over each other; and at least one power plane for supplying power to the layers. The power plane includes a region to which a power voltage is applied and a region to which a ground voltage is applied. The region to which a power voltage is applied is located adjacent to the region to which a ground voltage is applied, and forms a decoupling capacitor therebetween to decouple an influx of power noise to the layers or generation of power noise in the layers
摘要翻译：一种半导体存储器件，包括多个层，每个层包括存储单元阵列并彼此堆叠; 以及用于向层供电的至少一个电力平面。电力平面包括施加电源电压的区域和施加接地电压的区域。施加电源电压的区域位于与施加接地电压的区域相邻的位置处，并且在其间形成去耦电容器以将功率噪声流入到层中或在层中产生功率噪声

66. 发明申请

US20070104006A1 Memory core and method thereof 失效
标题翻译：内存核心及其方法
公开(公告)号：US20070104006A1
公开(公告)日：2007-05-10
申请号：US11584565
申请日：2006-10-23
申请人： Hong-Sun Hwang
发明人： Hong-Sun Hwang
IPC分类号： G11C7/02
CPC分类号： G11C29/24 , G11C7/1078 , G11C7/1096 , G11C7/18 , G11C11/401 , G11C11/4096 , G11C11/4097 , G11C2029/1204
摘要： A memory core and method thereof are provided. The example memory core may include an edge sub-array including a plurality of word lines, a plurality of bit lines, and a plurality of dummy bit lines, a sense amplifier circuit configured to amplify voltages of the plurality of dummy bit lines and a switching circuit configured to transfer at least one input data through the plurality of dummy bit lines, in response to at least one column select signal. The example method may include generating test input data in response to a test enable signal and a write signal, transferring the test input data to a plurality of dummy bit lines, in response to at least one column select signal and amplifying the test input data transferred to the plurality of dummy bit lines.
摘要翻译：提供了一种记忆核心及其方法。示例性存储器芯可以包括包括多个字线，多个位线和多个虚拟位线的边缘子阵列，被配置为放大多个虚拟位线的电压的读出放大器电路和切换电路，被配置为响应于至少一个列选择信号，通过所述多个虚拟位线传送至少一个输入数据。该示例性方法可以响应于至少一个列选择信号而产生测试输入数据，该测试输入数据响应于测试使能信号和写入信号，将测试输入数据传送到多个虚拟位线，并放大传输的测试输入数据到多个虚拟位线。

67. 发明申请

US20060181946A1 Full-stress testable memory device having an open bit line architecture and method of testing the same 有权
标题翻译：具有开放位线架构的全压力可测试存储器件及其测试方法
公开(公告)号：US20060181946A1
公开(公告)日：2006-08-17
申请号：US11319247
申请日：2005-12-27
申请人： Ki-Won Park , Hong-Sun Hwang , Sung-Ryul Kim
发明人： Ki-Won Park , Hong-Sun Hwang , Sung-Ryul Kim
IPC分类号： G11C7/02
CPC分类号： G11C7/18 , G11C29/12005 , G11C29/24 , G11C2029/1204
摘要： A full-stress testable memory device having an open bit line architecture and a method of testing the memory device. The memory device of the invention includes dummy bit lines, and a voltage controller connected to the dummy bit lines. The voltage controller alternately provides a first variable control voltage and a second variable control voltage to the dummy bit lines during a test mode. In accordance with a method of testing the memory device, a fixed voltage is provided to the dummy bit lines of the edge sub-arrays during a normal operation mode. However, during a test mode, the fixed voltage being applied to the dummy bit line is replaced with a supply voltage and/or a ground voltage, so that all of the sub-arrays can be equally tested.
摘要翻译：具有开放位线架构的全压力可测试存储器件和测试存储器件的方法。本发明的存储器件包括虚拟位线和连接到虚拟位线的电压控制器。电压控制器在测试模式期间交替地向虚拟位线提供第一可变控制电压和第二可变控制电压。根据测试存储器件的方法，在正常操作模式期间，将固定电压提供给边缘子阵列的虚拟位线。然而，在测试模式期间，施加到虚拟位线的固定电压被替换为电源电压和/或接地电压，使得可以对所有子阵列进行同样的测试。

68. 发明申请

US20060098503A1 Apparatus and method for repairing semiconductor memory device 失效
标题翻译：用于修复半导体存储器件的装置和方法
公开(公告)号：US20060098503A1
公开(公告)日：2006-05-11
申请号：US11270184
申请日：2005-11-09
申请人： Chang-Yeong Jeong , Hong-Sun Hwang
发明人： Chang-Yeong Jeong , Hong-Sun Hwang
IPC分类号： G11C29/00
CPC分类号： G11C29/808
摘要： Apparatus and methods are provided for repairing semiconductor memory devices having an open bit line sense amplifier architecture with cell array blocks having memory blocks formed of edge sub-blocks, main sub-blocks, dummy sub-blocks. Row defects can be processed using a straight edge block when DQ data are outputted by enabling three word lines such that a repair process for the memory device in an edge sub-block or a dummy sub-block has the same repair efficiency as that of a case where defects occur in a main sub-block.
摘要翻译：提供了用于修复具有开放位线读出放大器架构的半导体存储器件的装置和方法，其中单元阵列块具有由边缘子块，主子块，虚拟子块形成的存储块。当通过使能三个字线输出DQ数据时，可以使用直边块处理行缺陷，使得边缘子块或伪子块中的存储器件的修复处理具有与在主子块中出现缺陷的情况。

69. 发明授权

US5796668A Integrated circuit memory devices having reduced write cycle times and related methods 失效
标题翻译：集成电路存储器件具有缩短的写周期时间和相关方法
公开(公告)号：US5796668A
公开(公告)日：1998-08-18
申请号：US709622
申请日：1996-09-06
申请人： Dong-Il Seo , Hong-Sun Hwang
发明人： Dong-Il Seo , Hong-Sun Hwang
IPC分类号： G11C11/407 , G11C7/10 , G11C11/401 , G11C11/409 , G11C11/4096 , G11C8/00
CPC分类号： G11C7/1015 , G11C11/409 , G11C11/4096
摘要： An integrated circuit memory device includes a plurality of memory cells arranged in an array of rows and columns, a plurality of word lines wherein each of the word lines is associated with a predetermined row of the memory cells, and a plurality of common lines wherein each of the column lines is associated with a predetermined column of the memory cells. Each of a plurality of sense amplifiers is associated with a respective column line and each of the sense amplifiers detects a voltage difference between a pair of bit lines for the respective column and amplifies the voltage difference. A row decoder selects one of the word lines in response to a row address input during a write operation. An input/output driver receives data input during the write operation, and each of a plurality of input/output gates is connected between the input/output driver and a respective one of the column lines. A column decoder activates one of the input/output gates before the sense amplifier senses and amplifies the voltage difference. Related methods are also disclosed.
摘要翻译：一种集成电路存储器件，包括排列成行和列阵列的多个存储器单元，多条字线，其中每条字线与存储器单元的预定行相关联，以及多条公共线，其中每条的列线与存储器单元的预定列相关联。多个读出放大器中的每一个与相应的列线相关联，并且每个读出放大器检测用于各列的一对位线之间的电压差，并放大电压差。一行解码器在写入操作期间响应于输入的行地址来选择字线之一。输入/输出驱动器在写入操作期间接收数据输入，并且多个输入/输出门中的每一个连接在输入/输出驱动器和相应的列线之间。在读出放大器感测并放大电压差之前，列解码器激活输入/输出门之一。还公开了相关方法。

70. 发明授权

US5757714A Semiconductor memory device with on-chip boosted power supply voltage generator 失效
标题翻译：具有片上升压电源电压发生器的半导体存储器件
公开(公告)号：US5757714A
公开(公告)日：1998-05-26
申请号：US755477
申请日：1996-11-22
申请人： Jong-Hyun Choi , Hong-Sun Hwang
发明人： Jong-Hyun Choi , Hong-Sun Hwang
IPC分类号： G11C11/413 , G05F3/24 , G11C5/14 , G11C11/407 , H01L27/10 , G11C7/00
CPC分类号： G11C5/143
摘要： A semiconductor memory device uses three different power supply voltage levels including an internal IVcc, ground Vss and a boosted level Vpp more positive than the internal Vcc. A precharge control circuit in the memory device includes at least one NMOS transistor, at least one PMOS transistor and an output node having voltage values ranging from the IVcc either to Vss or to Vpp. The NMOS transistor acts as a loading transistor to the PMOS transistor and prevents latch-up in the PMOS transistor by maintaining IVcc below Vpp during the initial power set-up period of the memory device.
摘要翻译：半导体存储器件使用三个不同的电源电压电平，包括内部IVcc，接地Vss和升压电平Vpp比内部Vcc更正。存储器件中的预充电控制电路包括至少一个NMOS晶体管，至少一个PMOS晶体管和具有范围从IVcc到Vss或Vpp的电压值的输出节点。 NMOS晶体管充当PMOS晶体管的负载晶体管，并通过在存储器件的初始功率建立期间将IVcc保持在Vpp以下，来防止PMOS晶体管中的闩锁。

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