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1. 发明申请

US20120047319A1 SEMICONDUCTOR STORAGE DEVICE AND METHOD OF THROTTLING PERFORMANCE OF THE SAME 有权
标题翻译：半导体存储器件及其同步性能的方法
公开(公告)号：US20120047319A1
公开(公告)日：2012-02-23
申请号：US13166257
申请日：2011-06-22
申请人： Han Bin YOON , Yeong-Jae Woo , Dong Gi Lee , Young Kug Moon , Hyuck-Sun Kwon
发明人： Han Bin YOON , Yeong-Jae Woo , Dong Gi Lee , Young Kug Moon , Hyuck-Sun Kwon
IPC分类号： G06F12/00
CPC分类号： G06F3/0613 , G06F3/0653 , G06F3/0659 , G06F3/0679 , G06F2206/1014
摘要： A semiconductor storage device (SSD) and a method of throttling performance of the SSD. The method can include gathering at least two workload data items related with a workload of the semiconductor storage device, estimating the workload using the at least two workload data items, and throttling the performance of the semiconductor storage device according to the estimated workload. Accordingly, a workload that the semiconductor storage device will undergo can be estimated.
摘要翻译：一种半导体存储设备（SSD）和一种节制SSD性能的方法。该方法可以包括收集与半导体存储设备的工作负载相关的至少两个工作负载数据项，使用至少两个工作负载数据项估计工作量，以及根据所估计的工作量来调节半导体存储设备的性能。因此，可以估计半导体存储装置将经历的工作量。

2. 发明申请

US20120047317A1 SEMICONDUCTOR STORAGE DEVICE AND METHOD OF THROTTLING PERFORMANCE OF THE SAME 有权
标题翻译：半导体存储器件及其同步性能的方法
公开(公告)号：US20120047317A1
公开(公告)日：2012-02-23
申请号：US13166131
申请日：2011-06-22
申请人： Han Bin YOON , Yeong-Jae Woo , Dong Gi Lee , Young Kug Moon , Hyuck-Sun Kwon
发明人： Han Bin YOON , Yeong-Jae Woo , Dong Gi Lee , Young Kug Moon , Hyuck-Sun Kwon
IPC分类号： G06F12/00
CPC分类号： G06F3/0613 , G06F3/0653 , G06F3/0659 , G06F3/0679 , G06F2206/1014
摘要： A semiconductor storage device and a method of throttling performance of the same are provided. The semiconductor storage device includes a non-volatile memory device configured to store data in a non-volatile state; and a controller configured to control the non-volatile memory device. The controller calculates a new performance level, compares the calculated performance level with a predetermined reference, and determines the calculated performance level as an updated performance level according to the comparison result.
摘要翻译：提供半导体存储装置及其节流方法。半导体存储装置包括：非易失性存储装置，被配置为将数据存储在非易失性状态; 以及控制器，被配置为控制所述非易失性存储器件。控制器计算新的性能水平，将计算的性能水平与预定参考值进行比较，并根据比较结果将计算出的性能水平确定为更新的性能水平。

3. 发明授权

US07889546B2 Phase-change random access memory device, system having the same, and associated methods 有权
标题翻译：相变随机存取存储器件，具有相同的系统和相关方法
公开(公告)号：US07889546B2
公开(公告)日：2011-02-15
申请号：US12285656
申请日：2008-10-10
申请人： Joon-min Park , Young-kug Moon , Won-seok Lee
发明人： Joon-min Park , Young-kug Moon , Won-seok Lee
IPC分类号： G11C11/00
CPC分类号： G11C7/08 , G11C7/18 , G11C13/0004 , G11C2213/72
摘要： A phase-change random access memory (PRAM) device includes a PRAM cell array including a first sector and a second sector, a first global bit line coupled to a first local bit line of the first sector and a first local bit line of the second sector, and a first plurality of global bit line discharge units coupled to the first global bit line, the first plurality of global bit line discharge units configured to discharge the first global bit line in response to a first global discharge signal.
摘要翻译：相变随机存取存储器（PRAM）装置包括包括第一扇区和第二扇区的PRAM单元阵列，耦合到第一扇区的第一局部位线的第一全局位线和第二扇区的第一局部位线扇区和耦合到第一全局位线的第一多个全局位线放电单元，第一多个全局位线放电单元被配置为响应于第一全局放电信号而放电第一全局位线。

4. 发明申请

US20100125716A1 RESISTANCE VARIABLE MEMORY DEVICE 有权
标题翻译：电阻可变存储器件
公开(公告)号：US20100125716A1
公开(公告)日：2010-05-20
申请号：US12617758
申请日：2009-11-13
申请人： Kwang-jin Lee , Young-kug Moon , Kwang-ho Kim
发明人： Kwang-jin Lee , Young-kug Moon , Kwang-ho Kim
IPC分类号： G06F12/00
CPC分类号： G06F12/0215 , G06F12/0238 , G06F2212/7203 , G11C7/103 , G11C13/0004 , G11C13/004 , Y02D10/13
摘要： A resistance variable memory device includes a resistance variable memory cell array, a data register that prefetches read data of the resistance variable memory cell array, a data output unit that receives the prefetched read data from the data register and outputs the received data, and a page mode setting unit that sets one of a first page mode and a second page mode as a page mode. In the first page mode, the data output unit sequentially reads the read data prefetched in the data register as page addresses are sequentially received, and in the second page mode, the data output unit sequentially reads the read data prefetched in the data register after a start page address among a plurality of page addresses has been received
摘要翻译：电阻可变存储器件包括电阻可变存储单元阵列，预取电阻可变存储单元阵列的读取数据的数据寄存器，从数据寄存器接收预取的读取数据并输出接收的数据的数据输出单元，以及页面模式设置单元，其将第一页面模式和第二页面模式之一设置为页面模式。在第一页面模式中，数据输出单元顺序地读取在数据寄存器中预取的读取数据，因为顺序地接收页面地址，而在第二页面模式中，数据输出单元顺序地读取在数据寄存器中预读取的读取数据已经接收到多个页地址中的起始页地址

5. 发明申请

US20100118593A1 VARIABLE RESISTANCE MEMORY DEVICE AND SYSTEM THEREOF 有权
标题翻译：可变电阻存储器件及其系统
公开(公告)号：US20100118593A1
公开(公告)日：2010-05-13
申请号：US12619016
申请日：2009-11-16
申请人： Woo-Yeong Cho , Jong-Soo Seo , Young-Kug Moon , Jun-Soo Bae , Kwang-Jin Lee
发明人： Woo-Yeong Cho , Jong-Soo Seo , Young-Kug Moon , Jun-Soo Bae , Kwang-Jin Lee
IPC分类号： G11C11/00 , G11C7/04 , G11C7/02 , G11C8/00
CPC分类号： G11C13/0064 , G11C7/04 , G11C11/56 , G11C11/5678 , G11C13/0004 , G11C13/0023 , G11C13/0026 , G11C13/004 , G11C13/0069 , G11C2013/0054 , G11C2013/0076 , G11C2013/0078 , G11C2213/72 , H01L27/2409 , H01L29/868 , H01L45/06 , H01L45/1233 , H01L45/141 , H01L45/143 , H01L45/144 , H01L45/148
摘要： A phase-change random access memory device is provided. The phase-change random access memory device includes a global bit line connected to a write circuit and a read circuit, multiple local bit lines, each being connected to multiple phase-change memory cells, and multiple column select transistors selectively connecting the global bit line with each of the multiple local bit lines, each column select transistor having a resistance that varies depending on its distance from the write circuit and the read circuit.
摘要翻译：提供了相变随机存取存储器件。相变随机存取存储器件包括连接到写入电路和读取电路的全局位线，每个连接到多个相变存储器单元的多个局部位线，以及选择性地连接全局位线的多个列选择晶体管对于多个局部位线中的每一个，每个列选择晶体管具有根据其与写入电路和读取电路的距离而变化的电阻。

6. 发明申请

US20090097306A1 Phase-change random access memory device, system having the same, and associated methods 有权
标题翻译：相变随机存取存储器件，具有相同的系统和相关方法
公开(公告)号：US20090097306A1
公开(公告)日：2009-04-16
申请号：US12285656
申请日：2008-10-10
申请人： Joon-min Park , Young-kug Moon , Won-seok Lee
发明人： Joon-min Park , Young-kug Moon , Won-seok Lee
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C7/08 , G11C7/18 , G11C13/0004 , G11C2213/72
摘要： A phase-change random access memory (PRAM) device includes a PRAM cell array including a first sector and a second sector, a first global bit line coupled to a first local bit line of the first sector and a first local bit line of the second sector, and a first plurality of global bit line discharge units coupled to the first global bit line, the first plurality of global bit line discharge units configured to discharge the first global bit line in response to a first global discharge signal.
摘要翻译：相变随机存取存储器（PRAM）装置包括包括第一扇区和第二扇区的PRAM单元阵列，耦合到第一扇区的第一局部位线的第一全局位线和第二扇区的第一局部位线扇区和耦合到第一全局位线的第一多个全局位线放电单元，第一多个全局位线放电单元被配置为响应于第一全局放电信号而放电第一全局位线。

7. 发明申请

US20110305100A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20110305100A1
公开(公告)日：2011-12-15
申请号：US13152316
申请日：2011-06-03
申请人： Hak-soo YU , In-gyu BAEK , Hong-sun Hwang , Young-kug MOON
发明人： Hak-soo YU , In-gyu BAEK , Hong-sun Hwang , Young-kug MOON
IPC分类号： G11C5/14
CPC分类号： G11C5/063 , G11C5/025
摘要： A semiconductor memory device including a plurality of layers each including a memory cell array and which are stacked over each other; and at least one power plane for supplying power to the layers. The power plane includes a region to which a power voltage is applied and a region to which a ground voltage is applied. The region to which a power voltage is applied is located adjacent to the region to which a ground voltage is applied, and forms a decoupling capacitor therebetween to decouple an influx of power noise to the layers or generation of power noise in the layers
摘要翻译：一种半导体存储器件，包括多个层，每个层包括存储单元阵列并彼此堆叠; 以及用于向层供电的至少一个电力平面。电力平面包括施加电源电压的区域和施加接地电压的区域。施加电源电压的区域位于与施加接地电压的区域相邻的位置处，并且在其间形成去耦电容器以将功率噪声流入到层中或在层中产生功率噪声

8. 发明申请

US20090097307A1 Phase-change random access memory device, system having the same, and associated methods 审中-公开
标题翻译：相变随机存取存储器件，具有相同的系统和相关方法
公开(公告)号：US20090097307A1
公开(公告)日：2009-04-16
申请号：US12285657
申请日：2008-10-10
申请人： Joon-min Park , Young-kug Moon , Sang-ki Hwang
发明人： Joon-min Park , Young-kug Moon , Sang-ki Hwang
IPC分类号： G11C11/00 , G11C8/00 , G11C7/06
CPC分类号： G11C7/18 , G11C7/08 , G11C13/0004 , G11C2213/72
摘要： A phase-change random access memory (PRAM) device includes a PRAM cell array having a first bank that includes first to mth sectors, where m is a positive integer of at least 2, and sense amplifiers disposed between an xth sector and an (x+1)th sector of the bank, where x is a positive integer less than m.
摘要翻译：相变随机存取存储器（PRAM）器件包括具有包括第一至第m个扇区的第一存储体的PRAM单元阵列，其中m是至少为2的正整数，以及设置在第x个扇区和（x +1）行，其中x是小于m的正整数。

9. 发明授权

US07453722B2 Phase change memory device and memory cell array thereof 有权
标题翻译：相变存储器件及其存储单元阵列
公开(公告)号：US07453722B2
公开(公告)日：2008-11-18
申请号：US11319364
申请日：2005-12-29
申请人： Byung-Gil Choi , Jong-Soo Seo , Young-Kug Moon , Bo-Tak Lim , Su-Yeon Kim
发明人： Byung-Gil Choi , Jong-Soo Seo , Young-Kug Moon , Bo-Tak Lim , Su-Yeon Kim
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C13/0004 , G11C2013/0078 , G11C2213/72 , G11C2213/79
摘要： A phase change memory device is provided which includes a memory cell array including a plurality of memory cells, and a write driver for supplying a program current to the memory cell array through a global bitline. The memory cell array includes first and second cell regions, a first local bitline connected to the first cell region, a second local bitline connected to the second cell region, and a select region disposed between the first and second cell regions and supplying the program current supplied through the global bitline to the first and second local bitlines in response to a local select signal.
摘要翻译：提供了一种相变存储器件，其包括包括多个存储器单元的存储单元阵列，以及用于通过全局位线将编程电流提供给存储单元阵列的写入驱动器。存储单元阵列包括第一和第二单元区域，连接到第一单元区域的第一本地位线，连接到第二单元区域的第二本地位线，以及设置在第一单元区域和第二单元区域之间并提供程序电流的选择区域通过全局位线提供响应于本地选择信号的第一和第二本地位线。

10. 发明申请

US20070133268A1 Phase change memory device and memory cell array thereof 有权
标题翻译：相变存储器件及其存储单元阵列
公开(公告)号：US20070133268A1
公开(公告)日：2007-06-14
申请号：US11319364
申请日：2005-12-29
申请人： Byung-Gil Choi , Jong-Soo Seo , Young-Kug Moon , Bo-Tak Lim , Su-Yeon Kim
发明人： Byung-Gil Choi , Jong-Soo Seo , Young-Kug Moon , Bo-Tak Lim , Su-Yeon Kim
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C13/0004 , G11C2013/0078 , G11C2213/72 , G11C2213/79
摘要： A phase change memory device is provided which includes a memory cell array including a plurality of memory cells, and a write driver for supplying a program current to the memory cell array through a global bitline. The memory cell array includes first and second cell regions, a first local bitline connected to the first cell region, a second local bitline connected to the second cell region, and a select region disposed between the first and second cell regions and supplying the program current supplied through the global bitline to the first and second local bitlines in response to a local select signal.
摘要翻译：提供了一种相变存储器件，其包括包括多个存储器单元的存储单元阵列，以及用于通过全局位线将编程电流提供给存储单元阵列的写入驱动器。存储单元阵列包括第一和第二单元区域，连接到第一单元区域的第一本地位线，连接到第二单元区域的第二本地位线，以及设置在第一单元区域和第二单元区域之间并提供程序电流的选择区域通过全局位线提供响应于本地选择信号的第一和第二本地位线。

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