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61. 发明申请

US20140122843A1 CONDITIONAL STORE INSTRUCTIONS IN AN OUT-OF-ORDER EXECUTION MICROPROCESSOR 有权
标题翻译：不合格执行微处理器的条件存储指令
公开(公告)号：US20140122843A1
公开(公告)日：2014-05-01
申请号：US14007097
申请日：2012-04-06
申请人： G. Glenn Henry , Terry Parks , Rodney E. Hooker , Gerard M. Col , Colin Eddy
发明人： G. Glenn Henry , Terry Parks , Rodney E. Hooker , Gerard M. Col , Colin Eddy
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/3017 , G06F9/30076 , G06F9/30123 , G06F9/30174 , G06F9/30189 , G06F9/30196
摘要： An instruction translator translates a conditional store instruction (specifying data register, base register, and offset register of the register file) into at least two microinstructions. An out-of-order execution pipeline executes the microinstructions. To execute a first microinstruction, an execution unit receives a base value and an offset from the register file and generates a first result as a function of the base value and offset. The first result specifies the memory location address. To execute a second microinstruction, an execution unit receives the first result and writes the first result to an allocated entry in the store queue if the condition flags satisfy the condition (the store queue subsequently writes the data to the memory location specified by the address), and otherwise kills the allocated store queue entry so that the store queue does not write the data to the memory location specified by the address.
摘要翻译：指令翻译器将条件存储指令（指定寄存器文件的指定数据寄存器，基址寄存器和偏移寄存器）转换为至少两个微指令。无序执行管线执行微指令。为了执行第一微指令，执行单元从寄存器文件接收基值和偏移量，并且产生作为基值和偏移量的函数的第一结果。第一个结果指定内存位置地址。为了执行第二微指令，如果条件标志满足条件（存储队列随后将数据写入由地址指定的存储器位置），则执行单元接收第一结果并将第一结果写入存储队列中的已分配条目，，否则将杀死所分配的存储队列条目，使得存储队列不将数据写入由地址指定的存储器位置。

62. 发明授权

US08683225B2 Microprocessor that facilitates task switching between encrypted and unencrypted programs 有权
标题翻译：微处理器，有助于加密和未加密程序之间的任务切换
公开(公告)号：US08683225B2
公开(公告)日：2014-03-25
申请号：US13091698
申请日：2011-04-21
申请人： G. Glenn Henry , Terry Parks , Brent Bean , Thomas A. Crispin
发明人： G. Glenn Henry , Terry Parks , Brent Bean , Thomas A. Crispin
IPC分类号： G06F21/00
CPC分类号： H04L9/0827 , G06F9/30003 , G06F9/30079 , G06F9/30178 , G06F9/30189 , G06F12/0875 , G06F21/52 , G06F21/54 , G06F21/602 , G06F21/71 , G06F21/72 , G06F2212/402 , G06F2212/452 , G06F2221/2107 , H04L9/0618 , H04L9/0861 , H04L9/0891 , H04L9/0894 , H04L2209/12 , H04L2209/20
摘要： A microprocessor includes an architected register having a bit (may be x86 EFLAGS register reserved bit) set by the microprocessor. A fetch unit fetches encrypted instructions from an instruction cache and decrypts them (via XOR) prior to executing them, in response to the microprocessor setting the bit. The microprocessor saves the bit value to a stack in memory and then clears the bit in response to receiving an interrupt. The fetch unit fetches unencrypted instructions from the instruction cache and executes them without decrypting them after the microprocessor clears the bit. The microprocessor restores the saved value from the stack in memory to the bit in the architected register (and in one embodiment, also restores decryption key values) in response to executing a return from interrupt instruction. The fetch unit resumes fetching and decrypting the encrypted instructions in response to determining that the restored value of the bit is set.
摘要翻译：微处理器包括由微处理器设置的位（可以是x86 EFLAGS寄存器保留位）的架构化寄存器。读取单元从指令高速缓存中获取加密指令，并在执行它们之前对其进行解密（通过XOR），以响应微处理器设置该位。微处理器将位值保存到存储器中的堆栈，然后响应于接收到中断而清除该位。提取单元从指令高速缓存中提取未加密的指令，并在微处理器清零位之后执行它们而不对其进行解密。响应于执行中断指令的返回，微处理器将存储器中的保存值从存储器中的位恢复到构造寄存器中的位（并且在一个实施例中，还恢复解密密钥值）。响应于确定该位的恢复值被设置，获取单元恢复取出和解密加密指令。

63. 发明授权

US08635437B2 Pipelined microprocessor with fast conditional branch instructions based on static exception state 有权
标题翻译：流水线微处理器，具有基于静态异常状态的快速条件分支指令
公开(公告)号：US08635437B2
公开(公告)日：2014-01-21
申请号：US12481427
申请日：2009-06-09
申请人： G. Glenn Henry , Terry Parks , Brent Bean
发明人： G. Glenn Henry , Terry Parks , Brent Bean
IPC分类号： G06F15/00 , G06F7/38 , G06F9/44 , G06F9/00
CPC分类号： G06F9/30058 , G06F9/3867
摘要： A microprocessor includes a memory that stores an exception handler to handle an exception condition. The exception handler is a non-user program private to the microprocessor and includes a conditional branch instruction. A first fetch unit fetches instructions of a user program that includes a user program instruction that causes the exception condition. An execution unit executes the user program instructions fetched by the first fetch unit and executes instructions of the exception handler. The execution unit also saves a state in response to detecting the exception condition caused by the user program instruction. A second fetch unit fetches the exception handler instructions from the memory and resolves the conditional branch instruction based on the saved state without sending the conditional branch instruction to the execution unit to resolve the conditional branch instruction.
摘要翻译：微处理器包括存储异常处理程序来处理异常情况的存储器。异常处理程序是微处理器专用的非用户程序，并且包括条件转移指令。第一提取单元获取包括导致异常条件的用户程序指令的用户程序的指令。执行单元执行由第一取出单元取出的用户程序指令，并执行异常处理程序的指令。执行单元还响应于检测到由用户程序指令引起的异常状况而保存状态。第二提取单元从存储器中取出异常处理程序指令，并且基于保存的状态解析条件转移指令，而不向执行单元发送条件转移指令来解析条件转移指令。

64. 发明授权

US08631256B2 Distributed management of a shared power source to a multi-core microprocessor 有权
标题翻译：将共享电源分布式管理到多核微处理器
公开(公告)号：US08631256B2
公开(公告)日：2014-01-14
申请号：US13299225
申请日：2011-11-17
申请人： G. Glenn Henry , Darius D. Gaskins
发明人： G. Glenn Henry , Darius D. Gaskins
IPC分类号： G06F1/26
CPC分类号： G06F1/06 , G06F1/3296 , Y02D10/172
摘要： Microprocessors are provided with decentralized logic and associated methods for indicating power related operating states, such as desired voltages and frequency ratios, to shared microprocessor power resources such as a voltage regulator module (VRM) and phase locked loops (PLLs). Each core is configured to generate a value to indicate a desired operating state of the core. Each core is also configured to receive a corresponding value from each other core sharing the applicable resource, and to calculate a composite value compatible with the minimal needs of each core sharing the applicable resource. Each core is further configured to conditionally drive the composite value off core to the applicable resource based on whether the core is designated as a master core for purposes of controlling or coordinating the applicable resource. The composite value is supplied to the applicable shared resource without using any active logic outside the plurality of cores.
摘要翻译：微处理器具有分散逻辑和相关联的方法，用于将功率相关的操作状态（例如期望的电压和频率比）指示给诸如电压调节器模块（VRM）和锁相环（PLL）的共享微处理器功率资源。每个核心被配置为产生一个值以指示所述核心的期望操作状态。每个核心还被配置为从彼此分配可用资源的核心接收相应的值，并且计算与共享可应用资源的每个核心的最小需求兼容的复合值。每个核心还被配置为基于是否将核心指定为主核以有条件地将核心的复合值驱动到适用的资源，以便控制或协调适用的资源。复合值被提供给可应用的共享资源，而不使用多个核之外的任何活动逻辑。

65. 发明授权

US08607034B2 Apparatus and method for disabling a microprocessor that provides for a secure execution mode 有权
标题翻译：用于禁用提供安全执行模式的微处理器的装置和方法
公开(公告)号：US08607034B2
公开(公告)日：2013-12-10
申请号：US12263244
申请日：2008-10-31
申请人： G. Glenn Henry , Terry Parks
发明人： G. Glenn Henry , Terry Parks
IPC分类号： G06F9/00
CPC分类号： G06F21/72 , G06F12/1408 , G06F21/12 , G06F21/14 , G06F21/554 , G06F21/70 , G06F21/71 , G06F21/73 , G06F21/74 , G06F21/75 , G06F21/82
摘要： An apparatus including a microprocessor, a system memory, and a secure non-volatile memory. The microprocessor executes non-secure application programs and a secure application program. The secure application program is executed in a secure execution mode. The microprocessor has secure watchdog logic that monitors environmental attributes corresponding to the microprocessor and to the secure application program, and that transfers program control to one of a plurality of event handlers within the secure application program. The system memory has non-secure application programs stored therein. The secure non-volatile memory is coupled to the microprocessor via a private bus. The secure non-volatile memory is configured to store the secure application program, where the secure application program is encrypted when stored in the secure non-volatile memory, and where transactions over the private bus between the microprocessor and the secure non-volatile memory are isolated from the system bus and corresponding system bus resources within the microprocessor.
摘要翻译：一种包括微处理器，系统存储器和安全非易失性存储器的装置。微处理器执行非安全应用程序和安全应用程序。安全应用程序以安全执行模式执行。微处理器具有安全的看门狗逻辑，其监视对应于微处理器和安全应用程序的环境属性，并且将程序控制传送到安全应用程序内的多个事件处理程序之一。系统存储器中存储有非安全应用程序。安全的非易失性存储器经由专用总线耦合到微处理器。安全非易失性存储器被配置为存储安全应用程序，其中安全应用程序在存储在安全非易失性存储器中时被加密，以及在微处理器和安全非易失性存储器之间的专用总线上的事务是从系统总线和微处理器内的相应系统总线资源隔离。

66. 发明授权

US08495343B2 Apparatus and method for detection and correction of denormal speculative floating point operand 有权
标题翻译：用于非正常投机浮点运算的检测和校正的装置和方法
公开(公告)号：US08495343B2
公开(公告)日：2013-07-23
申请号：US12793821
申请日：2010-06-04
申请人： G. Glenn Henry , Gerard M. Col , Timothy A. Elliott , Rodney E. Hooker , Terry Parks
发明人： G. Glenn Henry , Gerard M. Col , Timothy A. Elliott , Rodney E. Hooker , Terry Parks
IPC分类号： G06F9/00
CPC分类号： G06F9/3865 , G06F9/3001 , G06F9/30025
摘要： A microprocessor includes a plurality of execution units configured to receive instructions and operands thereof and to execute the instructions. An instruction scheduler issues the instructions to the execution units and selects sources of the instruction operands. At least one of the execution units detects one of the operands of one of the instructions is a denormal operand, generates an indication that the instruction needs to be replayed in response to detecting the denormal operand, and provides the denormal operand to the instruction scheduler in response to detecting the denormal operand, rather than normalizing the denormal operand. The instruction scheduler normalizes the denormal operand, in response to the indication, and causes the normalized operand, rather than the denormal operand, to be provided to the execution unit when the instruction is replayed.
摘要翻译：微处理器包括被配置为接收其指令和操作数并执行指令的多个执行单元。指令调度器向执行单元发出指令并选择指令操作数的源。执行单元中的至少一个检测其中一个指令的操作数之一是反正态操作数，响应于检测到该反正态操作数而产生指示需要重播的指示，并将该反正态操作数提供给指令调度器对正反操作数进行检测的响应，而不是对正常操作数进行归一化。指令调度器响应于该指示来对归一化操作数进行归一化，并且当指令被重放时，使归一化操作数而不是反正态操作数提供给执行单元。

67. 发明授权

US08423751B2 Microprocessor with fast execution of call and return instructions 有权
标题翻译：具有快速执行调用和返回指令的微处理器
公开(公告)号：US08423751B2
公开(公告)日：2013-04-16
申请号：US12481199
申请日：2009-06-09
申请人： G. Glenn Henry , Terry Parks , Brent Bean
发明人： G. Glenn Henry , Terry Parks , Brent Bean
IPC分类号： G06F15/00 , G06F7/38 , G06F9/00 , G06F9/44
CPC分类号： G06F9/30054 , G06F9/3806 , G06F9/3844
摘要： A microprocessor includes an instruction set architecture, comprising a call instruction type, a return instruction type, and other instruction types. Execution units correctly execute program instructions of the other instruction types. A call/return stack has a plurality of entries arranged in a last-in-first-out manner. The call/return stack is architectural state of the microprocessor not modifiable by program instructions of the other instruction types. The call/return stack is architectural state of the microprocessor indirectly modifiable by program instructions of the call and return instruction types. The microprocessor also includes a fetch unit that fetches program instructions and sends the program instructions of the other instruction types to the execution units to be correctly executed. The fetch unit correctly executes program instructions of the call and return instruction types without sending the program instructions of the call and return instruction types to the execution units to be correctly executed.
摘要翻译：微处理器包括指令集架构，其包括调用指令类型，返回指令类型和其他指令类型。执行单元正确执行其他指令类型的程序指令。呼叫/返回栈具有以先进先出方式排列的多个条目。调用/返回栈是微处理器的架构状态，不能通过其他指令类型的程序指令进行修改。调用/返回栈是通过调用和返回指令类型的程序指令间接修改的微处理器的架构状态。微处理器还包括提取单元，其取得程序指令，并将其他指令类型的程序指令发送到执行单元以进行正确执行。提取单元正确地执行调用和返回指令类型的程序指令，而不将调用的程序指令和返回指令类型发送到要正确执行的执行单元。

68. 发明申请

US20130067202A1 CONDITIONAL NON-BRANCH INSTRUCTION PREDICTION 有权
标题翻译：条件非分支指导预测
公开(公告)号：US20130067202A1
公开(公告)日：2013-03-14
申请号：US13413258
申请日：2012-03-06
申请人： G. Glenn Henry , Terry Parks , Rodney E. Hooker
发明人： G. Glenn Henry , Terry Parks , Rodney E. Hooker
IPC分类号： G06F9/30
CPC分类号： G06F9/30174 , G06F9/30076 , G06F9/30112 , G06F9/3017 , G06F9/30189 , G06F9/30196
摘要： A microprocessor processes conditional non-branch instructions that specify a condition and instruct the microprocessor to perform an operation if the condition is satisfied and otherwise to not perform the operation. A predictor provides a prediction about a conditional non-branch instruction. An instruction translator translates the conditional non-branch instruction into a no-operation microinstruction when the prediction predicts the condition will not be satisfied, and into a set of one or more microinstructions to unconditionally perform the operation when the prediction predicts the condition will be satisfied. An execution pipeline executes the no-operation microinstruction or the set of microinstructions. The predictor translates into a second set of one or more microinstructions to conditionally perform the operation when the prediction does not make a prediction. In the case of a misprediction, the translator re-translates the conditional non-branch instruction into the second set of microinstructions.
摘要翻译：微处理器处理指定条件的条件非分支指令，并指示微处理器在条件满足的情况下执行操作，否则不执行操作。预测器提供关于条件非分支指令的预测。当预测预测条件不满足时，指令翻译器将条件非分支指令转换为无操作微指令，并且当预测预测条件将被满足时，指令转换为一组或多个微指令以无条件地执行操作。执行流水线执行无操作微指令或微指令集。当预测不进行预测时，预测器转换成第二组一个或多个微指令以有条件地执行操作。在错误预测的情况下，翻译者将条件非分支指令重新翻译成第二组微指令。

69. 发明授权

US08392693B2 Fast REP STOS using grabline operations 有权
标题翻译：快速REP STOS使用抓取操作
公开(公告)号：US08392693B2
公开(公告)日：2013-03-05
申请号：US12781210
申请日：2010-05-17
申请人： G. Glenn Henry , Colin Eddy , Rodney E. Hooker
发明人： G. Glenn Henry , Colin Eddy , Rodney E. Hooker
IPC分类号： G06F7/38 , G06F9/00 , G06F9/44 , G06F15/00
CPC分类号： G06F9/30043 , G06F9/30047 , G06F9/383 , G06F9/3834 , G06F9/3859 , G06F9/3865
摘要： A microprocessor includes a cache memory and a grabline instruction. The grabline instruction specifies a memory address that implicates a cache line of the memory. The grabline instruction instructs the microprocessor to initiate a zero-beat read-invalidate transaction on the bus to obtain ownership of the cache line. The microprocessor foregoes initiating the transaction on the bus when executing the grabline instruction if the microprocessor determines that a store to the cache line would cause an exception.
摘要翻译：微处理器包括高速缓冲存储器和获取指令。该grabline指令指定一个内存地址，暗示内存的高速缓存行。获取指令指示微处理器在总线上启动零跳读取无效事务以获得高速缓存行的所有权。如果微处理器确定到高速缓存行的存储将导致异常，则微处理器在执行抓取指令时放弃在总线上启动事务。

70. 发明授权

US08370641B2 Initialization of a microprocessor providing for execution of secure code 有权
标题翻译：提供执行安全代码的微处理器的初始化
公开(公告)号：US08370641B2
公开(公告)日：2013-02-05
申请号：US12263214
申请日：2008-10-31
申请人： G. Glenn Henry , Terry Parks
发明人： G. Glenn Henry , Terry Parks
IPC分类号： G06F11/30
CPC分类号： G06F21/72 , G06F12/1408 , G06F21/12 , G06F21/14 , G06F21/554 , G06F21/70 , G06F21/71 , G06F21/73 , G06F21/74 , G06F21/75 , G06F21/82
摘要： An apparatus including a microprocessor and a secure non-volatile memory. The microprocessor executes non-secure application programs and a secure application program. The microprocessor has secure execution mode initialization logic and an authorized public key. The secure execution mode initialization logic provides for initialization of a secure execution mode within the microprocessor. The secure execution mode initialization logic employs an asymmetric key algorithm to decrypt an enable parameter directing entry into the secure execution mode. The authorized public key is used to decrypt the enable parameter, the enable parameter having been encrypted according to the asymmetric key algorithm using an authorized private key that corresponds to the authorized public key. The secure non-volatile memory stores the secure application program, where transactions over the private bus between the microprocessor and the secure non-volatile memory are isolated from the system bus and corresponding system bus resources within the microprocessor.
摘要翻译：一种包括微处理器和安全非易失性存储器的装置。微处理器执行非安全应用程序和安全应用程序。微处理器具有安全执行模式初始化逻辑和授权公钥。安全执行模式初始化逻辑提供微处理器内的安全执行模式的初始化。安全执行模式初始化逻辑采用非对称密钥算法来解密引导进入安全执行模式的启用参数。授权公钥用于对使能参数进行解密，该使能参数已经使用与授权公钥相对应的授权私钥根据非对称密钥算法被加密。安全非易失性存储器存储安全应用程序，其中微处理器和安全非易失性存储器之间的专用总线上的事务与系统总线和微处理器内的对应系统总线资源隔离。

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