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61. 发明授权

US06455938B1 Integrated circuit interconnect shunt layer 有权
标题翻译：集成电路互连分流层
公开(公告)号：US06455938B1
公开(公告)日：2002-09-24
申请号：US09905479
申请日：2001-07-13
申请人： Pin-Chin Connie Wang , Amit P. Marathe , Christy Mei-Chu Woo
发明人： Pin-Chin Connie Wang , Amit P. Marathe , Christy Mei-Chu Woo
IPC分类号： H01L2945
CPC分类号： H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit and manufacturing method therefor is provided for an integrated circuit on a semiconductor substrate grated circuit having a semiconductor device. A dielectric layer is on the semiconductor substrate and has an opening provided therein. A barrier layer lines the opening, and a first conductor core fills the opening over the barrier layer. A second dielectric layer is formed on the first dielectric layer and has a second channel and via opening provided therein. A shunt layer is in the via opening above the conductor core. A barrier layer lines the second channel and via opening over the shunt layer and the second dielectric layer. A conductor core fills the second channel and via opening over the barrier layer and the first conductor core to form the second channel and via.
摘要翻译：提供了一种用于具有半导体器件的半导体衬底格栅电路上的集成电路的集成电路及其制造方法。电介质层位于半导体衬底上，其中设有开口。阻挡层对开口进行排列，并且第一导体芯填充阻挡层上的开口。第二电介质层形成在第一电介质层上并具有设置在其中的第二通道和通孔。并联层位于导体芯上方的通孔中。阻挡层将第二通道和通过开口穿过并联层和第二介电层。导体芯填充第二通道并通过阻挡层和第一导体芯上的开口形成第二通道和通孔。

62. 发明授权

US06417566B1 Void eliminating seed layer and conductor core integrated circuit interconnects 有权
标题翻译：消除种子层和导体芯集成电路互连
公开(公告)号：US06417566B1
公开(公告)日：2002-07-09
申请号：US09705121
申请日：2000-11-01
申请人： Pin-Chin Connie Wang , Amit P. Marathe
发明人： Pin-Chin Connie Wang , Amit P. Marathe
IPC分类号： H01L2348
CPC分类号： H01L21/76873 , H01L21/76843 , H01L23/5226 , H01L23/53223 , H01L23/53238 , H01L23/53252 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer is formed on the semiconductor substrate and a channel dielectric layer on the device dielectric layer has an opening formed therein. A barrier layer lines the channel opening and a conductor core fills the opening over the barrier layer. A seed layer is disposed between the barrier layer and the conductor core. The seed layer has an associated element which is formed during annealing into an intermetallic compound which has a density lower than the density of the conductor core.
摘要翻译：提供了具有半导体器件的半导体衬底的集成电路及其制造方法。在半导体衬底上形成器件电介质层，器件电介质层上的沟道电介质层上形成有开口。阻挡层对通道开口进行排列，并且导体芯填充阻挡层上的开口。种子层设置在阻挡层和导体芯之间。种子层具有在退火成形成密度低于导体芯的密度的金属间化合物的相关元件。

63. 发明授权

US06403474B1 Controlled anneal conductors for integrated circuit interconnects 有权
标题翻译：用于集成电路互连的受控退火导体
公开(公告)号：US06403474B1
公开(公告)日：2002-06-11
申请号：US09745917
申请日：2000-12-20
申请人： Steven C. Avanzino , Pin-Chin Connie Wang , Minh Van Ngo
发明人： Steven C. Avanzino , Pin-Chin Connie Wang , Minh Van Ngo
IPC分类号： H01L2144
CPC分类号： H01L21/76877 , H01L21/2885 , H01L21/76883
摘要： A method is provided for manufacturing an integrated circuit on a semiconductor wafer having a semiconductor substrate with a semiconductor device thereon. A dielectric layer is formed on the semiconductor substrate and an opening is formed in the dielectric layer. A barrier layer is deposited to line the opening. A seed layer is deposited on the barrier layer and securely bonds to the barrier layer. A conductor layer is deposited to fill the channel opening over the barrier layer. A planarization technique is used to planarize the barrier, seed layer, and conductor layers to be coplanar with the dielectric layer to form a conductor channel. The semiconductor wafer is then subjected to a two step timed anneal.
摘要翻译：提供了一种用于在其上具有半导体器件的半导体衬底的半导体晶片上制造集成电路的方法。在半导体衬底上形成电介质层，并在电介质层中形成开口。沉积阻挡层以使开口线对齐。种子层沉积在阻挡层上并牢固地结合到阻挡层上。沉积导体层以填充阻挡层上的通道开口。平面化技术用于平坦化屏障，晶种层和与电介质层共面的导体层，以形成导体沟道。然后对半导体晶片进行两步定时退火。

64. 外观设计

USD767747S1 Handheld fan 有权
标题翻译：手持风扇
公开(公告)号：USD767747S1
公开(公告)日：2016-09-27
申请号：US29521317
申请日：2015-03-23
申请人： Connie Wang
设计人： Connie Wang

65. 发明授权

US09299643B2 Ruthenium interconnect with high aspect ratio and method of fabrication thereof 有权
标题翻译：具有高纵横比的钌互连及其制造方法
公开(公告)号：US09299643B2
公开(公告)日：2016-03-29
申请号：US12286149
申请日：2008-09-29
申请人： Zheng Wang , Connie Wang , Erik Wilson , Wen Yu , Robert Chiu
发明人： Zheng Wang , Connie Wang , Erik Wilson , Wen Yu , Robert Chiu
IPC分类号： H01L29/40 , H01L23/485 , H01L21/768 , H01L23/532 , H01L27/105 , H01L27/115
CPC分类号： H01L23/485 , H01L21/76877 , H01L23/53252 , H01L27/105 , H01L27/1052 , H01L27/115 , H01L27/11517 , H01L2924/0002 , H01L2924/00
摘要： An electrically conductive interconnect is provided through an opening in a dielectric layer, electrically connecting two conductive layers. In one embodiment, the interconnect is formed by ruthenium entirely filling the opening in the dielectric layer. In another embodiment, an adhesion layer of titanium is provided in the opening prior to providing the ruthenium. In using this approach, an aspect ratio (i.e., the ratio of the length of the interconnect to the width thereof) of 20:1 or greater is achievable.
摘要翻译：导电互连通过介电层中的开口设置，电连接两个导电层。在一个实施例中，互连由完全填充介电层中的开口的钌形成。在另一个实施方案中，在提供钌之前，在开口中提供钛的粘附层。在使用这种方法时，可实现20:1或更大的纵横比（互连长度与其宽度之比）。

66. 发明授权

US09240418B2 Wordline resistance reduction method and structure in an integrated circuit memory device 有权
标题翻译：集成电路存储器件中的字线电阻降低方法和结构
公开(公告)号：US09240418B2
公开(公告)日：2016-01-19
申请号：US12961379
申请日：2010-12-06
申请人： Shenqing Fang , Jihwan Choi , Connie Wang , Eunha Kim
发明人： Shenqing Fang , Jihwan Choi , Connie Wang , Eunha Kim
IPC分类号： H01L21/00 , H01L27/115 , G11C5/06 , H01L27/105 , H01L29/66 , H01L21/8234
CPC分类号： H01L27/11573 , G11C5/063 , H01L21/823468 , H01L27/1052 , H01L27/11526 , H01L27/11531 , H01L29/665 , H01L29/66507
摘要： Methods and structures for reducing resistance in wordlines of an integrated circuit memory device are disclosed. In one embodiment, the method includes forming multiple columns of polycrystalline silicon for respective number of wordlines, forming core transistor junctions and periphery transistor junctions associated with the wordlines, performing a salicidation process for the periphery transistor junction and performing a salicidation process for the columns of polycrystalline silicon to from the wordlines with low resistance.
摘要翻译：公开了用于降低集成电路存储器件的字线中的电阻的方法和结构。在一个实施例中，该方法包括在相应数量的字线上形成多列多晶硅，形成与字线相关联的核心晶体管结和外围晶体管结，对外围晶体管结执行盐化处理，并对多晶硅从字线低电阻。

67. 外观设计

USD709402S1 Spiky heart shaped ring 有权
标题翻译：尖刺心形戒指
公开(公告)号：USD709402S1
公开(公告)日：2014-07-22
申请号：US29481223
申请日：2014-02-03
申请人： Connie Wang
设计人： Connie Wang

68. 外观设计

USD666342S1 Luminous stick 有权
标题翻译：发光棒
公开(公告)号：USD666342S1
公开(公告)日：2012-08-28
申请号：US29404244
申请日：2011-10-18
申请人： Connie Wang , Wei Hung Yu
设计人： Connie Wang , Wei Hung Yu

69. 外观设计

USD662994S1 Luminous bubble stick 有权
标题翻译：发光泡沫棒
公开(公告)号：USD662994S1
公开(公告)日：2012-07-03
申请号：US29404213
申请日：2011-10-18
申请人： Connie Wang , Wei Hung Yu
设计人： Connie Wang , Wei Hung Yu

70. 发明授权

US07845815B2 Straw cup with variable lights 有权
标题翻译：秸秆杯与可变灯
公开(公告)号：US07845815B2
公开(公告)日：2010-12-07
申请号：US12379558
申请日：2009-02-25
申请人： Wei Hung Yu , Connie Wang
发明人： Wei Hung Yu , Connie Wang
IPC分类号： F21V33/00 , F21S8/00 , F47G21/18 , A61J15/00 , A47G19/22
CPC分类号： A47G19/2227 , A47G2019/2238
摘要： The present invention relates to a straw cup with variable lights, primarily comprising of a set of light-emitting diodes surrounding the inside of the cup's straw, a circuit controller board, and power switch; when the power is activated, the liquid inside the straw's cup refracts and directs light, increasing the variation and brilliance of the twinkling lights and thus further increasing the variation of the straw cup's multicolored lights.
摘要翻译：本发明涉及具有可变光源的吸管杯，主要包括围绕杯子吸管内部的一组发光二极管，电路控制器板和电源开关; 当电源被激活时，吸管杯内的液体折射和引导光线，增加了闪烁灯的变化和亮度，从而进一步增加了吸管杯的五彩灯光的变化。

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