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61. 发明授权

US07005701B2 Method for fabricating a vertical NROM cell 有权
标题翻译：制造垂直NROM电池的方法
公开(公告)号：US07005701B2
公开(公告)日：2006-02-28
申请号：US10318551
申请日：2002-12-13
申请人： Ching-Nan Hsiao , Chi-Hui Lin , Chung-Lin Huang , Ying-Cheng Chuang
发明人： Ching-Nan Hsiao , Chi-Hui Lin , Chung-Lin Huang , Ying-Cheng Chuang
IPC分类号： H01L29/76 , H01L39/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L27/11568 , H01L27/115
摘要： A method for fabricating a vertical nitride read-only memory (NROM) cell. A substrate having at least one trench is provided. A spacer is formed over the sidewall of the trench. Subsequently, ion implantation is performed on the substrate using the spacer as a mask to form doping areas as bit lines in the substrate near its surface and the bottom of the trench. Bit line oxides are formed over each of the doping areas. After the spacer is removed, a conformable insulating layer as gate dielectric is deposited on the sidewall of the trench and the surface of the bit line oxide. Finally, a conductive layer as a word line is deposited over the insulating layer and fills in the trench.
摘要翻译：一种用于制造垂直氮化物只读存储器（NROM）单元的方法。提供具有至少一个沟槽的衬底。间隔件形成在沟槽的侧壁上。随后，使用间隔物作为掩模在衬底上进行离子注入，以在沟槽的表面和底部附近的衬底中形成作为位线的掺杂区域。在每个掺杂区域上形成位线氧化物。在移除间隔物之后，在沟槽的侧壁和位线氧化物的表面上沉积作为栅极电介质的适形绝缘层。最后，作为字线的导电层沉积在绝缘层上并填充在沟槽中。

62. 发明授权

US06916715B2 Method for fabricating a vertical NROM cell 有权
标题翻译：制造垂直NROM电池的方法
公开(公告)号：US06916715B2
公开(公告)日：2005-07-12
申请号：US10694155
申请日：2003-10-27
申请人： Ching-Nan Hsiao , Chi-Hui Lin , Chung-Lin Huang , Ying-Cheng Chuang
发明人： Ching-Nan Hsiao , Chi-Hui Lin , Chung-Lin Huang , Ying-Cheng Chuang
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/8246 , H01L27/115 , H01L27/148
CPC分类号： H01L27/11568 , H01L27/115
摘要： A method for fabricating a vertical nitride read-only memory (NROM) cell. A substrate having at least one trench is provided. A spacer is formed over the sidewall of the trench. Subsequently, ion implantation is performed on the substrate using the spacer as a mask to form doping areas as bit lines in the substrate near its surface and the bottom of the trench. Bit line oxides are formed over each of the doping areas. After the spacer is removed, a conformable insulating layer as gate dielectric is deposited on the sidewall of the trench and the surface of the bit line oxide. Finally, a conductive layer as a word line is deposited over the insulating layer and fills in the trench.
摘要翻译：一种用于制造垂直氮化物只读存储器（NROM）单元的方法。提供具有至少一个沟槽的衬底。间隔件形成在沟槽的侧壁上。随后，使用间隔物作为掩模在衬底上进行离子注入，以在沟槽的表面和底部附近的衬底中形成作为位线的掺杂区域。在每个掺杂区域上形成位线氧化物。在移除间隔物之后，在沟槽的侧壁和位线氧化物的表面上沉积作为栅极电介质的适形绝缘层。最后，作为字线的导电层沉积在绝缘层上并填充在沟槽中。

63. 发明授权

US06893919B2 Floating gate and fabricating method of the same 有权
公开(公告)号：US06893919B2
公开(公告)日：2005-05-17
申请号：US10810740
申请日：2004-03-26
申请人： Ying-Cheng Chuang , Chung-Lin Huang
发明人： Ying-Cheng Chuang , Chung-Lin Huang
IPC分类号： H01L21/8247 , H01L27/115 , H01L21/336
CPC分类号： H01L21/28273 , H01L27/115 , H01L27/11521
摘要： A floating gate and a fabricating method of the same. A semiconductor substrate is provided. A gate dielectric layer and a conducting layer are sequentially formed on the semiconductor substrate. A patterned hard mask layer having an opening is formed on the conducting layer, wherein a portion of the conducting layer is exposed through the opening. A spacer is formed on the sidewall of the opening. The patterned hard mask layer is removed. A conducting spacer is formed on the sidewall of the spacer. The exposed conducting layer and the exposed gate dielectric layer are sequentially removed.

64. 发明授权

US06847068B2 Floating gate and fabrication method therefor 有权
公开(公告)号：US06847068B2
公开(公告)日：2005-01-25
申请号：US10441801
申请日：2003-05-19
申请人： Ying-Cheng Chuang , Chung-Lin Huang , Chi-Hui Lin
发明人： Ying-Cheng Chuang , Chung-Lin Huang , Chi-Hui Lin
IPC分类号： H01L21/28 , H01L29/423 , H01L21/8242
CPC分类号： H01L29/42324 , H01L21/28273
摘要： A floating gate with multiple tips and a fabrication method thereof. A semiconductor substrate is provided, on which a patterned hard mask layer is formed, wherein the patterned hard mask layer has an opening. A gate dielectric layer and a first conducting layer with a first predetermined thickness are formed on the bottom of the opening. A spacer is formed on the sidewall of the opening. A conducting spacer is formed on the sidewall of the spacer. The first conducting layer is etched to a second predetermined thickness. A multi-tip floating gate is provided by the first conducting layer and the conducting spacer. A protecting layer is formed in the opening. The patterned hard mask layer, the gate dielectric layer, a portion of the protecting layer, and a portion of the first spacer are etched to expose the surface of the first conducting layer.

65. 发明授权

US06815290B2 Stacked gate flash memory device and method of fabricating the same 有权
标题翻译：堆叠式闪存器件及其制造方法
公开(公告)号：US06815290B2
公开(公告)日：2004-11-09
申请号：US10457867
申请日：2003-06-10
申请人： Chi-Hui Lin , Chung-Lin Huang
发明人： Chi-Hui Lin , Chung-Lin Huang
IPC分类号： H01L21336
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/42336 , H01L29/66825 , H01L29/7883
摘要： A stacked gate flash memory device and method of fabricating the same. A cell of the stacked gate flash memory device in accordance with the invention is disposed in a cell trench within a substrate and source and drain regions are formed in the same substrate side of the adjacent isolation trenches. Thus, the stacked gate flash memory device of the invention can achieve high integration of memory cells.

66. 发明授权

US06649473B1 Method of fabricating a floating gate for split gate flash memory 有权
标题翻译：制造分闸门闪存的浮栅的方法
公开(公告)号：US06649473B1
公开(公告)日：2003-11-18
申请号：US10330777
申请日：2002-12-27
申请人： Chi-Hui Lin , Chung-Lin Huang
发明人： Chi-Hui Lin , Chung-Lin Huang
IPC分类号： H01L21336
CPC分类号： H01L21/28273
摘要： A method of fabricating a floating gate for a flash memory. An active region is formed on a semiconductor substrate. A first insulating layer, a first conductive layer and a masking layer are sequentially formed in the active region. A part of the masking layer is removed to form a first opening. A second conductive layer is formed to cover the masking layer and the bottom surface and sidewall of the first opening. A second insulating layer is formed on the second conductive layer to fill the first opening. An oxidation process is performed until the second conductive layer in contact with the second insulating layer over the masking layer is oxidized into a third insulating layer. The second and third insulating layers are removed to form a second opening. A fourth insulating layer fills in the second opening. The masking layer and the first conductive layer underlying the masking layer uncovered by the fourth insulating layer are removed.
摘要翻译：一种制造闪存的浮动栅极的方法。在半导体衬底上形成有源区。在有源区域中依次形成第一绝缘层，第一导电层和掩模层。去除掩模层的一部分以形成第一开口。形成第二导电层以覆盖掩模层和第一开口的底表面和侧壁。在第二导电层上形成第二绝缘层以填充第一开口。进行氧化处理，直到与掩模层上的第二绝缘层接触的第二导电层被氧化成第三绝缘层。去除第二和第三绝缘层以形成第二开口。第四绝缘层填充在第二开口中。除去掩蔽层和被第四绝缘层未覆盖的掩蔽层下面的第一导电层。

67. 发明授权

US06486032B1 Method for fabricating control gate and floating gate of a flash memory cell 有权
标题翻译：用于制造闪存单元的控制栅极和浮动栅极的方法
公开(公告)号：US06486032B1
公开(公告)日：2002-11-26
申请号：US10174672
申请日：2002-06-18
申请人： Chih-Hui Lin , Chung-Lin Huang
发明人： Chih-Hui Lin , Chung-Lin Huang
IPC分类号： H01L218247
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115 , H01L29/42324 , H01L29/66825
摘要： A method for fabricating the control gate and floating gate of a flash memory cell. An active area is firstly formed on a semiconductor substrate, followed by the formation of a first insulating layer, a first conductive layer and a first masking layer. A first opening is then formed by partially removing the first masking layer, and a floating gate oxide layer is formed by oxidation. The remaining first masking layer is removed, followed by forming a sacrificial layer, which is then partially removed to define a second opening. The remaining sacrificial layer is used as a hard mask to partially remove the first conductive layer and the first insulating layer to form a third opening. A second insulating layer is formed to fill the third opening to form an insulating plug. Part of the first conductive layer and the first insulating layer are removed to form a floating gate, followed by forming a third insulating layer and a second conductive layer. The insulating plug is then used as stop layer to remove part of the second conductive layer and third insulating layer to form a control gate.
摘要翻译：一种用于制造闪存单元的控制栅极和浮置栅极的方法。首先在半导体衬底上形成有源区，然后形成第一绝缘层，第一导电层和第一掩模层。然后通过部分去除第一掩模层形成第一开口，并且通过氧化形成浮栅氧化层。除去剩余的第一掩蔽层，随后形成牺牲层，然后部分地去除牺牲层以限定第二开口。剩余的牺牲层用作硬掩模以部分地去除第一导电层和第一绝缘层以形成第三开口。形成第二绝缘层以填充第三开口以形成绝缘插头。去除第一导电层和第一绝缘层的一部分以形成浮置栅极，随后形成第三绝缘层和第二导电层。然后将绝缘插头用作停止层以去除部分第二导电层和第三绝缘层以形成控制栅极。

68. 发明授权

US06475894B1 Process for fabricating a floating gate of a flash memory in a self-aligned manner 有权
标题翻译：以自对准的方式制造闪存的浮动栅极的工艺
公开(公告)号：US06475894B1
公开(公告)日：2002-11-05
申请号：US10052622
申请日：2002-01-18
申请人： Chung-Lin Huang , Sheng-Tsung Chen , Chi-Hui Lin
发明人： Chung-Lin Huang , Sheng-Tsung Chen , Chi-Hui Lin
IPC分类号： H01L218247
CPC分类号： H01L27/11517 , H01L21/28273 , H01L27/115
摘要： The present invention provides a process for fabricating a floating gate of a flash memory. First, an isolation region is formed in a semiconductor substrate and the isolation region has a height higher than the substrate. A gate oxide layer and a first polysilicon layer are then formed. The first polysilicon layer is formed according to the contour of the isolation region to form a recess in the first polysilicon layer. A sacrificial insulator is filled into the recess. The first polysilicon layer is then selectively removed in a self-aligned manner using the sacrificial insulator as a hard mask to expose the isolation region. A polysilicon spacer is formed on the sidewalls of the first polysilicon layer. A first mask layer is formed on the isolation region, the sacrificial insulator in the recess is removed, and a floating gate region is defined. Then, the surfaces of the first polysilicon layer and polysilicon spacer in the floating gate region are oxidized to form a polysilicon oxide layer. Finally, the polysilicon oxide layer is used as a mask to pattern the underlying first polysilicon layer and polysilicon spacer in a self-aligned manner to form a floating gate. During the oxidation process, the polysilicon spacer of the present invention serves as a buffer layer, which is oxidized and protects the floating gate from being oxidized. Thus, the floating gate and STI overlay, and current leakage caused by insufficient overlay is prevented.
摘要翻译：本发明提供一种制造闪速存储器的浮动栅极的方法。首先，在半导体衬底中形成隔离区，并且隔离区的高度高于衬底。然后形成栅极氧化物层和第一多晶硅层。第一多晶硅层根据隔离区域的轮廓形成，以在第一多晶硅层中形成凹陷。牺牲绝缘体填充到凹部中。然后使用牺牲绝缘体作为硬掩模以自对准方式选择性地去除第一多晶硅层以暴露隔离区域。在第一多晶硅层的侧壁上形成多晶硅间隔物。在隔离区域上形成第一掩模层，去除凹槽中的牺牲绝缘体，并且限定浮栅区域。然后，浮置栅极区域中的第一多晶硅层和多晶硅间隔物的表面被氧化以形成多晶硅氧化物层。最后，使用多晶硅氧化物层作为掩模，以自对准的方式对下面的第一多晶硅层和多晶硅间隔物进行图案化以形成浮栅。在氧化过程中，本发明的多晶硅间隔物用作缓冲层，其被氧化并保护浮栅不被氧化。因此，防止浮动栅极和STI覆盖，以及由覆盖不足引起的电流泄漏。

69. 发明授权

US08604620B2 Semiconductor structure having lateral through silicon via 有权
标题翻译：具有横向硅通孔的半导体结构
公开(公告)号：US08604620B2
公开(公告)日：2013-12-10
申请号：US13342201
申请日：2012-01-03
申请人： Tzung-Han Lee , Chung-Lin Huang , Ron Fu Chu , Dah-Wei Liu
发明人： Tzung-Han Lee , Chung-Lin Huang , Ron Fu Chu , Dah-Wei Liu
IPC分类号： H01L29/40
CPC分类号： H01L21/76898 , H01L24/03 , H01L24/05 , H01L24/08 , H01L24/94 , H01L25/0657 , H01L2224/02371 , H01L2224/05548 , H01L2224/05624 , H01L2224/05639 , H01L2224/05647 , H01L2224/05666 , H01L2224/0568 , H01L2224/05681 , H01L2224/08145 , H01L2224/08148 , H01L2224/94 , H01L2225/06551 , H01L2225/06565 , H01L2224/03
摘要： The present invention provides a semiconductor structure having a lateral TSV and a manufacturing method thereof. The semiconductor structure includes a chip having an active side, a back side disposed opposite to the active side, and a lateral side disposed between the active side and the back side. The chip further includes a contact pad, a lateral TSV and a patterned conductive layer. The contact pad is disposed on the active side. The lateral TSV is disposed on the lateral side. The patterned conductive layer is disposed on the active side and is electrically connected to the lateral TSV and the contact pad.
摘要翻译：本发明提供一种具有横向TSV的半导体结构及其制造方法。半导体结构包括具有有源侧的芯片，与有源侧相对设置的背面以及设置在主动侧和后侧之间的侧面。芯片还包括接触焊盘，横向TSV和图案化导电层。接触垫设置在活动侧。横向TSV设置在侧面。图案化导电层设置在有源侧上并且电连接到侧向TSV和接触焊盘。

70. 发明申请

US20130168812A1 MEMORY CAPACITOR HAVING A ROBUST MOAT AND MANUFACTURING METHOD THEREOF 审中-公开
标题翻译：具有稳定运动的记忆体电容器及其制造方法
公开(公告)号：US20130168812A1
公开(公告)日：2013-07-04
申请号：US13426848
申请日：2012-03-22
申请人： TZUNG-HAN LEE , CHUNG-LIN HUANG , RON-FU CHU
发明人： TZUNG-HAN LEE , CHUNG-LIN HUANG , RON-FU CHU
IPC分类号： H01L29/92 , H01L21/02
CPC分类号： H01L28/91 , H01L27/10852
摘要： A manufacturing method for memory capacitor having a robust moat, comprising the steps of: providing a substrate; forming a patterned sacrificial layer on the substrate having a moat to separate a cell area and a peripheral area; forming a supporting layer on the sacrificial layer and filling the moat to form a annular member, wherein the supporting layer and the sacrificial layer arranged in alignment to form a stack structure; forming a plurality row of capacitor trenches on the substrate, wherein the capacitor trenches are formed at intervals in the stack structure; and forming a conducting layer on the supporting layer and covering the substrate and the inner surface of the stack structure defining the capacitor trenches.
摘要翻译：一种具有坚固的护城河的存储电容器的制造方法，包括以下步骤：提供衬底; 在具有护城河的基板上形成图案化的牺牲层以分离单元区域和周边区域; 在所述牺牲层上形成支撑层并填充所述护城河以形成环形构件，其中所述支撑层和所述牺牲层排列成对准以形成堆叠结构; 在所述基板上形成多排电容器沟槽，其中所述电容器沟槽在所述堆叠结构中间隔地形成; 以及在所述支撑层上形成导电层，并覆盖所述基板和限定所述电容器沟槽的所述堆叠结构的内表面。

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