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51. 发明授权

US4814644A Basic circuitry particularly for construction of multivalued logic systems 失效
标题翻译：特别用于构建多值逻辑系统的基本电路
公开(公告)号：US4814644A
公开(公告)日：1989-03-21
申请号：US821289
申请日：1986-01-22
申请人： Takeshi Yamakawa
发明人： Takeshi Yamakawa
IPC分类号： G05F3/26 , G06F7/49 , G06F7/544 , H03K17/30 , H03K17/687 , H03K17/693 , H03K19/08 , H03K19/094 , H03K19/21 , H03M5/20 , H03K5/22 , H03K3/01 , H03K5/153
CPC分类号： G06F7/49 , G05F3/262 , G06F7/544 , H03K17/302 , H03K17/687 , H03K17/693 , H03K19/0813 , H03K19/09425 , H03K19/215 , H03M5/20
摘要： Disclosed are basic circuits operable in a current mode in multivalued logic circuit systems, analog circuit systems and the like. Examples of the basic circuits are a successor, quantizer, adder, substracter, divider, multiplier, decoder, literal circuit, equivalence circuit, bilateral T-gate, complement literal circuit and h operator circuit. These basic circuits are realized by using floating threshold switching circuits, floating window switching circuits, threshold SPDT switching circuits, and the like.
摘要翻译：公开了在多值逻辑电路系统，模拟电路系统等中以当前模式操作的基本电路。基本电路的例子是后继，量化器，加法器，减法器，分频器，乘法器，解码器，文字电路，等效电路，双向T门，补码文字电路和h运算器电路。这些基本电路通过使用浮动阈值切换电路，浮动窗口切换电路，阈值SPDT切换电路等来实现。

52. 发明授权

US4724529A Method and apparatus for numerical division 失效
标题翻译：数值分割的方法和装置
公开(公告)号：US4724529A
公开(公告)日：1988-02-09
申请号：US701556
申请日：1985-02-14
申请人： Suren Irukulla , Bimal V. Patel
发明人： Suren Irukulla , Bimal V. Patel
IPC分类号： G06F7/537 , G06F7/483 , G06F7/49 , G06F7/493 , G06F7/52 , G06F7/533 , G06F7/535
CPC分类号： G06F7/535 , G06F7/49 , G06F7/4917 , G06F7/5375
摘要： A method and apparatus for radix-.beta. non-restoring division. The division process occurs in four phases. In a first phase, the input operands are transformed to produce a divisor lying in a designated numerical range. Next, a transitional phase involves generating an initial radix-.beta. quotient digit from the transformed numerator. An iterative phase of the process generates successive partial remainders according to a recursive method. From the sign and a single radix-.beta. digit of each of these partial remainders, the process generates a radix-.beta. quotient digit. Further, a fourth phase, which may run concurrently with the transitional and iterative phases, involves accumulating successively generated quotient digits to produce a final quotient value.
摘要翻译：基数β恢复分裂的方法和装置。分割过程分四个阶段进行。在第一阶段中，输入操作数被变换以产生位于指定数值范围内的除数。接下来，过渡阶段涉及从转换的分子生成初始的基数β商数。该过程的迭代阶段根据递归方法产生连续的部分余数。从符号和每个这些部分余数的单个基数β数字，该过程生成基数β商数。此外，可以与过渡和迭代阶段同时运行的第四阶段涉及累积连续生成的商数以产生最终商值。

53. 发明授权

US4159529A Fibonacci code adder 失效
标题翻译：斐波那契码加法器
公开(公告)号：US4159529A
公开(公告)日：1979-06-26
申请号：US861412
申请日：1977-12-16
申请人： Alexei P. Stakhov
发明人： Alexei P. Stakhov
IPC分类号： G06F7/49 , G06F7/60 , G06F7/72 , G06F7/50 , G06F5/00
CPC分类号： G06F7/60
摘要： A Fibonacci code adder comprising an n-digit half-adder which includes at least two inputs through which addends of numbers represented in the Fibonacci code minimal form are introduced and also includes intermediate sum and carry outputs coupled to analogous inputs of a rewriting device having their intermediate sum and carry outputs coupled to analogous inputs of a Fibonacci code converter whose outputs produce the codeword of the final sum.
摘要翻译：斐波那契编码加法器，其包括n位半加法器，其包括至少两个输入，通过该至少两个输入，以斐波纳契码最小形式表示的数字的加数被引入，并且还包括耦合到重写装置的类似输入的中间和和进位输出，中间和和进位输出耦合到斐波那契编码转换器的类似输入，其输出产生最终和的码字。

54. 发明授权

US4149261A Computer having circuitry for rounding-off insignificant digits 失效
标题翻译：计算机具有用于舍入无效数字的电路
公开(公告)号：US4149261A
公开(公告)日：1979-04-10
申请号：US777828
申请日：1977-03-15
申请人： Isao Harigaya , Akihiro Yamataka
发明人： Isao Harigaya , Akihiro Yamataka
IPC分类号： G06F7/48 , G06F7/49 , G06F7/491 , G06F15/02
CPC分类号： G06F7/491 , G06F15/02 , G06F15/025 , G06F7/49 , G06Q40/12
摘要： A computer capable of rounding a number, such as by raising, truncating or chopping the digits of the number which are lower than a specified digit position above a decimal point.
摘要翻译：能够对数字进行舍入的计算机，例如通过提高，截断或切割小于小数点上方的指定数字位置的数字的数字。

55. 发明授权

US3806719A Calculator for selectively calculating in decimal and time systems 失效
公开(公告)号：US3806719A
公开(公告)日：1974-04-23
申请号：US22813972
申请日：1972-02-22
申请人： SUWA SEIKOSHA KK
发明人： YAMAMURA K , GOTO M
IPC分类号： G06F7/49 , G06F7/491 , G06F7/52 , G06Q30/00 , G07C1/00 , G06F7/50
CPC分类号： G06F7/4915 , G06F7/49 , G06F7/4917 , G06Q30/04 , G07C1/00
摘要： A calculating apparatus which comprises circuits for selectively calculating in decimal and hexadic systems, the calculating apparatus further including a switching device to select one of the systems and circuits to supply a carry or borrow correction suitable to the selected system. According to one embodiment of the invention, the last said circuits function to add or subtract a decimal 4 when a correction is to be made for a decimal calculation for a hexadic problem. According to another embodiment, the first said circuits include sequential stages, a shift register coupling said stage, a gate to supply a binary 0110 signal, and a carry/borrow detector coupled to the register and the first of said stages and controlling said gate. According to still another embodiment, the aforesaid circuits collectively comprise a decimal calculator, circuit to supply operands to said calculator to produce a result, a device to examine said result to establish a carry/borrow requirement, flip flops coupled to and actuated by the last said device, gates controlled by the flip flops and by respective timing signals, a further gate controlled in part by the first said gates, a time calculation control switch effecting a complementary control on said further gate, and a correction gate for supplying a binary 0100 signal to said calculator and controlled by said further gate. According to still another embodiment the aforesaid circuits collectively comprise first and second calculator stages, a shift register coupling the stages, first and second correction detectors coupled to said first stage and register to detect decimal and hexedic carry/borrow correction requirements respectively, first and second gates respectively coupled to said first and second detectors and respectively adapted for passing a 0110 decimal correction binary signal and a 1010 hexadic correction binary signal to said second stage, a switch for commanding a time calculation, and an inverter between said gates for selectively and exclusively opening one of said gates to pass a correction signal, the inverter means being controlled by said switch.

56. 发明授权

US3394249A Apparatus for adding numbers using a decrementer and an incrementer 失效
标题翻译：使用减量器和增量器增加数字的装置
公开(公告)号：US3394249A
公开(公告)日：1968-07-23
申请号：US49121965
申请日：1965-09-29
申请人： IBM
发明人： ABERNATHY ROGER E , GENG HELLMUTH R , ONWILER WALTER N , ROBERT TARANTO
IPC分类号： G06F7/49
CPC分类号： G06F7/49

57. 发明授权

US3328567A Digital adding and subtracting device 失效
标题翻译：数字加减装置
公开(公告)号：US3328567A
公开(公告)日：1967-06-27
申请号：US44762265
申请日：1965-04-13
申请人： HITACHI LTD
发明人： AKIRA KAMOI , MASAKAZU EJIRI
IPC分类号： G06F7/02 , G06F7/42 , G06F7/49
CPC分类号： G06F7/49 , G06F7/02 , G06F7/42

58. 发明公开

US20240012615A1 FAST MODULAR MULTIPLICATION OF LARGE INTEGERS 审中-公开
公开(公告)号：US20240012615A1
公开(公告)日：2024-01-11
申请号：US17811079
申请日：2022-07-07
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Silvia Melitta Mueller , Ulrich Mayer , Dominik Steenken , Yvo Thomas Bernard Mulder , Manoj Kumar
IPC分类号： G06F7/492 , G06F7/49 , G06F7/72 , G06F7/501
CPC分类号： G06F7/4925 , G06F7/49 , G06F7/725 , G06F7/501
摘要： In an approach, a processor receives a plurality of first operand values, where the first operand values are integer values. A processor adds, using binary addition, the plurality of first operand values resulting in a sum value S. A processor determines a single combined modular correction term D for a binary sum of all operand values based on leading bits of the sum value S. A processor performs a modular addition of S and D resulting in a modular sum of said plurality of said first operand values.

59. 发明公开

US20230401034A1 Methods, Systems, and Circuits for Coordinated Optimization in In-Memory Sorting 审中-公开
公开(公告)号：US20230401034A1
公开(公告)日：2023-12-14
申请号：US18330666
申请日：2023-06-07
申请人： University of Virginia Patent Foundation
发明人： Marzieh Lenjani , Alif Ahmed , Kevin Skadron
IPC分类号： G06F7/26 , G06F7/49
CPC分类号： G06F7/26 , G06F7/49
摘要： Disclosed herein are systems, methods, and computer-readable media for sorting datasets within a Processing in Memory (PIM)-based system. A request to sort a dataset stored in a 3D-stacked memory can be received. The request can identify a specific dataset and sorting criteria, which includes a plurality of keys. The dataset can be partitioned into several subarrays across various memory banks within the 3D-stacked memory. Each piece of data within these subarrays can be separated into buckets based on the keys. Local histograms for each subarray and bank histograms based on the local histograms can be generated. A prefix-sum operation on the bank histograms can determine individual positions for the sorted dataset. Aggregation of the subarrays from all memory banks can form the sorted dataset, which can be subsequently returned.

60. 发明申请

US20220171601A1 ELECTRONIC ARCHITECTURE AND SEMICONDUCTOR DEVICES BASED ON A BASE 60 NUMERAL SYSTEM 有权
公开(公告)号：US20220171601A1
公开(公告)日：2022-06-02
申请号：US17109889
申请日：2020-12-02
申请人： Danny Rittman , Mo Jacob
发明人： Danny Rittman , Mo Jacob
IPC分类号： G06F7/49
摘要： Sexagesimal-native electronic architecture and methods are provided including a sexagesimal-native semiconductor unit natively performing operations and flows using a numeral system having sixty as its base. The semiconductor unit may be an integrated circuit, an arithmetic logic unit, a central processing unit, a microcontroller, or a microchip. The sexagesimal-native semiconductor unit is configured to communicate with semiconductor units that perform operations and flows using decimal and/or binary number systems. A sexagesimal numeral method provides a sexagesimal-native arithmetic operation unit performing mathematical operations using a numeral system having sixty as its base wherein all numbers are natively processed and represented as sexagesimal numbers. A sexagesimal-native integrated circuit performs operations using a Base 60 numeral system and is configured to communicate with integrated circuits that perform operations using decimal and/or binary number systems also is provided. In exemplary sexagesimal-native electronic architecture, the chip can work with other similar chips in parallel processing mode.

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