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1. 发明授权

US3809872A Time calculator with mixed radix serial adder/subtraction 失效
标题翻译：时间计算器与混合RADIX串行增加/分配
公开(公告)号：US3809872A
公开(公告)日：1974-05-07
申请号：US22692172
申请日：1972-02-16
申请人： SUWA SEIKOSHA KK
发明人： YAMAMURA K , GOTO M
IPC分类号： G06F7/49 , G06F7/491 , G06F7/52 , G06F7/50
CPC分类号： G06F7/4915 , G06F7/49 , G06F7/4917
摘要： A time calculating device characterized in that hours and minutes and perhaps seconds are directly set, times are added or subtracted, and the result of this calculation is obtained in hours, minutes and seconds. The times may also be multiplied or divided by an arbitrary figure, the result being obtained in hours, minutes and seconds or in other units. The time calculating apparatus comprises first and second calculators, the first calculator being adapted to receive and add or subtract two time figures and produce a result. The second calculator is adapted to receive and combine this result with a further figure. A means is provided coupling the first calculator to the second calculator for the transfer of the result to the latter. This means is responsive to the result and to a hexadic-decimal control signal for generating a decimal or hexadic correction signal which is transmitted to the second calculator as the aforesaid further figure for combination with the result. The time figures can be expressed as series of pulses and the aforesaid means includes a shift register to convert the result to parallel signals, there being provided a plurality of gates coupled to the shift register to detect when hexadic and decimal corrections are necessary and to generate an indicating signal for indicating the same.
摘要翻译：一种时间计算装置，其特征在于，直接设定小时和分钟，也可以设定秒数，添加或减少时间，计算结果以小时，分，秒为单位。时间也可以乘以或除以任意数字，结果以小时，分钟和秒或其他单位获得。时间计算装置包括第一和第二计算器，第一计算器适于接收和加或减两个时间图并产生结果。第二计算器适于接收并结合该结果与另一个图。提供了将第一计算器耦合到第二计算器以将结果传送给第二计算器的装置。这意味着响应于结果和十六进制十进制控制信号，用于产生十进制或六进制校正信号，该十进制或六进制校正信号作为上述另外的图形与结果一起传送到第二计算器。时间图可以表示为一系列脉冲，并且上述装置包括用于将结果转换为并行信号的移位寄存器，提供耦合到移位寄存器的多个门，以检测何时需要十六进制和十进制校正，并产生用于指示相同的指示信号。

2. 发明授权

US3806719A Calculator for selectively calculating in decimal and time systems 失效
公开(公告)号：US3806719A
公开(公告)日：1974-04-23
申请号：US22813972
申请日：1972-02-22
申请人： SUWA SEIKOSHA KK
发明人： YAMAMURA K , GOTO M
IPC分类号： G06F7/49 , G06F7/491 , G06F7/52 , G06Q30/00 , G07C1/00 , G06F7/50
CPC分类号： G06F7/4915 , G06F7/49 , G06F7/4917 , G06Q30/04 , G07C1/00
摘要： A calculating apparatus which comprises circuits for selectively calculating in decimal and hexadic systems, the calculating apparatus further including a switching device to select one of the systems and circuits to supply a carry or borrow correction suitable to the selected system. According to one embodiment of the invention, the last said circuits function to add or subtract a decimal 4 when a correction is to be made for a decimal calculation for a hexadic problem. According to another embodiment, the first said circuits include sequential stages, a shift register coupling said stage, a gate to supply a binary 0110 signal, and a carry/borrow detector coupled to the register and the first of said stages and controlling said gate. According to still another embodiment, the aforesaid circuits collectively comprise a decimal calculator, circuit to supply operands to said calculator to produce a result, a device to examine said result to establish a carry/borrow requirement, flip flops coupled to and actuated by the last said device, gates controlled by the flip flops and by respective timing signals, a further gate controlled in part by the first said gates, a time calculation control switch effecting a complementary control on said further gate, and a correction gate for supplying a binary 0100 signal to said calculator and controlled by said further gate. According to still another embodiment the aforesaid circuits collectively comprise first and second calculator stages, a shift register coupling the stages, first and second correction detectors coupled to said first stage and register to detect decimal and hexedic carry/borrow correction requirements respectively, first and second gates respectively coupled to said first and second detectors and respectively adapted for passing a 0110 decimal correction binary signal and a 1010 hexadic correction binary signal to said second stage, a switch for commanding a time calculation, and an inverter between said gates for selectively and exclusively opening one of said gates to pass a correction signal, the inverter means being controlled by said switch.

3. 发明授权

US3750062A Thin-type switchboard 失效
标题翻译：薄型开关板
公开(公告)号：US3750062A
公开(公告)日：1973-07-31
申请号：US3750062D
申请日：1971-08-16
申请人： SUWA SEIKOSHA KK
发明人： GOTO M
IPC分类号： G02F1/13 , G02F1/1335 , G04C3/00 , G06C7/02 , G06C11/02 , G06F3/02 , G09G3/18 , H01H36/00 , H01H41/08
CPC分类号： H01H36/0066 , G04C3/004 , G06C7/02 , G06C11/02 , G06F3/02 , G06F3/0202 , G09G3/18
摘要： A thin-type switchboard having a plurality of reed switches each of which is adapted to be operated when subjected to a magnetic field, said reed switches being disposed substantially in a single plane beneath an operating surface. A separate manually positionable permanent magnet operates selected ones of said reed switches when positioned in registration therewith adjacent said operating surface.
摘要翻译：一种具有多个舌簧开关的薄型配电板，每个簧片开关适于在经受磁场时被操作，所述簧片开关基本上设置在操作表面下方的单个平面中。当与其相邻的所述操作表面定位时，单独的可手动定位的永磁体操作所述舌簧开关中的选定的一个。

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