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    • 51. 发明授权
    • Device for transmitting or storing digital television pictures, and
device for receiving said pictures
    • 用于发送或存储数字电视图像的装置,以及用于接收所述图像的装置
    • US5570132A
    • 1996-10-29
    • US254092
    • 1994-06-06
    • Peter H. N. De WithWilhelmus J. Van Gestel
    • Peter H. N. De WithWilhelmus J. Van Gestel
    • H03M7/40H04N5/783H04N5/92H04N7/54H04N9/804H04N19/89H04N7/52
    • H04N7/54H04N19/89H04N9/8047H04N5/783
    • Device for transmitting or storing digital television pictures in which a maximum possible number of data of a group of transformed pixel blocks (DB.sub.1 . . . DB.sub.12) is transmitted in the form of variable-length code words (V.sub.1 . . . V.sub.N) in a corresponding channel block of predetermined length (FIG. 5A). If all code words of the groups of blocks are accommodated in the corresponding channel block (FIG. 5C), the channel block will also comprise surplus data of other blocks. The boundary, within a channel block, between these code words and surplus data is transmitted in the form of an address (P) which is accommodated at a predetermined position of the channel block. If the channel block length is inadequate for transmitting all code words of the group of blocks, the channel block (FIG. 5B), will comprise at least the code words which are representative of the DC coefficient and a number of important AC coefficients of each block. Said code words are accommodated in successive channel block sections (L.sub.1 . . . L.sub.12), with a code (C) for the length of these channel block sections being transmitted at predetermined positions of the channel block.
    • 用于发送或存储数字电视图像的装置,其中以可变长度码字(V1 ... VN)的形式发送一组经转换的像素块(DB1 ... DB12)的最大可能数量的数据, 相应的预定长度的通道块(图5A)。 如果块组中的所有码字被容纳在对应的信道块(图5C)中,则信道块还将包括其他块的剩余数据。 信道块内的这些码字与剩余数据之间的边界以容纳在信道块的预定位置的地址(P)的形式发送。 如果信道块长度不足以发送块组的所有码字,则信道块(图5B)将至少包括表示DC系数的码字和每个的重要AC系数的数量 块。 所述码字被容纳在连续的信道块部分(L1 ... L12)中,其中这些信道块部分的长度的码(C)在信道块的预定位置发送。
    • 52. 发明授权
    • Variable-length decoder for bit-stuffed data
    • 用于位填充数据的可变长度解码器
    • US5566192A
    • 1996-10-15
    • US454738
    • 1995-05-31
    • Heon-hee Moon
    • Heon-hee Moon
    • H03M7/40G06T9/00H03M7/42H04J3/06H04L7/08H04N7/24H04N7/54H04N7/62G06F11/00
    • H04N21/434H03M7/425H04N19/152H04N7/54H04N19/50H04N21/23611
    • A variable-length decoder variable-length-decodes a received variable-length-encoded data. The variable-length-encoded data is bit-stuffed in each data block to create data portions with a predetermined number of bits. Frame start codes representing a start of each frame and mass of macroblock start codes distinguishing between a plurality of masses of macroblocks are inserted into the data. Synchronization of data between frames and masses of macroblocks are accomplished via: a first-in-first-out (FIFO) memory which stores encoded data; a decoder which variable-length-decodes the input data in response to a control signal and generates an end-of-block (EOB) error signal when an EOB is not found; a decoding interface which interfaces between the decoder and a timing controller; and a timing controller which synchronizes decoding by use of start and initialization signals.
    • 可变长度解码器可变长度解码接收到的可变长度编码数据。 可变长度编码的数据在每个数据块中被填充以创建具有预定位数的数据部分。 表示每帧开始的帧起始码和区分多个宏块块的宏块开始码的质量被插入到数据中。 通过以下方式来实现帧与宏块质量之间的数据同步:存储编码数据的先进先出(FIFO)存储器; 解码器,其响应于控制信号对输入数据进行可变长度解码,并且当未找到EOB时产生块结束(EOB)错误信号; 解码接口,其在解码器和定时控制器之间进行接口; 以及通过使用起始和初始化信号来同步解码的定时控制器。
    • 56. 发明授权
    • Method of and apparatus for compressing image representing signals
    • 用于压缩表示信号的图像的方法和装置
    • US5542008A
    • 1996-07-30
    • US187459
    • 1994-01-28
    • Takayuki SugaharaIchiro Ando
    • Takayuki SugaharaIchiro Ando
    • H04N1/41H04N7/173H04N7/26H04N7/30H04N7/32H04N7/50H04N7/54G06K9/36G06K9/46
    • H04N7/17345H04N19/117H04N19/124H04N19/126H04N19/137H04N19/14H04N19/149H04N19/172H04N19/423H04N19/50H04N19/60H04N19/61H04N19/80H04N19/82H04N19/86H04N19/90H04N7/17336H04N7/54H04N19/146H04N19/152
    • An image representing input signal is processed so the data therein are filtered in a predetermined manner to derive a filtered signal. The values of the filtered signal are combined at successive time intervals, and the values are combined so there is an addition of a function of values of the filtered signal at the successive time intervals to derive a combined signal. The combined signal is converted into a signal representing a predicted number of bits in a frame of the image. In response to the signal representing a predicted number of bits in a frame of the image, a signal representing the magnitude of a control for quantization step size is derived which is as a function of an error between the predicted number of bits and a predetermined target value therefor. A function of the input signal data is orthogonally transformed so a transformed signal is derived. Output data represented by the transformed signal are quantized so they have quantized step size determined by the control signal representing the magnitude of a quantization step size and there is a reduction in the number of data bits for the image relative to the number of data bits in the input signal.
    • 处理表示输入信号的图像,使其中的数据以预定的方式被滤波以得到滤波信号。 滤波信号的值以连续的时间间隔组合,并且将这些值组合,以便在连续的时间间隔附加滤波信号的值的函数以导出组合信号。 组合信号被转换成表示图像帧中的预测位数的信号。 响应于表示图像的帧中的预测位数的信号,导出表示量化步长控制量值的信号,其作为预测位数与预定目标之间的误差的函数 价值。 输入信号数据的功能被正交变换,从而导出变换信号。 由经变换的信号表示的输出数据被量化,使得它们具有由表示量化步长大小的控制信号确定的量化步长,并且相对于数据位的数量,图像的数据位数减少 输入信号。
    • 58. 发明授权
    • Methods and devices for encoding and decoding frame signals and
recording medium therefor
    • 用于编码和解码帧信号的方法和装置及其记录介质
    • US5510840A
    • 1996-04-23
    • US441397
    • 1995-05-15
    • Jun YonemitsuYoichi Yagasaki
    • Jun YonemitsuYoichi Yagasaki
    • G06T9/00H04N7/26H04N7/46H04N7/50H04N7/54H04N9/804H04N21/236H04N21/434H04N7/24
    • H04N9/8047H04N19/00H04N19/105H04N19/112H04N19/137H04N19/577H04N19/61H04N21/236H04N21/434H04N7/54H04N19/70
    • A motion vector detection circuit detects the motion vector for each macro-block between an odd field and an even field. An encoding system decision circuit decides the type of the encoding system, that is if the encoding system is a field-based encoding system or a frame-based encoding system, based on a median of a motion vector. A control circuit controls gates and changeover switches, in accordance with the encoding system type as decided by the decision system, for generating a field-based reference picture or a frame-based reference picture from buffer memories. The circuitry from an additive node to a VLC circuit finds difference data between the reference picture and the picture to be encoded, while transforming the difference data by discrete cosine transform and variable length encoding the transformed data. The VLC circuit sets the encoding system type as a flag in a header of a predetermined hierarchical layer of a bit stream. By the above operation, any interlaced picture may be encoded efficiently, whether the picture includes little motion or abundant motion or includes both little motion and abundant motion in combination. A picture data decoding device detects the flag and executes decoding by changing over field-based decoding to frame-based decoding or vice versa depending on the flag for reproducing the picture data.
    • 运动矢量检测电路检测奇数场和偶场之间的每个宏块的运动矢量。 编码系统判定电路基于运动矢量的中值决定编码系统的种类,即编码系统是基于场的编码系统或基于帧的编码系统。 控制电路根据由判定系统决定的编码系统类型来控制门和切换开关,用于从缓冲存储器生成基于场的参考图像或基于帧的参考图像。 从附加节点到VLC电路的电路在参考图像和要编码的图像之间找到差分数据,同时通过离散余弦变换和变换数据的可变长度编码对差分数据进行变换。 VLC电路将编码系统类型设置为比特流的预定分层的报头中的标志。 通过上述操作,可以有效地编码任何隔行扫描图像,无论该图像包括少量运动还是丰富的运动,或者包括组合的少量运动和丰富的运动。 图像数据解码装置根据用于再现图像数据的标志,检测标志并执行基于字段的解码到基于帧的解码或反之亦然的解码。
    • 59. 发明授权
    • Data transmission apparatus for transmitting code data
    • 用于发送代码数据的数据发送装置
    • US5481554A
    • 1996-01-02
    • US113801
    • 1993-08-31
    • Tetsujiro Kondo
    • Tetsujiro Kondo
    • H04N5/926H04N5/945H04N7/26H04N7/30H04N7/52H04N7/54H04N19/89G06F11/08
    • H04N21/236H04N19/60H04N19/85H04N19/89H04N19/98H04N21/434H04N5/9261H04N7/54H04N5/9264H04N5/945
    • An ADRC encoder generates an ADRC block of 4.times.4 pixels, together with DR, MIN and quantized pixel data (DT) for each block. A macro block formatting circuit generates DR, MIN and DT code data for four ADRC blocks. An adding circuit generates sum data (DR.SIGMA.=DR1+DR2+DR3+DR4 and MIN.SIGMA.=MIN1+MIN2+MIN3+MIN4) of this hierarchical important data in the macro block. The sum data and the important data form which the sum data is formed are distributed and recorded in plural channels. If one of the important data has an error and the remaining important data and the sum data have no error, the important data with the error can be completely corrected. Reproduced pixel data is converted into 3.times.3 block format and an ADRC encoding circuit generates encoded data DTx representing a center pixel and DT data which represents the 8 pixels that surround the center pixel. A timing aligning circuit generates class information formed of the 8 pixel data, the class information being supplied to a memory as a read address for reading out existing-range data and predicted data DTx that had been stored therein during a learning operation. An error is detected by comparing the existing-range data to the encoded data Dtx; and when an error is detected, the predicted data DTx is selected.
    • ADRC编码器生成4×4像素的ADRC块,以及每个块的DR,MIN和量化像素数据(DT)。 宏块格式化电路为四个ADRC块生成DR,MIN和DT代码数据。 加法电路在宏块中生成该分层重要数据的和数据(DR SIGMA = DR1 + DR2 + DR3 + DR4和MIN SIGMA = MIN1 + MIN2 + MIN3 + MIN4)。 总和数据和形成数据的重要数据形式分布并记录在多个通道中。 如果其中一个重要数据有错误,剩余的重要数据和总和数据没有错误,则可以完全更正重要的数据错误。 再现的像素数据被转换为3×3块格式,并且ADRC编码电路产生代表围绕中心像素的8个像素的中心像素和DT数据的编码数据DTx。 定时对准电路在学习操作期间生成由8像素数据形成的类信息,将类信息作为用于读出现有范围数据的读取地址和已存储在其中的预测数据DTx提供给存储器。 通过将现有范围数据与编码数据Dtx进行比较来检测错误; 并且当检测到错误时,选择预测数据DTx。