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51. 发明授权

US4724519A Channel number priority assignment apparatus 失效
标题翻译：频道编号优先分配装置
公开(公告)号：US4724519A
公开(公告)日：1988-02-09
申请号：US750117
申请日：1985-06-28
申请人： George J. Barlow , James W. Keeley , Elmer W. Carroll
发明人： George J. Barlow , James W. Keeley , Elmer W. Carroll
IPC分类号： G06F13/14 , G06F12/06 , G06F13/362 , G06F13/368 , G06F13/378 , G06F13/36
CPC分类号： G06F13/368 , G06F12/0623 , G06F13/378
摘要： A data processing system has a system bus network which includes a distributed priority network for transferring data asynchronously between a number of subsystems which couple to the bus. Each subsystem includes priority logic circuits coupled to receive a group of priority signals from the priority network which establish when the subsystem has the highest priority of the requesting subsystems to access the bus. The number of subsystems include a plurality of identical subsystems, each of which has a channel number assignment apparatus. The apparatus of each identical subsystem is connected to receive the same of at least one of the group of priority signals. During the idle state of the system bus, the apparatus of each identical subsystem operates to store a unique state of the priority signal which is defined as a function of the subsystem's position on the bus thereby automatically establishing a unique channel number value for each identical subsystem.
摘要翻译：数据处理系统具有系统总线网络，该系统总线网络包括用于在耦合到总线的多个子系统之间异步地传送数据的分布式优先级网络。每个子系统包括优先级逻辑电路，其被耦合以从优先级网络接收一组优先级信号，该优先级信号建立当子系统具有请求子系统访问总线的最高优先级时。子系统的数量包括多个相同的子系统，每个子系统具有信道号分配装置。每个相同子系统的装置被连接以接收该组优先级信号中的至少一个。在系统总线的空闲状态期间，每个相同子系统的装置操作以存储优先级信号的唯一状态，其被定义为总线上子系统位置的函数，从而为每个相同的子系统自动建立唯一的信道数值。

52. 发明授权

US4620278A Distributed bus arbitration according each bus user the ability to inhibit all new requests to arbitrate the bus, or to cancel its own pending request, and according the highest priority user the ability to stop the bus 失效
公开(公告)号：US4620278A
公开(公告)日：1986-10-28
申请号：US527063
申请日：1983-08-29
申请人： James G. Ellsworth , Thomas E. Wulling
发明人： James G. Ellsworth , Thomas E. Wulling
IPC分类号： G06F13/378 , G06F13/36
CPC分类号： G06F13/378
摘要： A digital communication bus upon which arbitration is distributed in a multiplicity of communicable interconnected bus interface logics supports unique signals to each associated on user device and upon the bus. Arbitration inhibiting signals, called inhibit request signals, allow any one(s) user device(s) to inhibit the new entrance, via requests, into arbitration of all other bus interconnected bus interface logics and associated user devices. Arbitration among bus interface logics already registering requests continues in priority order. Each user device may, via a signal called retract request, deregister, or cancel, requests previously registered at the associated bus interface logics to arbitrate for ownership of the bus. Each user device may, via a signal called stop bus, cause continuous interface logics while being precluded from recognition that arbitration should ever be won. When the highest priority one user device so exercises the signal stop bus, then its associated bus interface logics always wins arbitrated ownership of the bus, but naught is known by, or done with, any user device of such ownership; effectively meaning the bus is stopped of normal data communication. Any bus-owning user device may communicate a signal, called priority disable, to the associated bus interface logic and upon a dedicated line of the bus, which signal, called priority disable, to the associated bus interface logic and upon a dedicated line of the bus, which signal postpones the recognition of the winning of arbitration in order that the current bus-owning user may longer retain ownership. Any particular bus interface logics may be, responsively to the setting of a flip-flop called the bus enable flip-flop by any external agency such as any User device or maintenance processor, disabled of any bus activity whatsoever, locking out the associated user device.

53. 发明授权

US4554628A System in which multiple devices have a circuit that bids with a fixed priority, stores all losing bids if its bid wins, and doesn't bid again until all stored bids win 失效
标题翻译：其中多个设备具有以固定优先级出价的电路的系统，如果其出价获胜则存储所有失败的出价，并且不再出价，直到所有存储的出价赢得
公开(公告)号：US4554628A
公开(公告)日：1985-11-19
申请号：US670117
申请日：1984-11-09
申请人： John L. Bell
发明人： John L. Bell
IPC分类号： G06F13/378 , G06F9/46
CPC分类号： G06F13/378
摘要： A bid control circuit is incorporated into a device on a time-shared data bus to control the sequence by which that device bids for the use of the bus. In one preferred embodiment, the bid control circuit includes a means for determining if a bid from that device to use the bus is the highest priority bid being made, a means for storing all bids other than its own bid upon the determination that its bid has the highest priority and that other devices were bidding for the bus and lost, and a means for inhibiting its own future bids until those devices having their bids stored have obtained the use of the bus subsequent to the storing operation.
摘要翻译：出价控制电路被并入到时分数据总线上的设备中，以控制该设备为使用总线而投标的顺序。在一个优选实施例中，投标控制电路包括用于确定来自该设备使用总线的出价是否是最高优先级的出价的装置，用于在确定其出价具有最高优先级和其他设备招标公车并丢失，并且在存储出价的那些设备已经在存储操作之后获得了使用总线的方法，并且禁止其自己的未来投标。

54. 发明授权

US4366480A Demand driven access mechanism 失效
标题翻译：需求驱动访问机制
公开(公告)号：US4366480A
公开(公告)日：1982-12-28
申请号：US273897
申请日：1981-06-15
申请人： David A. Van Hatten
发明人： David A. Van Hatten
IPC分类号： G06F13/378 , H04L12/413 , H04Q3/00
CPC分类号： H04L12/413 , G06F13/378
摘要： A demand driven access mechanism comprises logic apparatus at each station capable of seizing use of a shared communication channel for enabling access to a selected one station. The logic apparatus receives status signals from all stations so that if one station seeks access to the channel it will be enabled immediately upon an inactive status to the channel. If two or more stations simultaneously seek access to the channel, the logic apparatus establishes a priority order between them, thereby enabling access to only one station at a time. The priority ordering is based, in part, by the identity of the station last enabled, to thereby assure priority order allocation among the stations.
摘要翻译：需求驱动的访问机制包括在每个站处的逻辑设备，其能够占用共享通信信道的使用以使得能够访问所选择的一个站。逻辑设备从所有站接收状态信号，使得如果一个站寻求对信道的访问，则它将在对信道的非活动状态时立即被使能。如果两个或多个站同时寻求对信道的访问，则逻辑设备在它们之间建立优先级顺序，从而一次仅访问一个站。优先顺序部分地基于最后启用站的身份，从而确保站之间的优先顺序分配。

55. 发明授权

US4245299A System providing adaptive response in information requesting unit 失效
标题翻译：在信息请求单元中提供自适应响应的系统
公开(公告)号：US4245299A
公开(公告)日：1981-01-13
申请号：US867262
申请日：1978-01-05
申请人： William E. Woods , Richard A. Lemay , John L. Curley
发明人： William E. Woods , Richard A. Lemay , John L. Curley
IPC分类号： G06F13/38 , G06F13/16 , G06F13/378 , G06F13/42 , G06F3/04 , G08C15/00
CPC分类号： G06F13/378 , G06F13/4213
摘要： In a system which includes a common bus to which a plurality of units are connected for the transfer of information, such as a data processing system, information may be transferred by the highest priority unit during an asynchronously generated bus transfer cycle. Logic is provided for enabling a first unit, such as a central processor, to make a multiple fetch request of a second unit, such as a memory, during a first transfer cycle. The multiple fetch request requests the second unit to transfer multiple parts of data to the first unit during multiple further transfer cycles, wherein one part of data is transferred in each further transfer cycle. Logic is provided in the second unit to enable the second unit to indicate to the first unit, except during the last further transfer cycle, that each further transfer cycle will be followed by another further transfer cycle. Logic is provided in the first unit to enable the first unit to accept less parts of data than originally requested in the multiple fetch request. This permits the first unit to make multiple fetch requests of other units on the bus without regard to whether the other units are capable of performing multiple fetch operations and eliminates the need for abnormal condition recovery logic in the second unit. Logic is also provided to permit the first unit to utilize each part of data as it is received by the first unit without requiring the first unit to wait for the last transfer cycle before using any of the received parts of data.
摘要翻译：在包括诸如数据处理系统之类的多个单元连接的公共总线的系统中，在异步生成的总线传送周期期间，信息可以由最高优先级单元传送。逻辑被提供用于使第一单元（例如中央处理器）能够在第一传送周期期间进行诸如存储器的第二单元的多次提取请求。多次提取请求请求第二单元在多个其它传送周期期间将多个数据部分传送到第一单元，其中在每个进一步的传送周期中传送一部分数据。在第二单元中提供逻辑以使第二单元能够向第一单元指示，除了在最后一个进一步的传送周期内，每个进一步的传送周期将跟随另一传送周期。在第一单元中提供逻辑以使得第一单元能够接收比原来在多次提取请求中要求的更少的数据部分。这允许第一单元在总线上进行其他单元的多个提取请求，而不考虑其他单元是否能够执行多次获取操作，并且不需要第二单元中的异常状态恢复逻辑。还提供逻辑以允许第一单元利用第一单元接收的数据的每个部分，而不需要第一单元在使用任何接收的数据部分之前等待最后的传送周期。

56. 发明授权

US4000485A Data processing system providing locked operation of shared resources 失效
标题翻译：数据处理系统提供共享资源的锁定操作
公开(公告)号：US4000485A
公开(公告)日：1976-12-28
申请号：US591904
申请日：1975-06-30
申请人： George J. Barlow , Frank V. Cassarino, Jr. , John W. Conway , David B. O'Keefe
发明人： George J. Barlow , Frank V. Cassarino, Jr. , John W. Conway , David B. O'Keefe
IPC分类号： G06F9/46 , G06F9/52 , G06F13/00 , G06F13/36 , G06F13/368 , G06F13/378 , G06F13/42 , G06F9/18
CPC分类号： G06F13/4213 , G06F13/378
摘要： A central processing system which includes a plurality of units coupled over a common electrical bus for the transfer of information between any two units, includes one unit in which there is a shareable resource such as a memory for example. Apparatus is provided for any units to share such resource. Further apparatus is provided for enabling any of such units so sharing the resource to lock out any other unit which presents a specified control signal to the unit incorporating the resource.
摘要翻译：一种中央处理系统，其包括通过公共电气总线耦合以在任何两个单元之间传送信息的多个单元，包括一个单元，其中存在例如存储器等共享资源。为任何单位提供了共享这种资源的装置。提供了另外的装置，用于使任何这样的单元能够共享资源以将向控制信号提供特定控制信号的任何其它单元锁定到包含资源的单元。

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