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51. 发明授权

US3787835A Converter for gyro-compass digital display 失效
标题翻译： GYRO-COMPASS数字显示转换器
公开(公告)号：US3787835A
公开(公告)日：1974-01-22
申请号：US3787835D
申请日：1972-05-05
申请人： INT STANDARD ELECTRIC CORP
发明人： MATHIESEN O
IPC分类号： G01C19/38 , G06F1/025 , H03M1/00 , H03K13/02
CPC分类号： G06F1/025 , G01C19/38 , G06F2101/04 , H03M1/00 , H03M1/08
摘要： A gyro-compass (synchro) analog output data encoder system for open-loop control of a digital bearing angle indicator in degrees and decimal parts of degrees. Applicable, in general, to digital presentation of shaft angle changes at a remote location.
摘要翻译：陀螺罗盘（同步）模拟输出数据编码器系统，用于数字轴承角度指示器的开环控制，以度数和十进制度为单位。一般来说，适用于远程位置的轴角度变化的数字显示。

52. 发明授权

US11636907B2 Integrity verification of lifecycle-state memory using multi-threshold supply voltage detection 有权
公开(公告)号：US11636907B2
公开(公告)日：2023-04-25
申请号：US16916142
申请日：2020-06-30
申请人： NUVOTON TECHNOLOGY CORPORATION
发明人： Ziv Hershman , Yoel Hayon , Moshe Alon
IPC分类号： G11C29/12 , G11C29/02 , G11C29/44 , G11C29/38 , G11C29/50 , G06F21/57 , G11C5/14 , G06F30/34 , G06F1/025 , G06F3/06 , G06F21/78 , G11C29/04
摘要： An Integrated Circuit (IC) includes a non-volatile memory (NVM) and secure power-up circuitry. The NVM is configured to store an operational state of the IC. The secure power-up circuitry is configured to (i) during a power-up sequence of the IC, perform a first readout of the operational state from the NVM while a supply voltage of the IC is within a first voltage range, (ii) if the operational state read from the NVM in the first readout is a state that permits access to a sensitive resource of the IC, verify that the supply voltage is within a second voltage range, more stringent than the first voltage range, and then perform a second readout of the operational state from the NVM, and (iii) initiate a responsive action in response to a discrepancy between the operational states read from the NVM in the first readout and in the second readout.

53. 发明授权

US10673368B2 System and method for pulse-width modulation using an adjustable comparison criterion 审中-公开
公开(公告)号：US10673368B2
公开(公告)日：2020-06-02
申请号：US15934235
申请日：2018-03-23
申请人： THE BOEING COMPANY
发明人： Douglas C. Cameron , Dwayne C. Merna
IPC分类号： H02P27/08 , G06F1/025 , H03K7/08 , G01P15/08 , H02M7/5387
摘要： A pulse-width modulation control circuit includes a first transistor and a signal generator. The first transistor includes a first terminal coupled to a power source and a second terminal coupled to a first input of a controlled component. The signal generator includes a first node coupled to a gate of the first transistor. The signal generator is configured to receive a comparison value and a comparison criterion and to compare the comparison value to a counter value based on the comparison criterion. In response to the comparison value satisfying the comparison criterion with respect to the counter value, the signal generator is configured to send a control signal to the gate of the first transistor to generate a pulse edge of a pulse of a pulse-width modulated signal.

54. 发明申请

US20190115909A1 CALIBRATION OF A DUAL-PATH PULSE WIDTH MODULATION SYSTEM 审中-公开
公开(公告)号：US20190115909A1
公开(公告)日：2019-04-18
申请号：US16219187
申请日：2018-12-13
申请人： Cirrus Logic International Semiconductor Ltd.
发明人： Tejasvi DAS , Alan Mark MORTON , Xin ZHAO , Lei ZHU , Xiaofan FEI , Johann G. GABORIAU , John L. MELANSON , Amar VELLANKI
IPC分类号： H03K7/08 , H02M3/157 , G06F1/025
CPC分类号： H03K7/08 , G06F1/025 , H02M3/157 , H02M2001/0012 , H03F3/183 , H03F3/2175
摘要： A system may include a digital pulse width modulator subsystem, a first path coupled to an output of the digital pulse width modulator subsystem and configured to drive an open-loop driver stage, a second path coupled to the output of the digital pulse width modulator subsystem and configured to drive a closed-loop analog pulse width modulator, a controller to select between the first path and the second path for processing a signal based on one or more characteristics of the signal, and a calibration subsystem configured to calibrate at least one of a first gain of the first path and a second gain of the second path in order that the first gain and the second gain are at least approximately equal at the time of switching selection between the first path and the second path or vice versa, in order to minimize artifacts due to the switching.

55. 发明授权

US09448581B2 Timer unit circuit having plurality of output modes and method of using the same 有权
标题翻译：具有多种输出模式的定时器单元电路及其使用方法
公开(公告)号：US09448581B2
公开(公告)日：2016-09-20
申请号：US14560960
申请日：2014-12-04
申请人： Renesas Electronics Corporation
发明人： Yasuhiro Takata
IPC分类号： G06F1/04 , G06F1/06 , G06F1/025 , H03K7/08
CPC分类号： G06F1/06 , G06F1/025 , G06F1/04 , H03K7/08
摘要： A timer unit having a first output mode and a second output mode, the timer unit includes a first register that stores a first value, a second register that stores a second value, a third register that stores a third value, a counter that generates a count signal based on the first value, and an output circuit that outputs a first output signal and a second output signal. When the timer unit is set in the first output mode, the output circuit outputs the first output signal having a pulse width determined by the count signal and the second value, and outputs the second output signal having a pulse width determined by the count signal and the third value. When the timer unit is set in the second output mode, the output circuit outputs the first output signal having a pulse width determined by the count signal, the second value and the third value.
摘要翻译：一种具有第一输出模式和第二输出模式的定时器单元，所述定时器单元包括存储第一值的第一寄存器，存储第二值的第二寄存器，存储第三值的第三寄存器，产生第一值的计数器基于第一值的计数信号和输出第一输出信号和第二输出信号的输出电路。当定时器单元设置在第一输出模式时，输出电路输出具有由计数信号和第二值确定的脉冲宽度的第一输出信号，并输出具有由计数信号确定的脉冲宽度的第二输出信号，以及第三个值。当定时器单元设置在第二输出模式时，输出电路输出具有由计数信号确定的脉冲宽度的第一输出信号，第二值和第三值。

56. 发明授权

US09128536B2 Frequency synthesizer and frequency synthesizing method for converting frequency's spurious tones into noise 有权
标题翻译：频率合成器和频率合成方法，用于将频率的伪噪声转换为噪声
公开(公告)号：US09128536B2
公开(公告)日：2015-09-08
申请号：US13412653
申请日：2012-03-06
申请人： Liming Xiu , Ming-Chieh Lin
发明人： Liming Xiu , Ming-Chieh Lin
IPC分类号： G06F1/02 , G06F1/03 , G06F1/025
CPC分类号： G06F1/025 , G06F1/02 , G06F1/022 , G06F1/0328
摘要： One of the advantages of direct frequency synthesis technique (e.g., flying-adder architecture) is its capability of generating arbitrary frequency by utilizing the time-average-frequency concept. In the clock output of the direct frequency synthesizer, instead of one type of cycle, there are two types of cycles. Unlike the conventional one-type-cycle clock wherein clock energy is concentrated at its designed frequency, Time-Average-Frequency based clock spreads some of its energy into spurious tones, which could be harmful to certain applications. The spurious tones are caused by the periodic carry sequence generated from a fractional part accumulator inside the frequency synthesizer. The invention suggests a method and an apparatus to break this periodicity and convert the spurious tones into broadband noise.
摘要翻译：直接频率合成技术（例如飞行加法器结构）的优点之一是其通过利用时间平均频率概念产生任意频率的能力。在直接频率合成器的时钟输出中，代替一种类型的周期，有两种类型的周期。与其中时钟能量集中在其设计频率的常规单周期时钟不同，基于时间 - 平均频率的时钟将其一些能量扩展到伪噪声，这可能对某些应用有害。伪噪声是由频率合成器内的分数分量累加器产生的周期性进位序列引起的。本发明提出了一种破坏这种周期性并将伪噪声转换成宽带噪声的方法和装置。

57. 发明授权

US09071195B2 Method and system for signal synthesis 有权
标题翻译：信号合成方法和系统
公开(公告)号：US09071195B2
公开(公告)日：2015-06-30
申请号：US13977804
申请日：2011-12-26
申请人： David Gabbay
发明人： David Gabbay
IPC分类号： H03B21/00 , G06F1/025
CPC分类号： H03B21/00 , G06F1/025
摘要： The invention describes methods and systems for digital synthesis of electric signals. According to the invention, one or more bit-patterns are provided, each indicative of a rectangular waveform having a characteristic frequency. Further to determining a selected signal frequency to be synthesized, a selected bit-pattern associated therewith is obtained. Bits of the selected bit-pattern are cyclically serialized to generate a substantially rectangular waveform signal comprising the characteristic frequency. Then, the signal is filtered to suppress spurious frequencies outside a certain unfiltered frequency band which corresponds to the selected bit-pattern to thereby obtain a filtered signal with prominent frequency component corresponding to the selected signal frequency.
摘要翻译：本发明描述了用于数字合成电信号的方法和系统。根据本发明，提供了一个或多个位模式，每个位图形指示具有特征频率的矩形波形。为了确定要合成的所选择的信号频率，获得与其相关联的所选择的位模式。所选位图案的位被循环地串行化以产生包括特征频率的基本上矩形的波形信号。然后，对信号进行滤波，以抑制对应于所选位模式的某个未滤波频带之外的杂散频率，从而获得具有对应于所选信号频率的突出频率分量的滤波信号。

58. 发明授权

US08909973B2 Timer unit circuit having plurality of selectors and counter circuits that start counting in response to output of selectors 有权
标题翻译：定时器单元电路具有响应于选择器的输出而开始计数的多个选择器和计数器电路
公开(公告)号：US08909973B2
公开(公告)日：2014-12-09
申请号：US13343437
申请日：2012-01-04
申请人： Yasuhiro Takata
发明人： Yasuhiro Takata
IPC分类号： G06F1/04 , H03K7/08 , G06F1/025
CPC分类号： G06F1/06 , G06F1/025 , G06F1/04 , H03K7/08
摘要： A timer unit includes a first selector that receives a fixed value and a first enable signal, a second selector that receives the fixed value and a count cycle signal, a third selector that receives an output of the second selector, the count cycle signal, and a second enable signal, a first counter circuit that starts counting in response to an output of the first selector, and that generates the count cycle signal and a first counter circuit output signal indicating that a count value approaches a predetermined value, a second counter circuit that starts counting in response to an output of the third selector, and that generates a second counter circuit output signal, a first output signal generator that receives the first counter circuit output signal and the second counter circuit output signal to generate a first output signal, and a second output signal generator.
摘要翻译：定时器单元包括接收固定值的第一选择器和第一使能信号，接收固定值的第二选择器和计数周期信号，接收第二选择器的输出的第三选择器，计数周期信号和第二使能信号，响应于第一选择器的输出开始计数并产生计数周期信号的第一计数器电路和指示计数值接近预定值的第一计数器电路输出信号，第二计数器电路其响应于第三选择器的输出开始计数，并且产生第二计数器电路输出信号;第一输出信号发生器，其接收第一计数器电路输出信号和第二计数器电路输出信号以产生第一输出信号; 和第二输出信号发生器。

59. 发明申请

US20050280449A1 APPARATUS AND METHOD FOR HIGH FREQUENCY STATE MACHINE DIVIDER WITH LOW POWER CONSUMPTION 失效
标题翻译：低功耗高频状态机分路器的装置和方法
公开(公告)号：US20050280449A1
公开(公告)日：2005-12-22
申请号：US10710115
申请日：2004-06-18
申请人： Ram Kelkar , Pradeep Thiagarajan
发明人： Ram Kelkar , Pradeep Thiagarajan
IPC分类号： G06F1/025 , G06F1/04 , H03K21/00
CPC分类号： G06F1/04 , G06F1/025
摘要： A digital frequency divider apparatus includes a plurality of next-state generator elements receiving an input clock signal thereto, and configured to generate a next value for each of a corresponding plurality of internal state variables. A plurality of flip-flop elements is configured to store the generated next values for the plurality of internal state variables, the plurality of flip-flop elements further configured to provide a present value of the plurality of internal state variables to the next-state generator elements through a feedback path therebetween. The generated next values for the plurality of internal state variables are based upon the present values of the plurality of internal state variables and the input clock signal.
摘要翻译：数字分频装置包括多个下一状态发生器元件，其接收输入时钟信号，并且被配置为为相应的多个内部状态变量中的每一个生成下一个值。多个触发器元件被配置为存储针对多个内部状态变量的所生成的下一个值，所述多个触发器元件还被配置为向下一个状态发生器提供多个内部状态变量的当前值元件通过它们之间的反馈路径。所生成的多个内部状态变量的下一个值基于多个内部状态变量和输入时钟信号的当前值。

60. 发明申请

US20050270006A1 System and method for providing digital pulse width modulation 有权
标题翻译：提供数字脉宽调制的系统和方法
公开(公告)号：US20050270006A1
公开(公告)日：2005-12-08
申请号：US11187182
申请日：2005-07-21
申请人： Alain Chapuis
发明人： Alain Chapuis
IPC分类号： G05F1/40 , G06F1/025 , H02M3/157 , H02M3/335 , H02M7/5387 , H03K7/08
CPC分类号： H02M7/53873 , G06F1/025 , H02M3/157 , H03K7/08 , H03M1/661 , H03M1/822
摘要： A pulse width modulation system for use in a switching power supply circuit provides high-resolution pulse width modulated signals. The pulse width modulation system is configured to receive a control signal comprising a (m+n)-bit binary word and to provide a pulse width modulated signal with a predetermined average duty cycle having a resolution of substantially 2−(m+n). The pulse width modulation system includes a timing circuit for providing 2m timing signals, a dithering circuit, and a signal generator. Upon receiving the control signal, the dithering circuit is configured to provide a modified control signal, which comprises a series of up to 2n m-bit binary words. The signal generator is configured to receive the timing signals and the modified control signal and to provide the pulse width modulated signal having a duty cycle, which, when averaged over 2n timing cycles, is approximately equal to the predetermined average duty cycle. The pulse width modulated signal is used by a switching power supply circuit to control at least one power switching device.
摘要翻译：用于开关电源电路的脉宽调制系统提供高分辨率的脉宽调制信号。脉冲宽度调制系统被配置为接收包括（m + n）位二进制字的控制信号，并且提供具有基本为2的分辨率的预定平均占空比的脉宽调制信号 - （m + n）。脉宽调制系统包括一个用于提供2个定时信号的定时电路，一个抖动电路和一个信号发生器。在接收到控制信号时，抖动电路被配置成提供修改的控制信号，该控制信号包括一系列多达2个n位m位二进制字。信号发生器被配置为接收定时信号和修改的控制信号，并提供具有占空比的脉冲宽度调制信号，该占空比在超过2个定时周期时平均大约等于预定的平均占空比。开关电源电路使用脉宽调制信号来控制至少一个功率开关器件。

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