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51. 发明授权

US5786268A Method for forming programmable interconnect structures and programmable integrated circuits 失效
标题翻译：用于形成可编程互连结构和可编程集成电路的方法
公开(公告)号：US5786268A
公开(公告)日：1998-07-28
申请号：US904387
申请日：1997-08-01
申请人： Kathryn E. Gordon , Richard J. Wong
发明人： Kathryn E. Gordon , Richard J. Wong
IPC分类号： H01L23/525 , H01L29/00 , H01L21/44
CPC分类号： H01L23/5252 , H01L2924/0002 , Y10S148/055
摘要： Antifuses and gate arrays with antifuses are disclosed that have high thermal stability, reduced size, reduced leakage current, reduced capacitance in the unprogrammed state, improved manufacturing yield, and more controllable electrical characteristics. Some antifuses include spacers in the antifuse via. In some antifuses, the programmable material is planar, and the top or the bottom electrode is formed in the antifuse via. In some gate arrays, the antifuses are formed above the dielectric separating two levels of routing channels rather than below that dielectric.
摘要翻译：公开了具有抗熔丝的防潮和门阵列，其具有高的热稳定性，减小的尺寸，减小的漏电流，在未编程状态下的减小的电容，改善的制造产量和更可控的电特性。一些反熔丝包括反熔丝通孔中的间隔物。在一些反熔丝中，可编程材料是平面的，并且顶部或底部电极形成在反熔丝通孔中。在一些栅极阵列中，反熔丝形成在介电分离两层布线通道之上，而不是在该介电层之下。

52. 发明授权

US5760453A Moisture barrier layers for integrated circuit applications 失效
标题翻译：用于集成电路应用的防潮层
公开(公告)号：US5760453A
公开(公告)日：1998-06-02
申请号：US922760
申请日：1997-09-03
申请人： Chung-Zen Chen
发明人： Chung-Zen Chen
IPC分类号： H01L23/00 , H01L23/29 , H01L23/525 , H01L29/00 , H01L23/58
CPC分类号： H01L23/564 , H01L23/291 , H01L23/5258 , H01L2924/0002 , Y10S148/055 , Y10S438/94
摘要： The structure and method is provided which prevents moisture and contamination from diffusing through openings (e.g., fuse windows) in insulating layers to product devices. Three moisture barrier layers form a moisture impervious boundary system to prevent moisture from diffusing from a fuse window into other overlying layers and into product devices. First and second barrier layers are formed insulation layers below the fuse. A third barrier layer is formed over an uppermost insulation layer, the sidewalls of a fuse window and over the fuse. The first and third barrier layers form a seal in the fuse area. The method comprises forming an insulating layer 52 54 over portions of said substrate 50 including in said fuse window area 63. A first barrier layer 56, a first interlevel dielectric layer 58 are formed over the insulating layer. A second barrier layer 60 is formed over said first interlevel dielectric layer 58. Then a fuse 62 and overlying insulating and conductive layers 66 70 are formed over said fuse 62. Next, a fuse window 73 is formed through said insulating and conductive layers exposing the fuse and the first barrier layer. A third barrier layer 72 is formed over the fuse window, the fuse and the first barrier layer in the fuse window area.
摘要翻译：提供了防止湿气和污染物通过绝缘层中的开口（例如，熔丝窗）扩散到产品装置的结构和方法。三个防潮层形成不透水的边界系统，以防止水分从保险丝窗口扩散到其他上层并进入产品装置。第一和第二阻挡层在保险丝下方形成绝缘层。第三阻挡层形成在最上绝缘层，保险丝窗的侧壁和熔丝之上。第一和第三阻挡层在保险丝区域中形成密封。该方法包括在包括在所述熔丝窗口区域63中的所述衬底50的部分上形成绝缘层524.在绝缘层上形成第一阻挡层56，第一层间电介质层58。第二阻挡层60形成在所述第一层间电介质层58上。然后在所述保险丝62上方形成保险丝62和覆盖绝缘导电层6670。接下来，通过所述绝缘和导电层形成熔丝窗73，保险丝和第一个阻挡层。在保险丝窗口区域上形成第三阻挡层72，熔丝和熔丝和第一阻挡层。

53. 发明授权

US5726483A Method of jointly forming stacked capacitors and antifuses, method of blowing antifuses, and antifuses and stacked capacitors constituting a part of integrated circuitry 失效
标题翻译：共同形成叠层电容器和反熔丝的方法，吹入反熔丝的方法以及构成集成电路的一部分的反熔丝和叠层电容器
公开(公告)号：US5726483A
公开(公告)日：1998-03-10
申请号：US503022
申请日：1995-07-17
申请人： Charles H. Dennison
发明人： Charles H. Dennison
IPC分类号： H01L23/522 , H01L23/525 , H01L29/00
CPC分类号： H01L23/5252 , H01L23/5223 , H01L2924/0002 , Y10S148/055
摘要： A method of jointly forming stacked capacitors and antifuses includes, a) providing a common layer of electrically conductive material to form both a capacitor storage node and an inner antifuse plate; b) providing a common layer of dielectric material over the capacitor storage node and the inner antifuse plate, the common layer of dielectric material comprising both an intervening capacitor dielectric element and an intervening antifuse dielectric element, the common layer of dielectric material having a first breakdown voltage per unit length value for a given current per unit area; c) providing a common layer of electrically conductive material over the common layer of dielectric material to form both a capacitor cell layer and an outer antifuse plate; d) providing a lateral edge of the outer antifuse plate and a lateral edge of the intervening antifuse dielectric element; and e) depositing an antifuse breakdown layer of dielectric material over the lateral edges of the outer antifuse plate and the intervening antifuse dielectric element, the antifuse breakdown layer having a second breakdown voltage per unit length value for the same given current per same unit area which is lower than said first breakdown voltage per unit length value. Novel antifuse constructions, integrated circuitry and method of blowing antifuses are also disclosed.
摘要翻译：共同形成堆叠电容器和反熔丝的方法包括：a）提供公共的导电材料层以形成电容器存储节点和内部反熔丝板; b）在电容器存储节点和内部反熔丝板之上提供公共介电材料层，所述公共介电材料层包括中间电容器介质元件和中间反熔丝电介质元件，所述公共介电材料层具有第一击穿每单位面积给定电流的单位长度值的电压; c）在公共介电材料层上提供公共导电材料层，以形成电容器电池层和外部反熔丝板; d）提供外部反熔丝板的横向边缘和插入的反熔丝介质元件的横向边缘; 以及e）在所述外部反熔铸板和所述中间反熔丝电介质元件的横向边缘上沉积介电材料的反熔丝击穿层，所述反熔丝击穿层对于相同单位面积的相同给定电流具有每单位长度值的第二击穿电压，低于每单位长度值的所述第一击穿电压。还公开了新型反熔丝结构，集成电路和吹制反熔丝的方法。

54. 发明授权

US5721144A Method of making trimmable modular MOSFETs for high aspect ratio applications 失效
标题翻译：制造用于高宽高比应用的可调节模块化MOSFET的方法
公开(公告)号：US5721144A
公开(公告)日：1998-02-24
申请号：US547180
申请日：1995-10-24
申请人： Chang-Ming Hsieh , Somnuk Ratanaphanyarat , Shao-Fu Sanford Chu , Louis Lu-chen Hsu
发明人： Chang-Ming Hsieh , Somnuk Ratanaphanyarat , Shao-Fu Sanford Chu , Louis Lu-chen Hsu
IPC分类号： H01L21/8234 , H01L27/02 , H01L27/088
CPC分类号： H01L21/823475 , H01L21/823425 , H01L27/0203 , H01L27/088 , Y10S148/055
摘要： An improved design for high aspect ratio MOS devices is capable of 100% yields. The design is suitable for low voltage CMOS devices, such as microprocessors, which use the high aspect ratio MOS devices in embedded applications, and for HEMTs in high frequency applications, such as high power microwave devices. The high yields reduce manufacturing costs. A modular MOS concept is introduced to realize the 100% yield of large channel width devices. The structure of the modular MOS device is a regular MOS device with a unit device channel width. This can be a multi-finger device which has a proper dimension to be able to fit in a given layout area. Therefore, the number of modules which are needed to form a full large width device is not only determined by module size, but also on the manufacturing yield record, allowed chip real estate and performance requirement.
摘要翻译：高纵横比MOS器件的改进设计能够获得100％的产量。该设计适用于诸如微处理器的低电压CMOS器件，其使用嵌入式应用中的高纵横比MOS器件，以及用于诸如高功率微波器件的高频应用中的HEMT。高产量降低了制造成本。引入模块化MOS概念，实现大通道宽度器件的100％产量。模块化MOS器件的结构是具有单位器件沟道宽度的常规MOS器件。这可以是具有适当尺寸以能够适应给定布局区域的多指装置。因此，形成全宽度器件所需的模块数量不仅取决于模块尺寸，还取决于制造产量记录，芯片的可用性和性能要求。

55. 发明授权

US5701027A Programmable interconnect structures and programmable integrated circuits 失效
标题翻译：可编程互连结构和可编程集成电路
公开(公告)号：US5701027A
公开(公告)日：1997-12-23
申请号：US651102
申请日：1996-05-21
申请人： Kathryn E. Gordon , Richard J. Wong
发明人： Kathryn E. Gordon , Richard J. Wong
IPC分类号： H01L23/525 , H01L29/00
CPC分类号： H01L23/5252 , H01L2924/0002 , Y10S148/055
摘要： Antifuses and gate arrays with antifuses are disclosed that have high thermal stability, reduced size, reduced leakage current, reduced capacitance in the unprogrammed state, improved manufacturing yield, and more controllable electrical characteristics. Some antifuses include spacers in the antifuse via. In some antifuses, the programmable material is planar, and the top or the bottom electrode is formed in the antifuse via. In some gate arrays, the antifuses are formed above the dielectric separating two levels of routing channels rather than below that dielectric.
摘要翻译：公开了具有抗熔丝的防潮和门阵列，其具有高热稳定性，减小的尺寸，减小的漏电流，在未编程状态下的减小的电容，改进的制造产量和更可控的电特性。一些反熔丝包括反熔丝通孔中的间隔物。在一些反熔丝中，可编程材料是平面的，并且顶部或底部电极形成在反熔丝通孔中。在一些栅极阵列中，反熔丝形成在介电分离两层布线通道之上，而不是在该介电层之下。

56. 发明授权

US5652459A Moisture guard ring for integrated circuit applications 失效
标题翻译：防潮环用于集成电路应用
公开(公告)号：US5652459A
公开(公告)日：1997-07-29
申请号：US643715
申请日：1996-05-06
申请人： Chung-zen Chen
发明人： Chung-zen Chen
IPC分类号： H01L23/00 , H01L23/525 , H01L23/544 , H01L29/00
CPC分类号： H01L23/564 , H01L23/5256 , H01L23/544 , H01L2223/54453 , H01L2924/0002 , Y10S148/055 , Y10S257/913 , Y10S438/958
摘要： An improved structure and method for forming an integrated circuit guard ring which prevents contamination/moisture from diffusing through a fuse opening, in the insulating layer(s), to device areas, is described. A first insulating layer is formed over portions of the substrate. A gate insulating layer is formed surrounding the first insulating layer. The first ring surrounds a fuse area--including the area where the fuse will be cut by a laser or burned by a current. A first dielectric layer is formed over the substrate surface. A first passivation layer is then formed over the first insulating layer. A first opening is formed through the first passivation layer and first dielectric layer over the first ring. A fuse is formed over the first passivation layer over the fuse area and a second ring of water impervious material is formed on the first ring through the first opening. The first and second rings form a moisture impervious seal. A second insulating layer is then formed over the fuse and the first insulating layer. A fuse opening is etched over at least the fuse area through the second insulating layer and can expose the fuse. A second passivation layer is formed over the second insulating layer and the fuse.
摘要翻译：描述了一种用于形成集成电路保护环的改进的结构和方法，其防止污染/湿气通过绝缘层中的熔丝开口扩散到设备区域。第一绝缘层形成在衬底的部分上。围绕第一绝缘层形成栅极绝缘层。第一环围绕保险丝区域，包括保险丝被激光切割或被电流烧毁的区域。在衬底表面上形成第一电介质层。然后在第一绝缘层上形成第一钝化层。通过第一环上的第一钝化层和第一介电层形成第一开口。在保险丝区域上方的第一钝化层上形成保险丝，并且通过第一开口在第一环上形成第二不透水材料环。第一和第二环形成不透水的密封。然后在熔丝和第一绝缘层上形成第二绝缘层。保险丝开口至少通过第二绝缘层在熔断器区域上蚀刻，并且可以使保险丝露出。在第二绝缘层和熔丝上形成第二钝化层。

57. 发明授权

US5581111A Dielectric-polysilicon-dielectric antifuse for field programmable logic applications 失效
标题翻译：用于现场可编程逻辑应用的介质 - 多晶硅 - 电介质反熔丝
公开(公告)号：US5581111A
公开(公告)日：1996-12-03
申请号：US289114
申请日：1994-08-11
申请人： Wenn-Jei Chen
发明人： Wenn-Jei Chen
IPC分类号： H01L23/525 , H01L27/02
CPC分类号： H01L23/5252 , H01L2924/0002 , H01L2924/3011 , Y10S148/055
摘要： A novel antifuse structure includes a novel antifuse material layer comprises a first dielectric layer, a first polysilicon layer (which may optionally be lightly doped) disposed over the first dielectric layer, and a second dielectric layer disposed over the first polysilicon layer. The dielectric layers may be formed of silicon nitride, silicon dioxide, silicon oxynitride and combinations of the foregoing. Additional layers may also be included to form D/P/D/P/D, D/P/D/a-Si/D sandwiches, and the like. The polysilicon layer provides the ability to control the breakdown voltage of the antifuse through control of the doping level while maintaining a relatively large thickness of the antifuse material layer resulting in low capacitance for the antifuse. The antifuse material layer is compatible with high temperature processes (500.degree. C.-950.degree. C.) and may be carried out in the range of 400.degree. C.-950.degree. C. making it compatible with a wide range of processes.
摘要翻译：一种新颖的反熔丝结构包括一种新颖的反熔丝材料层，其包括第一介电层，设置在第一介电层上的第一多晶硅层（其可任选地是轻掺杂的）和设置在第一多晶硅层上的第二介电层。电介质层可以由氮化硅，二氧化硅，氮氧化硅以及前述的组合形成。还可以包括另外的层以形成D / P / D / P / D，D / P / D / a-Si / D三明治等。多晶硅层提供通过控制掺杂水平来控制反熔丝的击穿电压的能力，同时保持反熔丝材料层的相对较大的厚度，从而导致反熔丝的低电容。反熔丝材料层与高温工艺（500℃〜950℃）兼容，可在400℃〜950℃的范围内进行，使其与广泛的工艺相容。

58. 发明授权

US5573970A Method for reducing contamination of anti-fuse material in an anti-fuse structure 失效
标题翻译：减少反熔丝结构中抗熔丝材料污染的方法
公开(公告)号：US5573970A
公开(公告)日：1996-11-12
申请号：US477311
申请日：1995-06-06
申请人： Dipankar Pramanik , Subhash R. Nariani
发明人： Dipankar Pramanik , Subhash R. Nariani
IPC分类号： H01L23/525 , H01L21/70 , H01L27/00
CPC分类号： H01L23/5252 , H01L2924/0002 , Y10S148/055
摘要： An anti-fuse structure formed in accordance with the present invention includes a conductive layer base. A layer of anti-fuse material overlies the conductive base layer. On top of the anti-fuse layer is an insulating layer, in which a via hole is formed to the anti-fuse layer. The lateral dimension of the via hole is less than about 0.8 microns. Provided in the via hole is a conductive non-Al plug which overlies a layer of a a conductive barrier material such as TiN or TiW that contacts the anti-fuse material and overlies the insulating layer. Tungsten is effectively used as the non-Al plug. An electrically conductive layer is formed over the plug and is separated from the conductive barrier material overlying the anti-fuse layer by the plug. The structure is then programmable by application of a programming voltage and readable by application of a sensing voltage, which is lower than the programming voltage.
摘要翻译：根据本发明形成的抗熔丝结构包括导电层基底。一层抗熔丝材料覆盖在导电基层上。在抗熔丝层的顶部是绝缘层，其中在反熔丝层上形成通孔。通孔的横向尺寸小于约0.8微米。在通孔中设置有导电性非铝塞，其覆盖与导电阻挡材料（例如TiN或TiW）接触反熔丝材料并覆盖绝缘层的层。钨被有效地用作非铝插头。导电层形成在插塞上方，并且通过插头与覆盖抗熔丝层的导电阻挡材料分离。然后通过施加编程电压可编程结构，并通过施加低于编程电压的感测电压来读取结构。

59. 发明授权

US5538924A Method of forming a moisture guard ring for integrated circuit applications 失效
标题翻译：形成用于集成电路应用的防潮环的方法
公开(公告)号：US5538924A
公开(公告)日：1996-07-23
申请号：US523792
申请日：1995-09-05
申请人： Chung-zen Chen
发明人： Chung-zen Chen
IPC分类号： H01L23/00 , H01L23/525 , H01L23/544 , H01L21/465
CPC分类号： H01L23/564 , H01L23/5256 , H01L23/544 , H01L2223/54453 , H01L2924/0002 , Y10S148/055 , Y10S257/913 , Y10S438/958
摘要： An improved structure and method for forming an integrated circuit guard ring which prevents contamination/moisture from diffusing through a fuse opening, in the insulating layer(s), to device areas, is described. A first insulating layer is formed over portions of the substrate. A gate insulating layer is formed surrounding the first insulating layer. The first ring surrounds a fuse area--including the area where the fuse will be cut by a laser or burned by a current. A first dielectric layer is formed over the substrate surface. A first passivation layer is then formed over the first insulating layer. A first opening is formed through the first passivation layer and first dielectric layer over the first ring. A fuse is formed over the first passivation layer over the fuse area and a second ring of water impervious material is formed on the first ring through the first opening. The first and second rings form a moisture impervious seal. A second insulating layer is then formed over the fuse and the first insulating layer. A fuse opening is etched over at least the fuse area through the second insulating layer and can expose the fuse. A second passivation layer is formed over the second insulating layer and the fuse.
摘要翻译：描述了一种用于形成集成电路保护环的改进的结构和方法，其防止污染/湿气通过绝缘层中的熔丝开口扩散到设备区域。第一绝缘层形成在衬底的部分上。围绕第一绝缘层形成栅极绝缘层。第一环围绕保险丝区域，包括保险丝被激光切割或被电流烧毁的区域。在衬底表面上形成第一电介质层。然后在第一绝缘层上形成第一钝化层。通过第一环上的第一钝化层和第一介电层形成第一开口。在保险丝区域上方的第一钝化层上形成保险丝，并且通过第一开口在第一环上形成第二不透水材料环。第一和第二环形成不透水的密封。然后在熔丝和第一绝缘层上形成第二绝缘层。保险丝开口至少通过第二绝缘层在熔断器区域上蚀刻，并且可以使保险丝露出。在第二绝缘层和熔丝上形成第二钝化层。

60. 发明授权

US5475253A Antifuse structure with increased breakdown at edges 失效
标题翻译：防腐结构边缘增加破裂
公开(公告)号：US5475253A
公开(公告)日：1995-12-12
申请号：US132071
申请日：1993-10-04
申请人： Kevin T. Look , Evert A. Wolsheimer
发明人： Kevin T. Look , Evert A. Wolsheimer
IPC分类号： H01L21/82 , H01L21/768 , H01L23/525 , H01L27/10 , H01L29/04 , H01L27/02 , H01L49/00
CPC分类号： H01L21/76888 , H01L23/5252 , H01L2924/0002 , Y10S148/055
摘要： An antifuse is provided which includes a first conductive layer, an antifuse layer formed on the first conductive layer, and a second conductive layer formed on the antifuse layer. A portion of the antifuse layer forms a substantially orthogonal angle with the first conductive layer and the second conductive layer. This "corner" formation of the antifuse enhances the electric field at this location during programming, thereby providing a predictable location for the filament, i.e. the conductive path between the first and second conductive layers. This antifuse provides other advantages including: a relatively low programming voltage, good step coverage for the antifuse layer and the upper conductive layer, a low, stable resistance value, and minimal shearing effects on the filament.
摘要翻译：提供一种反熔丝，其包括第一导电层，形成在第一导电层上的反熔丝层，以及形成在反熔丝层上的第二导电层。反熔丝层的一部分与第一导电层和第二导电层形成大致正交的角度。反熔丝的这种“角”形成在编程期间增强了该位置处的电场，从而为灯丝提供可预测的位置，即第一和第二导电层之间的导电路径。该反熔丝提供了其它优点，包括：相对较低的编程电压，反熔丝层和上导电层的良好阶梯覆盖，低稳定的电阻值以及对细丝的最小剪切效应。

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