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51. 发明申请

US20150250055A1 ELECTROMAGNETIC FIELD MANIPULATION AROUND VIAS 有权
标题翻译：六角电磁场操作
公开(公告)号：US20150250055A1
公开(公告)日：2015-09-03
申请号：US14194278
申请日：2014-02-28
申请人： FUJITSU LIMITED
发明人： Yasuo HIDAKA
IPC分类号： H05K1/11 , H05K3/46 , H05K1/02
CPC分类号： H05K1/116 , H05K1/0225 , H05K1/0251 , H05K3/0047 , H05K3/429 , H05K2201/093 , H05K2201/096 , H05K2201/09618 , H05K2201/09718 , H05K2201/09727 , H05K2201/09845 , Y10T29/49165
摘要： A circuit may include a signal path, a first layer including the signal path, and a second layer including the signal path. The circuit may additionally include a path via having a signal-path via location and configured to connect the signal path at the first layer with the signal path at the second layer. The circuit may also include a ground plane associated with the first layer. The ground plane may have a ground-plane location that corresponds to the signal-path via location. The ground plane may also include an asymmetrical cutout portion that extends away from the ground-plane location on a first side of the ground plane that is opposite a second side of the ground plane that corresponds with a side of the first layer where the path via interfaces with the signal path at the first layer.
摘要翻译：电路可以包括信号路径，包括信号路径的第一层，以及包括信号路径的第二层。电路还可以包括具有经由位置的信号路径的路径通路，并被配置为将第一层处的信号路径与第二层处的信号路径连接。电路还可以包括与第一层相关联的接地平面。接地平面可以具有对应于信号路径经过位置的接地平面位置。接地平面还可以包括不对称的切口部分，其在接地平面的第一侧上远离接地平面位置延伸，该接地平面位于接地平面的与第一层的一侧相对的第二侧，其中通路与第一层的信号路径接口。

52. 发明申请

US20150237715A1 PRINTED CIRCUIT BOARD 有权
标题翻译：印刷电路板
公开(公告)号：US20150237715A1
公开(公告)日：2015-08-20
申请号：US14550535
申请日：2014-11-21
申请人： HONG FU JIN PRECISION INDUSTRY (WuHan) CO., LTD. , HON HAI PRECISION INDUSTRY CO., LTD.
发明人： FENG-HUA DENG , FENG ZHANG
IPC分类号： H05K1/02 , H05K1/11
CPC分类号： H05K1/0251 , H05K1/0225 , H05K1/113 , H05K1/115 , H05K1/116
摘要： A printed circuit board includes a first dielectric layer, a first ground layer, a second dielectric layer, a first power layer, a first via hole and a ground hole extending through the printed circuit board. A first signal line is laid on the first dielectric layer. A third signal line is laid on the second dielectric layer. The first and third signal lines are electrically connected to the first via hole. An extending direction of the first signal line on the first dielectric layer is the same as an extending direction of the third signal line is laid on the second dielectric layer. A first void area is defined in the first ground layer around the first via hole. A second void area is defined in the first power layer around the first via hole. The ground hole is outside the first void area and the second void area.
摘要翻译：印刷电路板包括第一介电层，第一接地层，第二电介质层，第一电源层，第一通孔和延伸穿过印刷电路板的接地孔。第一信号线被放置在第一电介质层上。第三信号线被放置在第二电介质层上。第一和第三信号线电连接到第一通孔。第一电介质层上的第一信号线的延伸方向与第二信号线的延伸方向相同。在第一通孔周围的第一接地层中限定第一空隙区域。在第一通孔周围的第一功率层中限定第二空隙区域。地孔在第一空隙区域和第二空隙区域之外。

53. 发明授权

US09099458B2 Construction of reliable stacked via in electronic substrates—vertical stiffness control method 有权
标题翻译：在电子基板中构建可靠的堆叠通孔 - 垂直刚度控制方法
公开(公告)号：US09099458B2
公开(公告)日：2015-08-04
申请号：US13539480
申请日：2012-07-01
申请人： Karan Kacker , Douglas O. Powell , David L. Questad , David J. Russell , Sri M. Sri-Jayantha
发明人： Karan Kacker , Douglas O. Powell , David L. Questad , David J. Russell , Sri M. Sri-Jayantha
IPC分类号： H05K1/11 , H05K1/09 , H01L23/498 , H05K3/46 , H05K1/02
CPC分类号： H01L23/49827 , H01L23/49838 , H01L2224/05001 , H01L2224/05548 , H01L2224/05572 , H01L2224/16 , H01L2924/00014 , H01L2924/15311 , H05K1/0271 , H05K1/116 , H05K3/4602 , H05K2201/0347 , H05K2201/09454 , H05K2201/09536 , H05K2201/0959 , H05K2201/096 , H05K2201/0969 , Y10T29/49155 , H01L2224/05599 , H01L2224/05099
摘要： A stacked via structure for reducing vertical stiffness includes: a plurality of stacked vias, each via disposed on a disc-like structure. The disc-like structure includes a platted through hole landing supporting the plurality of stacked vias. The platted through hole landing includes an etched pattern.
摘要翻译：用于减小垂直刚度的堆叠通孔结构包括：多个堆叠的通孔，每个通孔设置在盘状结构上。盘状结构包括支撑多个堆叠的通孔的平板通孔平台。镀层通孔着色包括蚀刻图案。

54. 发明申请

US20150208512A1 MANUFACTURING METHOD OF PART-MOUNTING PACKAGE 审中-公开
标题翻译：部件安装包装的制造方法
公开(公告)号：US20150208512A1
公开(公告)日：2015-07-23
申请号：US14597935
申请日：2015-01-15
申请人： NGK SPARK PLUG CO., LTD.
发明人： Kazushige AKITA
IPC分类号： H05K3/00 , H05K3/46 , H05K3/10
CPC分类号： H05K3/0097 , H05K1/113 , H05K1/116 , H05K1/183 , H05K3/0044 , H05K3/0052 , H05K3/10 , H05K3/403 , H05K3/4611 , H05K3/4614 , H05K3/4697 , H05K2201/0909 , H05K2201/0919 , H05K2201/0949 , H05K2201/09845 , Y10T29/49147 , Y10T29/49165 , Y10T29/49792 , Y10T29/49798
摘要： A method of manufacturing a part-mounting package includes: forming a first through-hole in a first insulating sheet and forming a second through-hole whose opening area is larger than the first through-hole in a second insulating sheet; forming a penetration conductor covering an inner surface of the second through-hole and forming a conductor layer on a surface of at least the second insulating sheet; laminating the first insulating sheet and the second insulating sheet where center positions of the first through-hole and the second through-hole are matched to each other; causing linear laser division grooves to pass through a center of the first through-hole and the second through-hole; and dividing the sheet laminated body along the laser division grooves, and causing the side surface recess part and the end face through-hole conductor to appear.
摘要翻译：制造部件安装封装的方法包括：在第一绝缘片中形成第一通孔，并在第二绝缘片中形成开口面积大于第一通孔的第二通孔; 形成覆盖所述第二通孔的内表面的穿透导体，并且在至少所述第二绝缘片的表面上形成导体层; 层叠第一绝缘片和第二绝缘片，其中第一通孔和第二通孔的中心位置相互匹配; 使线性激光分割槽穿过第一通孔和第二通孔的中心; 并且沿着激光分割槽分割片材层叠体，并且使侧表面凹部和端面通孔导体出现。

55. 发明授权

US09072188B2 Package substrate, method of manufacturing the package substrate and semiconductor package including the package substrate 有权
标题翻译：封装衬底，制造封装衬底的方法和包括封装衬底的半导体封装
公开(公告)号：US09072188B2
公开(公告)日：2015-06-30
申请号：US14194647
申请日：2014-02-28
申请人： Samsung Electronics Co., Ltd.
发明人： Tae-Young Yoon
IPC分类号： H05K1/11 , H05K3/24 , H01L25/065 , H01L23/48 , H01L23/498 , H01L23/538 , H01L23/31 , H01L23/00
CPC分类号： H05K1/116 , H01L23/3128 , H01L23/481 , H01L23/49827 , H01L23/49866 , H01L23/5381 , H01L24/16 , H01L24/32 , H01L24/48 , H01L24/73 , H01L25/0657 , H01L2224/16145 , H01L2224/16225 , H01L2224/16235 , H01L2224/32145 , H01L2224/48091 , H01L2224/48227 , H01L2224/48235 , H01L2224/73265 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06562 , H01L2924/00014 , H01L2924/15311 , H01L2924/181 , H05K1/113 , H05K3/242 , H05K2201/09227 , H05K2201/10734 , H05K2203/175 , Y10T29/49155 , Y10T29/49165 , H01L2224/32225 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A package substrate may include an insulating substrate, a first land array, a second land array, a first plating line and a second plating line. The first land array may be arranged on a first surface of the insulating substrate. The second land array may be arranged on a second surface of the insulating substrate opposite to the first surface. The second land array may be electrically connected to the first land array. The second land array may include outer lands and inner lands. The first plating line may be connected to the outer lands. The second plating line may be connected between the outer lands and the inner lands. The second plating line may have a width narrower than that of the first plating line. The second plating line may be removed by applying a removing current to the first plating line prior to the first plating line.
摘要翻译：封装基板可以包括绝缘基板，第一焊盘阵列，第二焊盘阵列，第一电镀线和第二电镀线。第一焊盘阵列可以布置在绝缘基板的第一表面上。第二平台阵列可以布置在与第一表面相对的绝缘基板的第二表面上。第二焊盘阵列可以电连接到第一焊盘阵列。第二焊盘阵列可以包括外部焊盘和内部焊盘。第一电镀线可以连接到外部焊盘。第二电镀线可以连接在外部焊盘和内部焊盘之间。第二电镀线的宽度可以比第一电镀线的宽度窄。可以通过在第一电镀线之前向第一电镀线施加去除电流来去除第二电镀线。

56. 发明申请

US20150180104A1 REDUCED BACKDRILLING WITH QUARTER WAVELENGTH TRANSMISSION LINE STUBS 有权
标题翻译：具有四分之一波长传输线路的减少后退
公开(公告)号：US20150180104A1
公开(公告)日：2015-06-25
申请号：US14135210
申请日：2013-12-19
申请人： Lenovo Enterprise Solutions (Singapore) Pte. Ltd.
发明人： Eric R. Ao , Donald R. Dignam , Stephen J. Flint , Jian Meng
IPC分类号： H01P1/203 , G06F17/50
CPC分类号： H01P1/2039 , H05K1/024 , H05K1/0248 , H05K1/116 , H05K3/0005 , H05K3/429 , H05K2201/0187
摘要： Embodiments of the present invention provide for a transmission line stub that includes a via stub of a conductive via. The conductive via includes a via stub and a coupling element, wherein a first transmission line configured to transmit a signal is coupled to the conductive via at the intersection of the via stub and the coupling element. The coupling element is configured to transmit the signal from the first transmission line. A line stub electrically coupled to the via stub, wherein the length of the line stub is selected such that the transmission line stub having a length of the sum of the lengths of the via stub and the line stub is configured to suppress a preselected frequency.
摘要翻译：本发明的实施例提供一种传输线短截线，其包括导电通孔的通孔短路。导电通孔包括通孔短截线和耦合元件，其中配置成传输信号的第一传输线在通孔短路和耦合元件的相交处耦合到导电通孔。耦合元件被配置为从第一传输线传输信号。电气耦合到通路短截线的线段，其中选择线段的长度，使得具有通孔短路和线路短线的长度之和的长度的传输线短截线被配置为抑制预选频率。

57. 发明申请

US20150116950A1 COIL COMPONENT, MANUFACTURING METHOD THEREOF, COIL COMPONENT-EMBEDDED SUBSTRATE, AND VOLTAGE ADJUSTMENT MODULE HAVING THE SAME 审中-公开
标题翻译：线圈组件及其制造方法，线圈组件嵌入式基板及其电压调整模块
公开(公告)号：US20150116950A1
公开(公告)日：2015-04-30
申请号：US14524940
申请日：2014-10-27
申请人： SAMSUNG ELECTRO-MECHANICS CO., LTD.
发明人： Ji No YOO , Han KIM , Won Gi KIM , Suk Hyeon CHO
IPC分类号： H01F27/28 , H05K7/02 , H01F41/02 , H01F27/29
CPC分类号： H01F27/2804 , H01F27/022 , H01F27/255 , H05K1/116 , H05K1/185 , H05K3/46 , H05K2201/086 , H05K2201/1003 , H05K2201/10196 , Y10T29/49075
摘要： A coil component may be capable of being easily manufactured and significantly decreasing direct current (DC) resistance of its wiring. The coil component may include a coil assembly including a core substrate and coil patterns formed on the core substrate; and a magnetic material part embedding the coil assembly therein.
摘要翻译：线圈部件可以容易地制造并且显着降低其布线的直流（DC）电阻。线圈部件可以包括线圈组件，其包括芯基板和形成在芯基板上的线圈图案; 以及将线圈组件嵌入其中的磁性材料部分。

58. 发明申请

US20150085458A1 Reducing Far End Crosstalk in Single Ended Interconnects and Buses 审中-公开
标题翻译：减少单端互连和总线中的远端串扰
公开(公告)号：US20150085458A1
公开(公告)日：2015-03-26
申请号：US14037826
申请日：2013-09-26
申请人： Raul Enriquez Shibayama , Mauro Lai , Richard K. Kunze , Nicholas B. Peterson , Carlos A. Lizalde Moreno , Kai Xiao
发明人： Raul Enriquez Shibayama , Mauro Lai , Richard K. Kunze , Nicholas B. Peterson , Carlos A. Lizalde Moreno , Kai Xiao
IPC分类号： H05K1/02 , H05K3/30 , H05K1/11
CPC分类号： H05K1/0231 , H01L23/49822 , H01L23/49827 , H01L2924/0002 , H05K1/0228 , H05K1/115 , H05K1/116 , H05K1/162 , H05K3/303 , H05K2201/09636 , Y10T29/4913 , H01L2924/00
摘要： Inductive coupling arising between adjacent vias in interconnect technologies (commonly associated with printed circuit boards or package) can be combatted through the addition of metal plates to vias. The plates generate capacitive coupling that can compensate for the inductive crosstalk normally generated between vias in printed circuit boards or packages. When the added plates of two neighboring vias overlap with each other, a capacitive coupling is generated. By balancing the inductive coupling with capacitive coupling, an effective reduction of far end crosstalk may be obtained.
摘要翻译：通过在通孔中添加金属板，互连技术中相邻通孔之间产生的感应耦合（通常与印刷电路板或封装相关联）可以对抗。板产生电容耦合，可以补偿印刷电路板或封装中通孔之间通常产生的电感串扰。当两个相邻通孔的添加板彼此重叠时，产生电容耦合。通过将电感耦合与电容耦合进行平衡，可以获得远端串扰的有效减少。

59. 发明申请

US20150053468A1 METHOD TO MAKE A MULTILAYER CIRCUIT BOARD WITH INTERMETALLIC COMPOUND AND RELATED CIRCUIT BOARDS 有权
标题翻译：制造具有互联化合物和相关电路板的多层电路板的方法
公开(公告)号：US20150053468A1
公开(公告)日：2015-02-26
申请号：US14532224
申请日：2014-11-04
申请人： HARRIS CORPORATION
发明人： MICHAEL RAYMOND WEATHERSPOON , LOUIS JOSEPH RENDEK, JR. , LAWRENCE WAYNE SHACKLETTE , CASEY PHILIP RODRIGUEZ
IPC分类号： H05K1/02 , H05K1/11 , H05K1/09
CPC分类号： H05K1/0298 , H05K1/09 , H05K1/116 , H05K3/429 , H05K3/4614 , H05K2201/0141 , H05K2201/09545 , H05K2203/061 , Y10T29/49117 , Y10T29/49124 , Y10T29/49126 , Y10T29/49155 , Y10T29/49165
摘要： A method for making a multilayer circuit board from circuit board layers, each including a dielectric layer and conductive traces thereon including a first metal. The method includes forming a through-via in a first circuit board layer, plating the through-via with the first metal, and coating a second metal onto the first metal of the first circuit board layer, the plated through-via, and the first metal. The method also includes aligning the first and second circuit board layers together so that the plated through-via of the first circuit board layer is adjacent a feature on the second circuit board layer, and heating and pressing the aligned first and second circuit board layers so as to laminate the dielectric layers together and form an intermetallic compound of the first and second metals bonding adjacent metal portions.
摘要翻译：一种从电路板层制造多层电路板的方法，每个电路板包括电介质层和其上包括第一金属的导电迹线。该方法包括在第一电路板层中形成通孔，将通孔与第一金属电镀，并将第二金属涂覆在第一电路板层的第一金属上，镀通孔和第一金属金属。该方法还包括将第一和第二电路板层对准在一起，使得第一电路板层的电镀通孔与第二电路板层上的特征相邻，并且加热并压紧对准的第一和第二电路板层以将电介质层层合在一起并形成接合相邻金属部分的第一和第二金属的金属间化合物。

60. 发明申请

US20150053467A1 MULTILAYER SUBSTRATE 有权
标题翻译：多层基板
公开(公告)号：US20150053467A1
公开(公告)日：2015-02-26
申请号：US14526698
申请日：2014-10-29
申请人： Murata Manufacturing Co., Ltd.
发明人： Shigetoshi Hayashi , Tomoya Yokoyama , Takako Sato
IPC分类号： H05K1/02 , H05K1/03 , H05K1/09 , H05K1/11
CPC分类号： H05K1/112 , H01L23/13 , H01L23/15 , H01L23/49805 , H01L23/49822 , H01L23/49838 , H01L2224/16225 , H01L2924/15162 , H01L2924/1531 , H01L2924/19105 , H05K1/0271 , H05K1/0298 , H05K1/0306 , H05K1/092 , H05K1/113 , H05K1/116 , H05K1/165 , H05K3/403 , H05K3/4629 , H05K2201/083 , H05K2201/09145
摘要： Provided is a multilayer substrate that can prevent generation of cracks caused by stress generated due to a difference between the coefficient of linear expansion of electrode pads and that of a ceramic material. An electrode pad arranged on a layer below an outermost component mounting electrode pad has a larger area than an area of the component mounting electrode pad. Similarly, an electrode pad arranged on a layer below a component mounting electrode pad has a larger area than an area of the component mounting electrode pad, an electrode pad arranged on a layer below a component mounting electrode pad has a larger area than an area of the component mounting electrode pad, and an electrode pad arranged on a layer below a component mounting electrode pad has a larger area than an area of the component mounting electrode pad.
摘要翻译：提供一种多层基板，其可以防止由于电极焊盘的线膨胀系数与陶瓷材料的线性膨胀系数之间的差异而产生的应力产生的裂纹。布置在最外面部件安装电极焊盘下方的层上的电极焊盘的面积大于部件安装电极焊盘的面积。类似地，布置在部件安装电极焊盘下方的层上的电极焊盘具有比部件安装电极焊盘的面积更大的面积，布置在部件安装电极焊盘下方的电极焊盘的面积大于部件安装电极焊盘和布置在部件安装电极焊盘下方的层上的电极焊盘的面积大于部件安装电极焊盘的面积。

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