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1. 发明申请

US20150085458A1 Reducing Far End Crosstalk in Single Ended Interconnects and Buses 审中-公开
标题翻译：减少单端互连和总线中的远端串扰
公开(公告)号：US20150085458A1
公开(公告)日：2015-03-26
申请号：US14037826
申请日：2013-09-26
申请人： Raul Enriquez Shibayama , Mauro Lai , Richard K. Kunze , Nicholas B. Peterson , Carlos A. Lizalde Moreno , Kai Xiao
发明人： Raul Enriquez Shibayama , Mauro Lai , Richard K. Kunze , Nicholas B. Peterson , Carlos A. Lizalde Moreno , Kai Xiao
IPC分类号： H05K1/02 , H05K3/30 , H05K1/11
CPC分类号： H05K1/0231 , H01L23/49822 , H01L23/49827 , H01L2924/0002 , H05K1/0228 , H05K1/115 , H05K1/116 , H05K1/162 , H05K3/303 , H05K2201/09636 , Y10T29/4913 , H01L2924/00
摘要： Inductive coupling arising between adjacent vias in interconnect technologies (commonly associated with printed circuit boards or package) can be combatted through the addition of metal plates to vias. The plates generate capacitive coupling that can compensate for the inductive crosstalk normally generated between vias in printed circuit boards or packages. When the added plates of two neighboring vias overlap with each other, a capacitive coupling is generated. By balancing the inductive coupling with capacitive coupling, an effective reduction of far end crosstalk may be obtained.
摘要翻译：通过在通孔中添加金属板，互连技术中相邻通孔之间产生的感应耦合（通常与印刷电路板或封装相关联）可以对抗。板产生电容耦合，可以补偿印刷电路板或封装中通孔之间通常产生的电感串扰。当两个相邻通孔的添加板彼此重叠时，产生电容耦合。通过将电感耦合与电容耦合进行平衡，可以获得远端串扰的有效减少。

2. 发明授权

US6055372A Serial interrupt bus protocol 失效
标题翻译：串行中断总线协议
公开(公告)号：US6055372A
公开(公告)日：2000-04-25
申请号：US845634
申请日：1997-05-01
申请人： James Kardach , Sung Soo Cho , Nicholas B. Peterson , Thomas R Lane , Jayesh M. Joshi , Neil Songer
发明人： James Kardach , Sung Soo Cho , Nicholas B. Peterson , Thomas R Lane , Jayesh M. Joshi , Neil Songer
IPC分类号： G06F13/24 , G06F9/46
CPC分类号： G06F13/24
摘要： A serial interrupt bus protocol is implemented in which any number of peripherals in a computer system may signal any predetermined interrupt signals to the system's interrupt controller without requiring a dedicated pin for each possible interrupt. Each peripheral implemented on the serial interrupt bus incorporates state machine logic for cycling through possible interrupt states. The peripherals are daisy chained beginning and ending with a serial interrupt controller which follows the same state machine logic as the system peripherals. When the serial interrupt controller receives an active interrupt signal, it determines which interrupt signal to provide to the system's interrupt controller based on the interrupt state of the interrupt controller state machine logic. Peripherals on a secondary serial interrupt bus may be daisy chained with peripherals on a primary system interrupt bus through a system interrupt bridge which also includes state machine logic for following the same state diagram as the system peripherals.
摘要翻译：实现串行中断总线协议，其中计算机系统中的任何数量的外围设备可以向系统的中断控制器发出任何预定的中断信号，而不需要针对每个可能的中断的专用引脚。在串行中断总线上实现的每个外设都包含状态机逻辑，用于循环通过可能的中断状态。外设以串联中断控制器为起始和结束，该控制器遵循与系统外设相同的状态机器逻辑。当串行中断控制器接收到一个有效的中断信号时，根据中断控制器状态机逻辑的中断状态确定提供给系统中断控制器的中断信号。辅助串行中断总线上的外设可以通过系统中断桥与主系统中断总线上的外设串联链接，系统中断总线还包括状态机逻辑，用于跟随与系统外设相同的状态图。

3. 发明授权

US5671421A Serial interrupt bus protocol 失效
标题翻译：串行中断总线协议
公开(公告)号：US5671421A
公开(公告)日：1997-09-23
申请号：US351637
申请日：1994-12-07
申请人： James Kardach , Sung Soo Cho , Nicholas B. Peterson , Thomas R. Lane , Jayesh M. Joshi , Neil Songer
发明人： James Kardach , Sung Soo Cho , Nicholas B. Peterson , Thomas R. Lane , Jayesh M. Joshi , Neil Songer
IPC分类号： G06F13/24 , G06F9/46 , G06F13/14
CPC分类号： G06F13/24
摘要： A serial interrupt bus protocol is implemented in which any number of peripherals in a computer system may signal any predetermined interrupt signals to the system's interrupt controller without requiring a dedicated pin for each possible interrupt. Each peripheral implemented on the serial interrupt bus incorporates state machine logic for cycling through possible interrupt states. The peripherals are daisy chained beginning and ending with a serial interrupt controller which follows the same state machine logic as the system peripherals. When the serial interrupt controller receives an active interrupt signal, it determines which interrupt signal to provide to the system's interrupt controller based on the interrupt state of the interrupt controller state machine logic. Peripherals on a secondary serial interrupt bus may be daisy chained with peripherals on a primary system interrupt bus through a system interrupt bridge which also includes state machine logic for following the same state diagram as the system peripherals.
摘要翻译：实现串行中断总线协议，其中计算机系统中的任何数量的外围设备可以向系统的中断控制器发出任何预定的中断信号，而不需要针对每个可能的中断的专用引脚。在串行中断总线上实现的每个外设都包含状态机逻辑，用于循环通过可能的中断状态。外设以串联中断控制器为起始和结束，该控制器遵循与系统外设相同的状态机器逻辑。当串行中断控制器接收到一个有效的中断信号时，根据中断控制器状态机逻辑的中断状态确定提供给系统中断控制器的中断信号。辅助串行中断总线上的外设可以通过系统中断桥与主系统中断总线上的外设串联链接，系统中断总线还包括状态机逻辑，用于跟随与系统外设相同的状态图。

4. 发明授权

US5535420A Method and apparatus for interrupt signaling in a computer system 失效
标题翻译：计算机系统中的中断信令的方法和装置
公开(公告)号：US5535420A
公开(公告)日：1996-07-09
申请号：US356131
申请日：1994-12-14
申请人： James Kardach , Sung S. Cho , Nicholas B. Peterson , Thomas R. Lane
发明人： James Kardach , Sung S. Cho , Nicholas B. Peterson , Thomas R. Lane
IPC分类号： G06F13/24
CPC分类号： G06F13/24
摘要： A computer architecture which provides for the dynamic configuration of peripheral interrupts. A global router is implemented for mapping interrupts received over a multiple-line shared interrupt bus to correspond to system standard IRQ interrupt signals for a programable interrupt controller (PIC). The global router may configure interrupts to be both level sensitive and edge-triggered interrupts as well as being sharable among multiple devices. The global router further provides its interrupts to a shared interrupt bus which may receive other system interrupts for propagation to the computer system's PIC. The global router provides a centrally located motherboard resource that provides a totally flexible interrupt configuration scheme.
摘要翻译：提供外设中断的动态配置的计算机体系结构。实现全局路由器，用于映射通过多行共享中断总线接收的中断，以对应于可编程中断控制器（PIC）的系统标准IRQ中断信号。全局路由器可以将中断配置为电平敏感和边沿触发中断，并且可以在多个设备之间共享。全局路由器还将其中断提供给共享中断总线，共享中断总线可能会接收其他系统中断以传播到计算机系统的PIC。全球路由器提供了一个中央位置的主板资源，提供完全灵活的中断配置方案。

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