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51. 发明授权

US4849969A Implementation of smoothing apparatus for an independently clocked network 失效
标题翻译：实现独立时钟网络的平滑设备
公开(公告)号：US4849969A
公开(公告)日：1989-07-18
申请号：US195964
申请日：1988-05-19
申请人： Kadiresan Annamalai
发明人： Kadiresan Annamalai
IPC分类号： H04L7/00 , H04J3/06 , H04L7/04 , H04L12/42 , H04Q11/04
CPC分类号： H04L12/422 , H04J3/0632 , H04L2007/045
摘要： A method and apparatus are disclosed for preserving a minimum or maximum interpacket gap length in an independently clocked data network, typically one following the ANSI-FDDI standard. A smoother is placed downstream of each elastic buffer in the network. The smoother detects the occurrence in an arriving stream of bytes of short preambles, i.e., those having fewer than a threshold number of idle bytes, and inserts some number n.sub.a additional idle bytes into such preambles. Subsequently arriving bytes are delayed by n.sub.a byte clock periods by, in a preferred embodiment, storing them in a FIFO sequence of registers. In order to be available for lengthening other short preambles when they arrive, the smoother also detects the arrival of long preambles, i.e., those having more than the threshold number of idle bytes, and deletes a number n.sub.d idle bytes from such long preambles. Deletion is accomplished in the preferred embodiment by reducing the delay of the stream, which in turn is accomplished by reducing the length of the FIFO sequence of delay registers by n.sub.d registers. Idle bytes which may have been temporarily stored in delay registers which are no longer part of the FIFO sequence are discarded. This reduces the extension of the smoother and makes it available for inserting idle bytes into subsequently arriving short preambles. The method and apparatus can be expanded to provide several extended states at each of several different thresholds. It can also be applied in a network requiring a maximum interpacket gap length by providing a normal state and one or more contracted states.

52. 发明授权

US4779087A Loop transmission system with frame synchronization control 失效
标题翻译：环路传输系统具有帧同步控制
公开(公告)号：US4779087A
公开(公告)日：1988-10-18
申请号：US938193
申请日：1986-12-11
申请人： Haruki Fukuda , Kenshi Tazaki , Masahiro Matsuda , Tomohiki Awazu
发明人： Haruki Fukuda , Kenshi Tazaki , Masahiro Matsuda , Tomohiki Awazu
IPC分类号： H04L7/08 , H04L12/28 , H04L12/42 , H04L7/00 , H04J3/06 , H04L11/16
CPC分类号： H04L12/422
摘要： A loop transmission system with frame synchronization control includes a loop (1) through which information in the form of a sequence of frames is transmitted, a plurality of node units (51, 52, . . . , 5n; 3, 4) inserted at predetermined positions in the loop (1) for receiving and delivering information, and a supervisory device (2) inserted at a predetermined position in the loop (1) for supervising the transmission of information through the loop (1) in association with the node units (51, 52, . . . , 5n; 3, 4). The supervisory device (2) is operable to deliver a frame synchronization cancellation signal. Each of the node units (51, 52, . . . , 5n; 3, 4) is adapted to detect the frame synchronization cancellation signal and cancel the synchronized operation state in bypassing or taking-in of a node and to restore synchronization in the frame next to the synchronization cancelled frame. Therefore, quick restoration of synchronization after bypassing or taking-in of a node is ensured.
摘要翻译： PCT No.PCT / JP86 / 00062 Sec。 371日期1986年12月11日第 102（e）日期1986年12月11日PCT申请1986年2月13日PCT公布。公开号WO86 / 05053 日期：1986年8月28日。具有帧同步控制的环路传输系统包括循环（1），通过该循环（1）发送以帧序列形式的信息，多个节点单元（51,52 ...，5n ; 3，4）插入到环路（1）中用于接收和传送信息的预定位置;以及监控装置（2），其插入在环路（1）中的预定位置，用于通过环路（1）监视信息的传输）与节点单元（51,52，...，5n; 3,4）相关联。监控装置（2）可操作以传递帧同步消除信号。每个节点单元（51,52，...，5n; 3,4）适于检测帧同步消除信号，并且在旁路或接收节点时取消同步操作状态，并且恢复在框架旁边的同步取消帧。因此，可以确保在旁路或接入节点后快速恢复同步。

53. 发明授权

US4769813A Ring communication system 失效
标题翻译：环通信系统
公开(公告)号：US4769813A
公开(公告)日：1988-09-06
申请号：US122299
申请日：1987-11-18
申请人： Joseph M. Lenart
发明人： Joseph M. Lenart
IPC分类号： H04L12/42 , H04L12/43 , H04J3/02 , H04Q11/04
CPC分类号： H04L12/43 , H04L12/422
摘要： Communication systems of a plurality of switching nodes connected in a closed ring. A switching stage at each node transmits words of data from node-to-node in a time-division multiplexed data stream. Data can be inserted onto the ring by each switching stage, and data addressed to a switching stage is removed from the ring by that switching stage. Data words are loaded into input registers at each switching stage on the leading edge of a clock pulse, decoding occurs within each switching stage during the clock pulse, and the data words are placed in the proper output registers of each switching stage in response to the termination of the clock pulse.
摘要翻译：以闭环连接的多个交换节点的通信系统。每个节点的切换阶段在时分多路复用数据流中从节点到节点传输数据字。可以通过每个切换级将数据插入到环上，并且通过该切换级将寻址到切换级的数据从环中移除。数据字被加载到时钟脉冲前沿的每个切换阶段的输入寄存器中，在时钟脉冲期间在每个切换级内进行解码，并且数据字被响应于每个切换级的每个切换级的适当的输出寄存器终止时钟脉冲。

54. 发明授权

US4417242A Method for connecting or disconnecting selected stations in a ring communication system, and ring communication system including selectively connectable stations 失效
标题翻译：用于在环形通信系统中连接或断开所选择的站的方法，以及包括可选择地连接的站的环通信系统
公开(公告)号：US4417242A
公开(公告)日：1983-11-22
申请号：US353746
申请日：1982-03-01
申请人： Urs Bapst , Heinz Keller , Heinrich Meyr , Hans R. Muller
发明人： Urs Bapst , Heinz Keller , Heinrich Meyr , Hans R. Muller
IPC分类号： H03L7/10 , H04L7/00 , H04L12/42 , H04Q9/00 , H04J3/08 , H04L7/08
CPC分类号： H04L12/422 , H04L7/0083
摘要： In a ring communication system comprising selectively connectable data stations, each station has connecting circuitry including a phase-locked loop arrangement (111) which is frozen at its current frequency and phase in response to a signal interruption caused by a station insertion or removal operation. Control logic (113) generates a freeze control signal in dependence of the signal energy status on input lines (75). This control signal activates gates (149, 151) and switches (155, 157) to interrupt change control signals of the phase-locked loop circuitry and to keep an oscillator control voltage at a given value. The control logic also provides an auxiliary data signal during the freeze interval which is applied to the ring to keep stations downstream in synchronism. By this method and arrangement, undesired reactions and excursions of the phase-locked loop circuitry in response to a signal energy outage are prevented, and synchronization can be rapidly regained after station insertion or removal.
摘要翻译：在包括可选择地连接的数据站的环形通信系统中，每个站具有连接电路，该连接电路包括响应于由站插入或移除操作引起的信号中断而冻结在其当前频率和相位的锁相环装置（111）。控制逻辑（113）根据输入线（75）上的信号能量状态产生冻结控制信号。该控制信号激活门（149,151）和开关（155,157）以中断锁相环电路的改变控制信号，并将振荡器控制电压保持在给定值。控制逻辑还在冻结间隔期间提供辅助数据信号，该信号被施加到环上，以使站下游同步。通过该方法和布置，防止响应于信号能量中断的锁相环电路的不期望的反应和偏移，并且可以在站插入或移除之后快速恢复同步。

55. 发明授权

US4284843A Repeating station for use in digital data communications link 失效
标题翻译：重复站用于数字数据通信链路
公开(公告)号：US4284843A
公开(公告)日：1981-08-18
申请号：US37834
申请日：1979-05-10
申请人： Emery A. White
发明人： Emery A. White
IPC分类号： H04L1/00 , H04L7/033 , H04L7/04 , H04L7/06 , H04L12/42 , H04L25/24 , H04L25/49 , H04L25/52 , H04L25/02
CPC分类号： H04L12/422 , H04L1/0083 , H04L25/242 , H04L25/4925 , H04L7/033 , H04L2007/045 , H04L7/046 , H04L7/06
摘要： A repeater for use in a data communications link, particularly of the type to provide the exchange of process control information with external controlled equipment, includes a detector for detecting incoming data presented on the data communications link. Through the use of a free running internal clock, the data is retimed, reconstructed through the use of a modulator and presented to a transmitter for placement back on the data link. The repeater further provides data and clock signals to the external controlled equipment and receives signals from that equipment which serve, by way of logic circuitry within the repeater, to effect the modification of the data received by the repeater to thus enable the controlled equipment to communicate with other elements connected to the link.
摘要翻译：用于数据通信链路的转发器，特别是提供与外部受控设备交换过程控制信息的类型的中继器包括用于检测在数据通信链路上呈现的输入数据的检测器。通过使用自由运行的内部时钟，数据被重新定时，通过使用调制器重建，并呈现给发送器以放置在数据链路上。中继器还向外部受控设备提供数据和时钟信号，并从该设备接收信号，该信号通过中继器内的逻辑电路来实现对中继器接收的数据的修改，从而使被控设备能够通信其他元素连接到链接。

56. 发明授权

US4071706A Data packets distribution loop 失效
标题翻译：数据包分发循环
公开(公告)号：US4071706A
公开(公告)日：1978-01-31
申请号：US722583
申请日：1976-09-13
申请人： Charles Stewart Warren
发明人： Charles Stewart Warren
IPC分类号： H04J3/06 , G06F13/00 , G06F13/42 , G06F15/16 , G06F15/173 , H04L7/00 , H04L12/42
CPC分类号： G06F13/4247 , H04L12/422
摘要： A data communications or distribution loop has a plurality of computer stations each of which introduces a delay while it examines the header of each circulating packet or block of data. An elastic synchronizing buffer, including a random-access memory, is included in the loop to introduce a delay which, when added to the delays introduced by the stations, equals the period of a packet. The delay introduced by the buffer is automatically adjusted as stations are added to, or removed from, the loop.
摘要翻译：数据通信或分发回路具有多个计算机站，每个计算机站在检查每个循环分组或数据块的头部时引入延迟。包括随机存取存储器的弹性同步缓冲器被包括在循环中以引入一个延迟，该延迟当被添加到由站引入的延迟时等于分组的周期。缓冲区引入的延迟是自动调整的，因为站被添加到循环中或从循环中移除。

57. 发明授权

US12122309B2 Power and data center (PDC) for automotive applications 有权
公开(公告)号：US12122309B2
公开(公告)日：2024-10-22
申请号：US17804289
申请日：2022-05-26
申请人： Aptiv Technologies AG
发明人： Lee Bauer , Martin Bornemann , Christian Schäfer
IPC分类号： B60R16/03 , G05D1/00 , G06F18/25 , G06V20/56 , H04L12/42 , H04L67/12
CPC分类号： B60R16/03 , G05D1/0088 , G06F18/251 , G06V20/56 , H04L12/422 , H04L67/12
摘要： A power and data center (PDC) can serve as a combined data concentrator and power distributor that delivers scalable and affordable network/power redundancy into an automotive electrical/electronic architecture (E/EA) that supports partially or fully autonomous vehicles. In some embodiments, a vehicle that includes the smart E/EA is divided into zones, where each zone includes one or more PDCs and one or more sensors, actuators, controllers, loudspeakers or other devices that are coupled to and powered by their zone PDC(s). Each PDC collects and processes (or passes through) raw or pre-processed sensor data from the one or more sensors in its zone. The sensors provide their data to the PDC by way of cost efficient, short-range data links. In some embodiments, one or more actuators in each zone are coupled to their respective zone PDC, and receive their control data from the PDC over a high-speed data bus or data link.

58. 发明授权

US10063465B2 Network system and relay device 有权
公开(公告)号：US10063465B2
公开(公告)日：2018-08-28
申请号：US15033670
申请日：2014-09-05
申请人： Hitachi, Ltd.
发明人： Tatsuya Maruyama , Tsutomu Yamada , Chikashi Komatsu , Mitsuyasu Kido , Shouji Yoshida
IPC分类号： H04L12/721 , H04L12/437 , H04L12/42 , H04L12/703 , H04L12/833
CPC分类号： H04L45/34 , H04L12/422 , H04L12/437 , H04L45/28 , H04L47/31
摘要： An object of the present invention is to provide a network system or the like in which the construction cost of a network for a plurality of control systems is suppressed which is excellent in resistance to a network failure. In order to solve the problems, according to the present invention, there is provided a network system including a plurality of communication devices that are disposed in a plurality of bases, and are grouped into predetermined control systems for each of the devices which transmit and receive packets to and from each other so as to monitor or control target equipment, and a plurality of relay devices each of which includes a plurality of communication ports and transmits a packet transmitted by the communication device to another communication device, in which a plurality of communication devices disposed in each base are connected in parallel between the two relay devices, the relay devices disposed in different bases are connected to each other in a ring shape via a network, and a plurality of communication devices disposed in at least one base include communication devices belonging to different control systems.

59. 发明申请

US20180102944A1 SYSTEMS AND METHODS FOR AVOIDING INADVERTENT LOOPS IN A LAYER 2 SWITCHED NETWORK 审中-公开
公开(公告)号：US20180102944A1
公开(公告)日：2018-04-12
申请号：US15356969
申请日：2016-11-21
申请人： Ciena Corporation
发明人： Rajneesh MISHRA , Vikas TRIVEDI , Prashant VASHISHT
IPC分类号： H04L12/24 , H04L12/721 , H04L12/42
CPC分类号： H04L12/422 , H04L12/462 , H04L43/0829 , H04L45/66
摘要： Loop prevention systems and methods implemented in a switch to prevent loops in a Layer 2 packet switched network based on Media Access Control (MAC) movement in a forwarding database include enabling class based MAC learning on one or more ports with all of the one or more ports initially in a higher priority learning class; disabling MAC movements from the higher priority learning class to a lower priority learning class and disabling MAC movements in the lower priority learning class such that the switch discards frames attempting to perform MAC movement to ports which are in the lower priority learning class; and managing a priority for specific Source MAC addresses between a source port belonging to the higher priority learning class and the lower priority learning class based on detected loops for the specific Source MAC addresses.

60. 发明授权

US09407454B2 Anti-starvation and bounce-reduction mechanism for a two-dimensional bufferless interconnect 有权
公开(公告)号：US09407454B2
公开(公告)日：2016-08-02
申请号：US14605988
申请日：2015-01-26
申请人： Intel Corporation
发明人： Andres Mejia
IPC分类号： H04L12/43 , G06F15/78 , H04J3/08 , H04L12/42 , H04L12/741
CPC分类号： H04L12/43 , G06F15/7825 , H04J3/085 , H04L12/422 , H04L45/74 , H04L2012/421
摘要： A slot reservation method is disclosed. The slot reservation method generates slot reservations in two dimensions to address starvation and to reduce bounce of messages transmitted through an interconnect. An interconnect implemented using the slot reservation method is capable of being scaled to larger network-on-chip implementations.

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