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51. 发明申请

US20170085821A1 DUAL SAMPLE-AND-HOLD CIRCUIT WITH RESISTIVE GAIN 审中-公开
公开(公告)号：US20170085821A1
公开(公告)日：2017-03-23
申请号：US15356500
申请日：2016-11-18
申请人： Sony Semiconductor Solutions Corporation
发明人： Noam Eshel , Golan Zeituni
IPC分类号： H04N5/378 , G11C27/02
CPC分类号： H04N5/378 , G11C27/024 , H02M11/00 , H03M3/30 , H04N5/374
摘要： An image processing circuit includes a first dual sample-and-hold circuit that samples a first data and a second data from a first pixel, a second dual sample-and-hold circuit that samples a third data and a fourth data from a second pixel, a voltage-to-current circuit including a resistor and a current source, that receives the first data and the second data to output a first difference data, and that receives the third data and the fourth data to output a second difference data; and an analog-to-digital converter that converts the first and second difference data from an analog form to a digital form.

52. 发明授权

US09589591B2 Signal processing device, signal processing method, and computer program 有权
标题翻译：信号处理装置，信号处理方法和计算机程序
公开(公告)号：US09589591B2
公开(公告)日：2017-03-07
申请号：US14534592
申请日：2014-11-06
申请人： SONY CORPORATION
发明人： Yuuki Matsumura , Shiro Suzuki
IPC分类号： G11B20/10 , H03M7/30 , H03M3/00 , G11B20/00
CPC分类号： G11B20/10037 , G11B20/10027 , G11B2020/00065 , H03M3/30 , H03M7/3004 , H03M7/3013 , H03M7/3031 , H03M7/3044 , H03M7/3048
摘要： There is provided a signal processing device including a signal coincidence detection portion which detects samples, in which values based on a number of times of appearance of bits coincide with each other over a plurality of samples within a pre-set period, between a first modulated signal obtained by delaying an input signal obtained by ΣΔ modulation and a second modulated signal obtained by subjecting the input signal to the ΣΔ modulation again, a signal changeover portion which switches between the first modulated signal and the second modulated signal for outputting, and a switching control portion which controls the switching between the first modulated signal and the second modulated signal by the signal changeover portion in the samples in which the values based on the number of times of the appearance coincide with each other obtained by the signal coincidence detection portion.
摘要翻译：提供了一种信号处理装置，包括信号一致检测部分，其检测样本，其中基于比特出现次数的值在预设时段内在多个样本之间彼此重合的值在第一调制通过延迟通过ΣΔ调制获得的输入信号而获得的信号和通过再次对输入信号进行ΣΔ调制而获得的第二调制信号，在第一调制信号和第二调制信号之间切换以输出的信号切换部分，以及切换控制部分，其通过由信号重合检测部分获得的基于出现次数彼此重合的值的样本中的信号切换部分来控制第一调制信号和第二调制信号之间的切换。

53. 发明申请

US20170041019A1 DELTA SIGMA MODULATOR WITH DYNAMIC ERROR CANCELLATION 有权
标题翻译：具有动态错误消除的DELTA SIGMA调制器
公开(公告)号：US20170041019A1
公开(公告)日：2017-02-09
申请号：US15226436
申请日：2016-08-02
申请人： Texas Instruments Incorporated
发明人： Eeshan MIGLANI , Karthikeyan GUNASEKARAN , Santhosh Kumar GOWDHAMAN , Shagun DUSAD
IPC分类号： H03M3/00
CPC分类号： H03M3/50 , H03M1/00 , H03M1/001 , H03M1/0626 , H03M1/0665 , H03M1/12 , H03M1/747 , H03M3/30 , H03M3/34 , H03M3/422 , H03M3/458 , H03M7/3004
摘要： The disclosure provides a delta sigma modulator that includes a first input port and a second input port. These ports receive a differential input signal. A DAC is coupled to the first input port and the second input port, and receives a differential feedback signal and a plurality of selection signals. A loop filter generates a differential filtered signal in response to a differential error signal. The differential error signal is proportional to a difference in the differential input signal and the differential feedback signal. A quantizer generates a quantized output signal in response to the differential filtered signal. A modified DWA block coupled between the quantizer and the DAC, generates the plurality of selection signals in response to a chop clock, a regular clock, the quantized output signal and a plurality of selection index signals. A selection index signal is dependent on previously generated plurality of selection signals.
摘要翻译：本公开提供了包括第一输入端口和第二输入端口的Δ-Σ调制器。这些端口接收差分输入信号。 DAC耦合到第一输入端口和第二输入端口，并且接收差分反馈信号和多个选择信号。环路滤波器响应差分误差信号产生差分滤波信号。差分误差信号与差分输入信号和差分反馈信号的差成比例。量化器响应于差分滤波信号产生量化的输出信号。耦合在量化器和DAC之间的经修改的DWA块响应于斩波时钟，规则时钟，量化的输出信号和多个选择索引信号产生多个选择信号。选择索引信号取决于先前生成的多个选择信号。

54. 发明申请

US20170018593A1 SYSTEM, METHOD, AND APPARATUS FOR GENERATING A RAMP SIGNAL WITH A CHANGING SLOPE 审中-公开
标题翻译：用于产生具有变化斜率的RAMP信号的系统，方法和装置
公开(公告)号：US20170018593A1
公开(公告)日：2017-01-19
申请号：US15211936
申请日：2016-07-15
申请人： Cista System Corp.
发明人： Wenhao Qiao , Guangbin Zhang , Dennis Tunglin Lee
IPC分类号： H01L27/146 , H03M3/00 , H03L7/197 , H03L7/08 , H03K4/08
CPC分类号： H01L27/14643 , H01L27/14609 , H03K4/08 , H03K6/04 , H03L7/1976 , H03M1/56 , H03M3/30
摘要： A device for generating a ramp signal with a changing slope is disclosed. The device may comprise a processor configured to generate a variable signal. The device may also comprise a phase-locked loop (PLL) circuit configured to receive the variable signal and a reference clock signal, generate a changing ramp clock signal based on the variable signal and the reference clock signal, and output the generated changing ramp clock signal as an input of an analog-to-digital-converter (ADC) circuit.
摘要翻译：公开了一种用于产生斜率变化的斜坡信号的装置。该设备可以包括被配置为生成可变信号的处理器。该装置还可以包括配置为接收可变信号和参考时钟信号的锁相环（PLL）电路，基于可变信号和参考时钟信号产生改变的斜坡时钟信号，并输出所产生的变化斜坡时钟信号作为模数转换器（ADC）电路的输入。

55. 发明申请

US20160365950A1 DIRECT DIGITAL SYNTHESIS OF SIGNALS USING MAXIMUM LIKELIHOOD BIT-STREAM ENCODING 有权
标题翻译：使用最大似然比特流编码的信号的直接数字合成
公开(公告)号：US20160365950A1
公开(公告)日：2016-12-15
申请号：US15187651
申请日：2016-06-20
申请人： Intel Corporation
发明人： Kameran Azadet
IPC分类号： H04L1/00 , H04L25/49 , H04B1/04
CPC分类号： G06F9/3001 , G06F5/01 , G06F9/30036 , G06F17/15 , H03F1/0288 , H03F1/3241 , H03F1/3258 , H03F3/189 , H03F3/24 , H03F2200/336 , H03F2201/3209 , H03F2201/3212 , H03F2201/3224 , H03F2201/3233 , H03H17/06 , H03M3/30 , H04B1/0003 , H04B1/0475 , H04B1/62 , H04B2001/0408 , H04L1/0054 , H04L25/02 , H04L25/03 , H04L25/03178 , H04L25/03216 , H04L25/4917 , H04L27/2334
摘要： Methods and apparatus are provided for direct synthesis of RF signals using maximum likelihood sequence estimation. An RF digital RF input signal is synthesized by performing maximum likelihood sequence estimation on the digital RF input signal to produce a digital stream, such that after filtering by a prototype filter the produced digital stream produces a substantially minimum error. The substantially minimum error comprises a difference between a digital output of the prototype filter and the digital RF input signal. The digital stream is substantially equal to the input digital RF signal. The digital stream can be applied to an analog restitution filter, and the output of the analog restitution filter comprises an analog RF signal that approximates the digital RF input signal.
摘要翻译：提供了使用最大似然序列估计直接合成RF信号的方法和装置。通过对数字RF输入信号执行最大似然序列估计来合成RF数字RF输入信号以产生数字流，使得在通过原型滤波器滤波之后，所产生的数字流产生基本上最小的误差。基本上最小的误差包括原型滤波器的数字输出和数字RF输入信号之间的差异。数字流基本上等于输入的数字RF信号。数字流可以应用于模拟恢复滤波器，并且模拟恢复滤波器的输出包括近似数字RF输入信号的模拟RF信号。

56. 发明授权

US09520895B2 Low power analog to digital converter 有权
公开(公告)号：US09520895B2
公开(公告)日：2016-12-13
申请号：US14705805
申请日：2015-05-06
申请人： Intel Corporation
发明人： Takao Oshita , George L. Geannopoulos , David E. Duarte , J Keith Hodgson , James S. Ayers , Avner Kornfeld , Jonathan P. Douglas
IPC分类号： H03M3/00 , H03M1/12 , H03M1/00 , H03M1/80
CPC分类号： H03M3/458 , H03M1/00 , H03M1/002 , H03M1/12 , H03M1/123 , H03M1/1245 , H03M1/804 , H03M3/30 , H03M3/32 , H03M3/34
摘要： Described is an analog to digital converter (ADC) which comprises: a sigma-delta modulator to receive an analog signal, the sigma-delta modulator operable to perform chopping to cancel common-mode noise; and one or more counters coupled to the sigma-delta modulator to generate a digital code representative of the analog signal.

57. 发明申请

US20160241256A1 SIGNAL MODULATION CIRCUIT 审中-公开
标题翻译：信号调制电路
公开(公告)号：US20160241256A1
公开(公告)日：2016-08-18
申请号：US15137129
申请日：2016-04-25
申请人： Onkyo Corporation
发明人： Yoshinori NAKANISHI , Tsuyoshi KAWAGUCHI , Mamoru SEKIYA
IPC分类号： H03M3/00
CPC分类号： H03M3/37 , G11B20/10009 , G11B2020/00065 , H03M3/30 , H03M3/346 , H03M3/348 , H03M3/424 , H04R3/00
摘要： Provided is a modulation circuit that can correct an output state in real time and reliably modulate an input signal to output the modulated signal. The signal modulation circuit includes a subtractor, an integrator, a chopper circuit, a frequency divider, and a D-type flip-flop. A delay circuit of a sigma delta modulation circuit is not provided to a feedback circuit, and a signal is delayed and quantized in the D-type flip-flop. The chopper circuit inserts a zero level at timing synchronized with a clock signal, so that pulse density modulation is performed.
摘要翻译：提供了可以实时校正输出状态并可靠地调制输入信号以输出调制信号的调制电路。信号调制电路包括减法器，积分器，斩波电路，分频器和D型触发器。 Σ-Δ调制电路的延迟电路不提供给反馈电路，并且在D型触发器中延迟和量化信号。斩波电路在与时钟信号同步的定时插入零电平，从而执行脉冲密度调制。

58. 发明申请

US20160233879A1 LOW POWER ANALOG TO DIGITAL CONVERTER 审中-公开
标题翻译：低功耗模拟到数字转换器
公开(公告)号：US20160233879A1
公开(公告)日：2016-08-11
申请号：US14705805
申请日：2015-05-06
申请人： Intel Corporation
发明人： Takao Oshita , George L. Geannopoulos , David E. Duarte , J. Keith Hodgson , James S. Ayers , Avner Kornfeld , Jonathan P. Douglas
IPC分类号： H03M3/00 , H03M1/00 , H03M1/12
CPC分类号： H03M3/458 , H03M1/00 , H03M1/002 , H03M1/12 , H03M1/123 , H03M1/1245 , H03M1/804 , H03M3/30 , H03M3/32 , H03M3/34
摘要： Described is an analog to digital converter (ADC) which comprises: a sigma-delta modulator to receive an analog signal, the sigma-delta modulator operable to perform chopping to cancel common-mode noise; and one or more counters coupled to the sigma-delta modulator to generate a digital code representative of the analog signal.
摘要翻译：描述了一种模数转换器（ADC），其包括：用于接收模拟信号的Σ-Δ调制器，可用于执行斩波以消除共模噪声的Σ-Δ调制器; 以及耦合到Σ-Δ调制器的一个或多个计数器以产生表示模拟信号的数字代码。

59. 发明申请

US20160231156A1 RESONANCE CIRCUIT USED FOR MEASUREMENT DEVICE AND MEASUREMENT DEVICE 有权
标题翻译：用于测量装置和测量装置的谐振电路
公开(公告)号：US20160231156A1
公开(公告)日：2016-08-11
申请号：US15015262
申请日：2016-02-04
申请人： Yokogawa Electric Corporation
发明人： Yuki IKADAI , Masami WADA
IPC分类号： G01F1/84 , H03M3/00 , H03K5/02 , G06G7/16
CPC分类号： G01F1/8422 , G01F1/8431 , G01F1/8436 , G01N9/002 , G01N2009/006 , G06G7/16 , H03K5/02 , H03M3/30
摘要： A resonance circuit is configured to receive a pulse density signal obtained by ΔΣ-modulating an analog displacement signal by a ΔΣ modulator and a multi-bit signal obtained from the pulse density signal and to generate an excitation signal based on the pulse density signal and the multi-bit signal. The resonance circuit includes an amplification factor controller configured to set an amplification factor depending on a vibration signal obtained from the multi-bit signal, a multiplier configured to amplify a level of the pulse density signal by the amplification factor, and a circuit group configured to generate the excitation signal based on a pulse density signal obtained by further ΔΣ-modulating an output of the multiplier. The amplification factor controller is configured to set the amplification factor using a proportional control and an integral control based a difference between an amplitude signal obtained from the vibration signal and a target amplitude value.
摘要翻译：谐振电路被配置为接收通过ΔΣ调制器对模拟位移信号进行ΔΣ调制而获得的脉冲密度信号和从脉冲密度信号获得的多位信号，并且基于脉冲密度信号和多位信号。谐振电路包括：放大系数控制器，被配置为根据从多位信号获得的振动信号设定放大系数;被配置为通过放大系数放大脉冲密度信号的电平的乘法器和被配置为基于通过进一步ΔΣ调制乘法器的输出而获得的脉冲密度信号来产生激励信号。放大系数控制器被配置为使用基于从振动信号获得的振幅信号与目标振幅值之间的差异的比例控制和积分控制来设置放大系数。

60. 发明授权

US09397691B2 Mostly-digital open-loop ring oscillator delta-sigma ADC and methods for conversion 有权
标题翻译：大多数数字开环环形振荡器delta-sigma ADC和转换方法
公开(公告)号：US09397691B2
公开(公告)日：2016-07-19
申请号：US14302626
申请日：2014-06-12
申请人： The Regents of the University of California
发明人： Ian Galton , Gerry Taylor
IPC分类号： H03M3/00
CPC分类号： H03M3/386 , H03M3/30 , H03M3/38 , H03M3/388 , H03M3/412
摘要： A continuous-time delta-sigma modulator for analog-to-digital conversion includes a pair of pseudo-differential signal paths including a pair of pseudo-differential signal paths including current-controlled ring oscillators as the load of open-loop common-source amplifiers that are driven by an analog input signal. The signal path produces digital values by sampling the open-loop current-controlled ring oscillators. A calibration circuit measures nonlinear distortion coefficients in a replica of the signal path. A nonlinearity corrector corrects digital values based upon the nonlinear distortion coefficients.
摘要翻译：用于模数转换的连续时间Δ-Σ调制器包括一对伪差分信号路径，其包括一对伪差分信号路径，包括作为开环共源极放大器的负载的电流控制环形振荡器由模拟输入信号驱动。信号路径通过采样开环电流控制的环形振荡器产生数字值。校准电路测量信号路径副本中的非线性失真系数。非线性校正器基于非线性失真系数校正数字值。

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