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1. 发明申请

US20170041019A1 DELTA SIGMA MODULATOR WITH DYNAMIC ERROR CANCELLATION 有权
标题翻译：具有动态错误消除的DELTA SIGMA调制器
公开(公告)号：US20170041019A1
公开(公告)日：2017-02-09
申请号：US15226436
申请日：2016-08-02
申请人： Texas Instruments Incorporated
发明人： Eeshan MIGLANI , Karthikeyan GUNASEKARAN , Santhosh Kumar GOWDHAMAN , Shagun DUSAD
IPC分类号： H03M3/00
CPC分类号： H03M3/50 , H03M1/00 , H03M1/001 , H03M1/0626 , H03M1/0665 , H03M1/12 , H03M1/747 , H03M3/30 , H03M3/34 , H03M3/422 , H03M3/458 , H03M7/3004
摘要： The disclosure provides a delta sigma modulator that includes a first input port and a second input port. These ports receive a differential input signal. A DAC is coupled to the first input port and the second input port, and receives a differential feedback signal and a plurality of selection signals. A loop filter generates a differential filtered signal in response to a differential error signal. The differential error signal is proportional to a difference in the differential input signal and the differential feedback signal. A quantizer generates a quantized output signal in response to the differential filtered signal. A modified DWA block coupled between the quantizer and the DAC, generates the plurality of selection signals in response to a chop clock, a regular clock, the quantized output signal and a plurality of selection index signals. A selection index signal is dependent on previously generated plurality of selection signals.
摘要翻译：本公开提供了包括第一输入端口和第二输入端口的Δ-Σ调制器。这些端口接收差分输入信号。 DAC耦合到第一输入端口和第二输入端口，并且接收差分反馈信号和多个选择信号。环路滤波器响应差分误差信号产生差分滤波信号。差分误差信号与差分输入信号和差分反馈信号的差成比例。量化器响应于差分滤波信号产生量化的输出信号。耦合在量化器和DAC之间的经修改的DWA块响应于斩波时钟，规则时钟，量化的输出信号和多个选择索引信号产生多个选择信号。选择索引信号取决于先前生成的多个选择信号。

2. 发明公开

US20240146314A1 CHARGE PUMP SPUR CORRECTION 审中-公开
公开(公告)号：US20240146314A1
公开(公告)日：2024-05-02
申请号：US17977834
申请日：2022-10-31
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Karthikeyan GUNASEKARAN , Jagannathan VENKATARAMAN
IPC分类号： H03L7/089 , H03L7/099
CPC分类号： H03L7/0895 , H03L7/0992
摘要： In an example, a system includes a phase frequency detector (PFD) coupled to a charge pump, and a loop filter coupled to the charge pump. The system also includes a voltage controlled oscillator (VCO) coupled to the loop filter. The system includes a fast Fourier transform (FFT) engine coupled to an output of the VCO, the FFT engine configured to estimate a phase and a magnitude of reference spurs of an input reference signal. The system includes spur correction circuitry coupled to an input of the VCO, the spur correction circuitry configured to correct for the reference spurs of the input reference signal based at least in part on the phase and magnitude of the reference spurs.

3. 发明申请

US20220239304A1 FDAC/2 SPUR ESTIMATION AND CORRECTION 有权
公开(公告)号：US20220239304A1
公开(公告)日：2022-07-28
申请号：US17538746
申请日：2021-11-30
申请人： Texas Instruments Incorporated
发明人： Karthikeyan GUNASEKARAN , Snehasish ROYCHOWDHURY , Rakesh MANJUNATH , Aswath V S , Sthanunathan RAMAKRISHNAN , Sarma Sudareswara GUNTURI , Rahul SHARMA , Jagannathan VENKATARAMAN , Nagarajan VISWANATHAN
IPC分类号： H03M1/10 , H03M1/66
摘要： A spur correction system for a transmit chain having an interleaving multiplexer. In some embodiments, the spur correction system includes a spur sense chain, a correction controller, and a Q path corrector. The interleaving multiplexer combines signals from multiple bands in response to a clock signal. The spur sense chain estimates an error that is in phase with the clock signal (an I-phase error) and an error that is a derivative of the clock signal (a Q-phase error). The correction controller compensates for the estimated I-phase error by injecting an I-phase correction signal into the transmit chain. The Q path corrector compensates for the estimated Q-phase error by selectively connecting one or more capacitors within the interleaving multiplexer.

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