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51. 发明授权

US09601475B2 Workpiece with semiconductor chips, semiconductor device and method for producing a workpiece with semiconductor chips 有权
公开(公告)号：US09601475B2
公开(公告)日：2017-03-21
申请号：US15041127
申请日：2016-02-11
申请人： Intel Deutschland GmbH
发明人： Markus Brunnbauer , Thorsten Meyer , Stephan Bradl , Ralf Plieninger , Jens Pohl , Klaus Pressel , Recai Sezi
IPC分类号： H01L21/301 , H01L25/00 , H01L21/56 , H01L23/31 , H01L23/538 , H01L23/552 , H01L23/60 , H01L23/00 , H01L23/48 , H01L21/48
CPC分类号： H01L25/50 , H01L21/4853 , H01L21/486 , H01L21/561 , H01L21/565 , H01L21/568 , H01L23/3128 , H01L23/48 , H01L23/5389 , H01L23/552 , H01L23/60 , H01L24/19 , H01L24/96 , H01L24/97 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/20 , H01L2224/97 , H01L2924/01006 , H01L2924/01015 , H01L2924/01033 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/1617 , H01L2924/181 , H01L2924/19043 , H01L2924/3025 , H01L2224/82 , H01L2924/00
摘要： A workpiece has at least two semiconductor chips, each semiconductor chip having a first main surface, which is at least partially exposed, and a second main surface. The workpiece also comprises an electrically conducting layer, arranged on the at least two semiconductor chips, the electrically conducting layer being arranged at least on regions of the second main surface, and a molding compound, arranged on the electrically conducting layer.

52. 发明授权

US09601444B2 Cable mounted modularized signal conditioning apparatus system 有权
公开(公告)号：US09601444B2
公开(公告)日：2017-03-21
申请号：US14317248
申请日：2014-06-27
申请人： Tektronix, Inc.
发明人： Kei-Wean C. Yang
IPC分类号： H01L23/60 , H01P3/06
CPC分类号： H01L23/60 , H01L2924/0002 , H01P3/06 , Y10T29/49123 , H01L2924/00
摘要： A modularized signal conditioning apparatus system includes at least two slots formed in a coaxial cable. The slots are spaced apart so as to not reduce the measuring performance of the coaxial cable. Slots may be at least 40 mills from one another. In an ESD embodiment, within each slot is an ESD protection component, such as a pair of Shottky diodes coupled between the ground shell and the center conductor of the coaxial cable. Methods of producing modularized signal conditioning apparatus system are also described.

53. 发明授权

US09601335B2 Trench formation for dielectric filled cut region 有权
公开(公告)号：US09601335B2
公开(公告)日：2017-03-21
申请号：US15282836
申请日：2016-09-30
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , GLOBALFOUNDRIES, INC.
发明人： Andrew M. Greene , Ryan O. Jung , Ruilong Xie , Peng Xu
IPC分类号： H01L21/28 , H01L23/60 , H01L21/84 , H01L21/8238 , H01L29/423 , H01L27/092 , H01L29/08 , H01L29/06 , H01L27/12
CPC分类号： H01L21/76224 , H01L21/0217 , H01L21/28114 , H01L21/28123 , H01L21/32139 , H01L21/823437 , H01L21/823481 , H01L21/823814 , H01L21/823821 , H01L23/60 , H01L27/088 , H01L27/0924 , H01L27/1211 , H01L29/0649 , H01L29/0653 , H01L29/0847 , H01L29/42368 , H01L29/42376 , H01L29/66545 , H01L29/6656 , H01L29/66628 , H01L29/78
摘要： A method for forming a gate cut region includes forming a tapered profile gate line trench through a hard mask, a dummy layer and a dummy dielectric formed on a substrate, forming a dummy gate dielectric and a dummy gate conductor in the trench and planarizing a top surface to reach the hard mask. The dummy gate conductor is patterned to form a cut trench in a cut region. The dummy gate conductor is recessed, and the cut trench is filled with a first dielectric material. The dummy layer is removed and spacers are formed. A gate line is opened up and the dummy gate conductor is removed from the gate line trench. A gate dielectric and conductor are deposited, and a gate cap layer provides a second dielectric that is coupled to the first dielectric material in the cut trench to form a cut last structure.

54. 发明申请

US20170077086A1 Electrostatic Discharge Protection Element 审中-公开
标题翻译：静电放电保护元件
公开(公告)号：US20170077086A1
公开(公告)日：2017-03-16
申请号：US15065523
申请日：2016-03-09
申请人： Realtek Semiconductor Corp.
发明人： Tay-Her TSAUR , Cheng-Cheng YEN
IPC分类号： H01L27/02 , H01L23/50 , H01L23/60
CPC分类号： H01L23/50 , H01L23/60 , H01L27/0288
摘要： An electrostatic discharge protection element is provided, which leads out the electrostatic discharge current between an internal circuit and an input/output terminal in the event of electrostatic discharge. The electrostatic discharge protection element includes an I/O pad, conductor, and a gap structure. The I/O pad is connected between the I/O terminal and the internal circuit, and the conductor is connected to a ground terminal. The gap structure is disposed between the I/O pad and the conductor, which is configured to establish a path from the I/O pad to the conductor connected to the ground terminal for conducting the electrostatic discharge current.
摘要翻译：提供一种静电放电保护元件，其在静电放电的情况下引起内部电路和输入/输出端子之间的静电放电电流。静电放电保护元件包括I / O焊盘，导体和间隙结构。 I / O焊盘连接在I / O端子和内部电路之间，导体连接到接地端子。间隙结构设置在I / O焊盘和导体之间，其被配置为建立从I / O焊盘到连接到接地端子的导体的路径，用于传导静电放电电流。

55. 发明授权

US09583447B2 EMI shielding method of semiconductor packages 有权
标题翻译：半导体封装的EMI屏蔽方法
公开(公告)号：US09583447B2
公开(公告)日：2017-02-28
申请号：US14915321
申请日：2015-04-15
申请人： Genesem Inc.
发明人： Bok-Woo Han , Hee-Dong Lee
IPC分类号： H01L21/00 , H01L23/552 , H01L23/60 , H01L21/56 , H01L23/28
CPC分类号： H01L23/552 , H01L21/56 , H01L23/28 , H01L23/60 , H01L2924/0002 , H01L2924/00
摘要： Disclosed is an EMI shielding method of semiconductor packages, including a tape attaching step of attaching an edge of a tape to a lower side of a frame to dispose the tape inside an inner circumferential side of the frame, a tape cutting step of forming holes through the tape at regular intervals, a semiconductor package fastening step of disposing edges of lower sides of the semiconductor packages on an upper side of the tape so that bumps, formed on the lower sides of the semiconductor packages, are inserted into the holes in the tape to thus fasten the semiconductor packages at regular intervals to the upper side of the tape, and a coating step of performing a coating operation over the tape to form a coat on the semiconductor packages and the upper side of the tape.
摘要翻译：本发明公开了一种半导体封装的EMI屏蔽方法，包括将带的边缘附着到框架的下侧的带附接步骤，以将带设置在框架的内周侧内;带切割步骤，磁带以规则的间隔，半导体封装紧固步骤，将半导体封装的下侧的边缘设置在磁带的上侧，使得形成在半导体封装的下侧上的凸块插入磁带的孔中从而将半导体封装以规则的间隔紧固到带的上侧，以及涂覆步骤，在带上进行涂覆操作，以在半导体封装和磁带的上侧形成涂层。

56. 发明授权

US09576945B2 Methods and apparatus for increased holding voltage in silicon controlled rectifiers for ESD protection 有权
标题翻译：用于ESD保护的可控硅整流器中增加保持电压的方法和装置
公开(公告)号：US09576945B2
公开(公告)日：2017-02-21
申请号：US14593894
申请日：2015-01-09
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Jam-Wem Lee , Tzu-Heng Chang , Tsung-Che Tsai , Ming-Hsiang Song
IPC分类号： H01L29/45 , H01L27/02 , H01L23/62 , H01L27/092 , H01L23/60 , H01L29/06 , H01L29/73 , H01L21/8248 , H01L29/812
CPC分类号： H01L27/0262 , H01L21/8248 , H01L23/60 , H01L23/62 , H01L27/0921 , H01L29/0619 , H01L29/73 , H01L29/812
摘要： Methods and apparatus for increased holding voltage SCRs. A semiconductor device includes a semiconductor substrate of a first conductivity type; a first well of the first conductivity type; a second well of a second conductivity type adjacent to the first well, an intersection of the first well and the second well forming a p-n junction; a first diffused region of the first conductivity type formed at the first well and coupled to a ground terminal; a first diffused region of the second conductivity type formed at the first well; a second diffused region of the first conductivity type formed at the second well and coupled to a pad terminal; a second diffused region of the second conductivity type formed in the second well; and a Schottky junction formed adjacent to the first diffused region of the second conductivity type coupled to a ground terminal. Methods for forming devices are disclosed.
摘要翻译：提高保持电压SCR的方法和装置。半导体器件包括第一导电类型的半导体衬底; 第一导电类型的第一井; 与第一阱相邻的第二导电类型的第二阱，形成p-n结的第一阱和第二阱的交点; 第一导电类型的第一扩散区域形成在第一阱处并且耦合到接地端子; 形成在第一阱处的第二导电类型的第一扩散区域; 第二导电类型的第二扩散区域形成在第二阱处并耦合到焊盘端子; 第二导电类型的第二扩散区形成在第二阱中; 以及与第二导电类型的第一扩散区相邻形成的与肖特基结相连的接地端子。公开了用于形成装置的方法。

57. 发明授权

US09570906B2 Voltage clamping circuit 有权
标题翻译：钳位电路
公开(公告)号：US09570906B2
公开(公告)日：2017-02-14
申请号：US14677921
申请日：2015-04-02
申请人： Zhengxiang Wang , Yang Wang
发明人： Zhengxiang Wang , Yang Wang
IPC分类号： H02H3/22 , H02H9/04 , H01L23/60 , H01L27/02
CPC分类号： H02H9/046 , H01L23/60 , H01L27/0259 , H01L27/0266 , H02H9/041
摘要： A voltage supply for providing a clamped voltage to a circuit element to be protected against electrical overstress (EOS) has a reference voltage module and a voltage clamp module. The reference voltage module has a first field-effect transistor (FET) whose source and drain are connected in series between a programmable reference current source and a first resistor across a power supply. The gate of the first FET is connected to its drain to provide a reference voltage defined by the reference current flowing in the first resistor. The voltage clamp module has a second FET whose gate receives the reference voltage and whose source is connected to provide to the protected circuit element the clamped voltage whose variation is limited by the reference voltage.
摘要翻译：用于向要被保护以防止电过压（EOS）的电路元件提供钳位电压的电压源具有参考电压模块和电压钳模块。参考电压模块具有第一场效应晶体管（FET），其源极和漏极串联在可编程参考电流源和跨电源的第一电阻之间。第一FET的栅极连接到其漏极，以提供由在第一电阻器中流动的参考电流限定的参考电压。电压钳模块具有第二FET，其栅极接收参考电压，并且其源极连接以向受保护的电路元件提供变化受参考电压限制的钳位电压。

58. 发明申请

US20170040289A1 SEMICONDUCTOR PACKAGE 审中-公开
标题翻译：半导体封装
公开(公告)号：US20170040289A1
公开(公告)日：2017-02-09
申请号：US15213392
申请日：2016-07-18
申请人： Samsung Electronics Co., Ltd.
发明人： Jae-Gil LIM , JUNYOUNG KO , SEYEOUL PARK , Kyung-A JIN
IPC分类号： H01L25/065 , H01L25/18
CPC分类号： H01L25/18 , H01L23/552 , H01L23/60 , H01L25/0657 , H01L2224/05554 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48145 , H01L2224/49175 , H01L2224/73265 , H01L2225/06506 , H01L2225/06537 , H01L2225/06562 , H01L2924/15311 , H01L2924/181 , H01L2924/19107 , H01L2924/00014 , H01L2924/00012 , H01L2924/00
摘要： Embodiments of a semiconductor package includes first semiconductor chips stacked on a substrate to form an offset stack structure, and a second semiconductor chip disposed on the substrate and electrically connected to the substrate through an input/output (I/O) wire and a ground wire. The first semiconductor chips are stacked to slope toward the second semiconductor chip. A height of the topmost portion of the ground wire from the top of the second semiconductor chip is higher than a height of the topmost portion of the I/O wire from the top of second semiconductor chip.
摘要翻译：半导体封装的实施例包括堆叠在衬底上以形成偏移堆叠结构的第一半导体芯片和设置在衬底上并通过输入/输出（I / O）线和接地线电连接到衬底的第二半导体芯片。第一半导体芯片被堆叠以朝向第二半导体芯片倾斜。接地线从第二半导体芯片的顶部的最高部分的高度高于来自第二半导体芯片的顶部的I / O线的最高部分的高度。

59. 发明申请

US20170025369A1 SHIELDED QFN PACKAGE AND METHOD OF MAKING 有权
标题翻译：屏蔽QFN封装及其制造方法
公开(公告)号：US20170025369A1
公开(公告)日：2017-01-26
申请号：US14806486
申请日：2015-07-22
申请人： NXP B.V.
发明人： Jan Gulpen , Leonardus Antonius Elisabeth van Gemert
IPC分类号： H01L23/60 , H01L23/31 , H01L21/78 , H01L21/52 , H01L21/3205 , H01L23/495 , H01L21/56
CPC分类号： H01L23/552 , H01L21/32051 , H01L21/4825 , H01L21/52 , H01L21/561 , H01L21/565 , H01L21/78 , H01L23/3107 , H01L23/3114 , H01L23/3121 , H01L23/49503 , H01L23/4952 , H01L23/49541 , H01L23/49548 , H01L23/49575 , H01L23/60 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/92 , H01L24/97 , H01L2224/32245 , H01L2224/45014 , H01L2224/48247 , H01L2224/73265 , H01L2224/92247 , H01L2224/97 , H01L2924/00012 , H01L2224/83 , H01L2224/85 , H01L2924/00
摘要： Consistent with an example embodiment, a semiconductor device comprises a device die having bond pads providing connection to device die circuitry and a QFN half-etched lead frame with a package boundary; the QFN half-etched lead frame has a top-side surface and an under-side surface. The QFN half-etched lead frame includes a sub-structure of I/O terminals and a die attach area, the die attach area facilitating device die attachment thereon and the terminal I/O terminals providing connection to the device die bond pads and additional terminals located about the corners of the sub-structure. An envelope of molding compound encapsulates the device die mounted on the top-side surface of the QFN half-etched lead frame. A RF (radio-frequency) shield layer is on the envelope of the molding compound, the RF shield electrically connected to the additional terminals via conductive connections defined in corresponding locations on the envelope of the molding compound.
摘要翻译：与示例实施例一致，半导体器件包括具有提供到器件管芯电路的连接的接合焊盘的器件管芯和具有封装边界的QFN半蚀刻引线框架; QFN半蚀刻引线框架具有顶侧表面和下侧表面。 QFN半蚀刻引线框架包括I / O端子的子结构和管芯附着区域，管芯附着区域有助于器件管芯附着在其上，并且端子I / O端子提供与器件管芯接合焊盘和附加端子的连接位于子结构的拐角处。模塑料的包络封装安装在QFN半蚀刻引线框架的顶侧表面上的器件裸片。 RF（射频）屏蔽层位于模制化合物的封套上，RF屏蔽通过在模制化合物的封套上的相应位置中限定的导电连接电连接到附加端子。

60. 发明申请

US20170025368A1 CONDUCTIVE SEAL RING FOR POWER BUS DISTRIBUTION 有权
标题翻译：用于电力总线分配的导电密封圈
公开(公告)号：US20170025368A1
公开(公告)日：2017-01-26
申请号：US14809141
申请日：2015-07-24
申请人： QUALCOMM INCORPORATED
发明人： Christopher N. Brindle , Anton Arriagada
IPC分类号： H01L23/58 , H01L23/00 , H01L23/66 , H01L23/60 , H01L23/522 , H01L23/528
CPC分类号： H01L23/585 , H01L23/5225 , H01L23/5286 , H01L23/562 , H01L23/60 , H01L23/66
摘要： A multi-block semiconductor device includes a first block and a second block operating in different power regimes from each other. A seal ring is around a periphery of the die, hermetically sealing the first and second blocks. The die has a substrate and an insulating layer, the seal ring being on the insulating layer. The seal ring serves as a power bus for the first block but not the second block. The seal ring and first block are electrically coupled to a first ground node, the first ground node being electrically isolated at a die-level from other ground nodes in the multi-block semiconductor device. In some embodiments, the second block is located in a central area of the die, and a plurality of metal lines electrically connect the seal ring to the first block, the metal lines being evenly spaced around a majority of the periphery of the semiconductor die.
摘要翻译：多块半导体器件包括彼此以不同功率方式工作的第一块和第二块。密封环围绕模具的周边，密封第一和第二块。模具具有基板和绝缘层，密封环位于绝缘层上。密封圈用作第一块的电源总线，但不是第二个块。密封环和第一块电耦合到第一接地节点，第一接地节点与多块半导体器件中的其它接地节点在晶片级电隔离。在一些实施例中，第二块位于模具的中心区域中，并且多个金属线将密封环电连接到第一块，金属线围绕半导体管芯的大部分周边均匀间隔开。

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