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51. 发明授权

US06927993B2 Multi-bit ROM cell, for storing on of N>4 possible states and having bi-directional read, an array of such cells 有权
标题翻译：用于存储N> 4个可能状态并具有双向读取的多位ROM单元，这样的单元阵列
公开(公告)号：US06927993B2
公开(公告)日：2005-08-09
申请号：US10642079
申请日：2003-08-14
申请人： Bomy Chen , Kai Man Yue , Dana Lee , Feng Gao
发明人： Bomy Chen , Kai Man Yue , Dana Lee , Feng Gao
IPC分类号： G11C11/56 , G11C17/00 , G11C17/12 , H01L21/8236 , H01L21/8246 , H01L27/112
CPC分类号： H01L27/112 , G11C11/5692 , G11C17/12 , H01L27/1126 , H01L27/11266
摘要： A array of multi-bit Read Only Memory (ROM) cells is in a semiconductor substrate of a first conductivity type with a first concentration. Each ROM cell has a first and second regions of a second conductivity type spaced apart from one another in the substrate. A channel is between the first and second regions. The channel has three portions, a first portion, a second portion and a third portion. A gate is spaced apart and is insulated from at least the second portion of the channel. Each ROM cell has one of a plurality of N possible states, where N is greater than 2. The state of each ROM cell is determined by the existence or absence of extensions or halos that are formed in the first portion of the channel and adjacent to the first region and/or in the third portion of the channel adjacent to the second region. These extensions and halos are formed at the same time that extensions or halos are formed in MOS transistors in other parts of the integrated circuit device, thereby reducing cost. The array of ROM cells are arranged in a plurality of rows and columns, with ROM cells in the same row having their gates connected together. ROM cells in the same column have the first regions connected in a common first column, and second regions connected in common second column. Finally, ROM cells in adjacent columns to one side share a common first column, and cells in adjacent columns to another side share a common second column.
摘要翻译：多位只读存储器（ROM）单元的阵列位于具有第一浓度的第一导电类型的半导体衬底中。每个ROM单元具有在基板中彼此间隔开的第二导电类型的第一和第二区域。通道在第一和第二区域之间。通道具有三个部分，第一部分，第二部分和第三部分。栅极间隔开并且至少与通道的第二部分绝缘。每个ROM单元具有多个N个可能状态中的一个，其中N大于2.每个ROM单元的状态由存在或不存在在通道的第一部分中形成并与通道的第一部分相邻第一区域和/或与第二区域相邻的通道的第三部分。在集成电路器件的其他部分的MOS晶体管中形成扩展或光晕的同时形成这些扩展和光晕，从而降低成本。 ROM单元的阵列被布置成多个行和列，其中同一行中的ROM单元的门连接在一起。同一列中的ROM单元具有连接在公共第一列中的第一区域和连接在公共第二列中的第二区域。最后，一侧的相邻列中的ROM单元共享一个共同的第一列，另一侧的相邻列中的单元格共享第二列。

52. 发明申请

US20050063220A1 Memory device and method for simultaneously programming and/or reading memory cells on different levels 失效
标题翻译：用于同时编程和/或读取不同级别的存储单元的存储器件和方法
公开(公告)号：US20050063220A1
公开(公告)日：2005-03-24
申请号：US10987091
申请日：2004-11-12
申请人： Mark Johnson
发明人： Mark Johnson
IPC分类号： G11C11/56 , G11C17/14 , G11C17/16 , H01L27/102 , G11C17/00
CPC分类号： G11C17/06 , G11C11/5692 , G11C13/003 , G11C17/14 , G11C17/16 , G11C17/165 , G11C2213/71 , G11C2213/76 , H01L27/101 , H01L27/1021 , H01L27/2481 , H01L45/1233 , H01L45/16
摘要： A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.
摘要翻译：公开了一种非常高密度的现场可编程存储器。阵列垂直地形成在衬底上方，使用几层，其各层包括垂直制造的存储单元。 N级阵列中的单元可以形成N + 1掩蔽步骤以及接触所需的掩蔽步骤。自动对准技术的最大限度地使光刻限制最小化。在一个实施例中，外围电路形成在硅衬底中，并且在衬底上方制造N电平阵列。

53. 发明申请

US20050035395A1 Array of multi-bit ROM cells with each cell having bi-directional read and a method for making the array 有权
标题翻译：具有每个单元具有双向读取的多位ROM单元的阵列和用于制作阵列的方法
公开(公告)号：US20050035395A1
公开(公告)日：2005-02-17
申请号：US10642078
申请日：2003-08-14
申请人： Dana Lee , Bomy Chen
发明人： Dana Lee , Bomy Chen
IPC分类号： G11C11/56 , G11C17/12 , H01L21/8246 , H01L27/112 , H01L29/788
CPC分类号： H01L27/11266 , G11C11/5692 , G11C17/12 , H01L27/112
摘要： A array of multi-bit Read Only Memory (ROM) cells is in a semiconductor substrate of a first conductivity type with a first concentration. Each ROM cell has a first and second regions of a second conductivity type spaced apart from one another in the substrate. A channel is between the first and second regions. The channel has three portions, a first portion, a second portion and a third portion. A gate is spaced apart and is insulated from at least the second portion of the channel. Each ROM cell has one of a plurality of N possible states, where N is greater than 2. The state of each ROM cell is determined by the existence or absence of extensions or halos that are formed in the first portion of the channel and adjacent to the first region and/or in the third portion of the channel adjacent to the second region. These extensions and halos are formed at the same time that extensions or halos are formed in MOS transistors in other parts of the integrated circuit device, thereby reducing cost. The array of ROM cells are arranged in a plurality of rows and columns, with ROM cells in the same row having their gates connected together. ROM cells in the same column have the first regions connected in a common first column, and second regions connected in common second column. Finally, ROM cells in adjacent columns to one side share a common first column, and cells in adjacent columns to another side share a common second column.
摘要翻译：多位只读存储器（ROM）单元的阵列位于具有第一浓度的第一导电类型的半导体衬底中。每个ROM单元具有在基板中彼此间隔开的第二导电类型的第一和第二区域。通道在第一和第二区域之间。通道具有三个部分，第一部分，第二部分和第三部分。门间隔开并与通道的至少第二部分绝缘。每个ROM单元具有多个N个可能状态中的一个，其中N大于2.每个ROM单元的状态由存在或不存在在通道的第一部分中形成并与通道的第一部分相邻第一区域和/或与第二区域相邻的通道的第三部分。在集成电路器件的其他部分的MOS晶体管中形成扩展或光晕的同时形成这些扩展和光晕，从而降低成本。 ROM单元的阵列被布置成多个行和列，其中同一行中的ROM单元的门连接在一起。同一列中的ROM单元具有连接在公共第一列中的第一区域和连接在公共第二列中的第二区域。最后，一侧的相邻列中的ROM单元共享一个共同的第一列，另一侧的相邻列中的单元格共享第二列。

54. 发明授权

US06809948B2 Mask programmable read-only memory (ROM) cell 失效
标题翻译：掩模可编程只读存储器（ROM）单元
公开(公告)号：US06809948B2
公开(公告)日：2004-10-26
申请号：US10430931
申请日：2003-05-06
申请人： Ishai Nachumovsky , Yaov Nissan-Cohen , Robert J. Strain
发明人： Ishai Nachumovsky , Yaov Nissan-Cohen , Robert J. Strain
IPC分类号： G11C1700
CPC分类号： H01L27/112 , G11C11/5692 , G11C17/16
摘要： A multi-bit programmable memory cell is provided that includes an access transistor and a plurality of N anti-fuse elements. The access transistor has a source coupled to a source line and a gate coupled to a word line. Each of the anti-fuse elements has a first terminal coupled to a drain of the access transistor, and a second terminal coupled to a corresponding bit line. At most, only one of the anti-fuse elements is programmed. The memory cell is capable of storing M bits, wherein N=2M−1. A method is provided for both programming and reading the memory cell. In another embodiment, the anti-fuse elements can be replaced with mask-programmable elements.
摘要翻译：提供了一种多位可编程存储单元，其包括存取晶体管和多个N个反熔丝元件。存取晶体管具有耦合到源极线的源极和耦合到字线的栅极。每个反熔丝元件具有耦合到存取晶体管的漏极的第一端子和耦合到相应位线的第二端子。最多只有一个反熔丝元件被编程。存储单元能够存储M位，其中N = 2-M -1。提供了编程和读取存储器单元的方法。在另一个实施例中，反熔丝元件可以用掩模可编程元件代替。

55. 发明申请

US20040208055A1 Methods and circuits for testing programmability of a semiconductor memory cell and memory array using a breakdown phenomenon in an ultra-thin dielectric 有权
标题翻译：使用超薄电介质中的击穿现象来测试半导体存储单元和存储器阵列的可编程性的方法和电路
公开(公告)号：US20040208055A1
公开(公告)日：2004-10-21
申请号：US10796270
申请日：2004-03-09
发明人： Jianguo Wang , David Fong , Jack Zezhong Peng , Fei Ye , Michael David Fliesler
IPC分类号： G11C011/34
CPC分类号： G11C11/5692 , G11C17/16 , G11C29/50 , G11C2029/5006 , H01L27/112 , H01L27/11206
摘要： A method of testing the programmability of a memory cell is disclosed. The memory cell comprises a select transistor and a data storage element. The method comprises applying a test voltage across the data storage element. The select transistor is turned on. Finally, a current flow through the data storage element when the test voltage is applied is measured. A test positive signal is indicated if the current flow is greater than a reference.
摘要翻译：公开了一种测试存储器单元的可编程性的方法。存储单元包括选择晶体管和数据存储元件。该方法包括在数据存储元件上施加测试电压。选择晶体管导通。最后，测量施加测试电压时通过数据存储元件的电流。如果电流大于参考值，则显示测试正信号。

56. 发明授权

US06690597B1 Multi-bit PROM memory cell 有权
标题翻译：多位PROM存储单元
公开(公告)号：US06690597B1
公开(公告)日：2004-02-10
申请号：US10422439
申请日：2003-04-24
申请人： Craig M. Perlov , Ping Mei
发明人： Craig M. Perlov , Ping Mei
IPC分类号： G11C700
CPC分类号： G11C11/5692 , G11C17/16 , G11C2216/26
摘要： A memory cell comprises at least two antifuses in series with a diode. Each antifuse expresses a different resistance from the others when blown, and each requires an escalating programming voltage over the last to be programmed. The antifuse structures differ in their respective geometries and materials so that a low programming voltage will blow the more sensitive fuse first, and a higher voltages will program the lesser sensitive fuses thereafter.
摘要翻译：存储单元包括与二极管串联的至少两个反熔丝。每个反熔丝在吹制时表现出与其他反射体不同的电阻，并且每个反熔丝需要在最后编程的程序电压上升。反熔丝结构在其各自的几何形状和材料上是不同的，因此低编程电压将首先吹出更敏感的熔丝，并且更高的电压将对较小的敏感熔丝编程。

57. 发明申请

US20030223291A1 Multi-bit programmable memory cell having multiple anti-fuse elements 失效
标题翻译：具有多个反熔丝元件的多位可编程存储单元
公开(公告)号：US20030223291A1
公开(公告)日：2003-12-04
申请号：US10430931
申请日：2003-05-06
申请人： Tower Semiconductor, Ltd.
发明人： Ishai Nachumovsky , Yaov Nissan-Cohen , Robert J. Strain
IPC分类号： G11C017/00
CPC分类号： H01L27/112 , G11C11/5692 , G11C17/16
摘要： A multi-bit programmable memory cell is provided that includes an access transistor and a plurality of N anti-fuse elements. The access transistor has a source coupled to a source line and a gate coupled to a word line. Each of the anti-fuse elements has a first terminal coupled to a drain of the access transistor, and a second terminal coupled to a corresponding bit line. At most, only one of the anti-fuse elements is programmed. The memory cell is capable of storing M bits, wherein Nnull2Mnull1. A method is provided for both programming and reading the memory cell. In another embodiment, the anti-fuse elements can be replaced with mask-programmable elements.
摘要翻译：提供了一种多位可编程存储单元，其包括存取晶体管和多个N个反熔丝元件。存取晶体管具有耦合到源极线的源极和耦合到字线的栅极。每个反熔丝元件具有耦合到存取晶体管的漏极的第一端子和耦合到相应位线的第二端子。最多只有一个反熔丝元件被编程。存储单元能够存储M位，其中N = 2-M -1。提供了编程和读取存储器单元的方法。在另一个实施例中，反熔丝元件可以用掩模可编程元件代替。

58. 发明申请

US20030132482A1 Semiconductor device and method for producing the same 失效
公开(公告)号：US20030132482A1
公开(公告)日：2003-07-17
申请号：US10336805
申请日：2003-01-06
申请人： Semiconductor Energy Laboratory Co., Ltd.
发明人： Minoru Miyazaki , Akane Murakami , Satoshi Teramoto
IPC分类号： H01L027/01 , H01L027/12 , H01L031/0392
CPC分类号： G11C11/56 , G11C11/5692 , H01L27/12 , H01L29/42384 , H01L29/4908 , H01L29/66757 , H01L29/78603
摘要： In the production of thin film transistor (TFT), a gate insulating film is formed to cover an active layer, a titanium nitride film is formed on the gate insulating film, and an aluminum film used as the gate electrode is formed on the titanium nitride film. The resulted configuration prevents the etching of the aluminum film from the insulating film side even if the etchant of aluminum enters the recessed portion at the edge of the active layer during the patterning of the gate electrode. Also in the anodizing process, when an oxide film is formed on the surface of the aluminum film, the oxidation of aluminum from the gate insulating film side is prevented even when the electrolyte solution enters the recessed portion at the edge of the active layer.

59. 发明授权

US06556468B2 High bit density, high speed, via and metal programmable read only memory core cell architecture 有权
公开(公告)号：US06556468B2
公开(公告)日：2003-04-29
申请号：US09917226
申请日：2001-07-27
申请人： Anurag Garg
发明人： Anurag Garg
IPC分类号： G11C1700
CPC分类号： G11C17/16 , G06F2213/0038 , G11C11/5692
摘要： A high bit density, high speed, via and metal BE type programmable ROM core cell architecture for storing large amounts of non-volatile data and having a relatively fast turn around time is provided. The ROM core cell may include memory cells organized in rows and columns where each of the memory cells includes three transistors and two bit lines. The arrangement between the three transistors and two bit lines may be such that each of the memory cells is capable of storing four bits of data.

60. 发明申请

US20030026121A1 Vertically stacked field programmable nonvolatile memory and method of fabrication 有权
公开(公告)号：US20030026121A1
公开(公告)日：2003-02-06
申请号：US10253354
申请日：2002-09-23
发明人： Mark G. Johnson , Thomas H. Lee , Vivek Subramanian , Paul Michael Farmwald , James M. Cleeves
IPC分类号： G11C011/00
CPC分类号： G11C17/06 , G11C11/5692 , G11C13/003 , G11C17/14 , G11C17/16 , G11C17/165 , G11C2213/71 , G11C2213/76 , H01L27/101 , H01L27/1021 , H01L27/2481 , H01L45/1233 , H01L45/16
摘要： A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with Nnull1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.

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