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51. 发明授权

US4884233A Fast summing circuit 失效
标题翻译：快速求和电路
公开(公告)号：US4884233A
公开(公告)日：1989-11-28
申请号：US207110
申请日：1988-06-14
申请人： Akira Ishizuka , Toshihiko Nakamura
发明人： Akira Ishizuka , Toshihiko Nakamura
IPC分类号： G06F7/50 , G06F7/52
CPC分类号： G06F7/5336 , G06F7/509 , G06F7/49994
摘要： A summing circuit (20) is for summing up zeroth through n-th input data signals A(0) to A(n) to produce a sum signal S consisting of zeroth through m-th output bits s(0) to s(m) where n represents a first predetermined natural number and m represents a second predetermined natural number which is not less than the first predetermined natural number. A preprocessing circuit (22) preprocesses the zeroth through the n-th input data signals A(0) to A(n) into a preprocessed signal which is (n+1) bits long. A logic circuit (24) carries out a logical operation on the preprocessed signal to produce the sum signal S. For example, each of the zeroth through the n-th input data signals A(0) to A(n) is given by an equation: ##EQU1## where a(d) represents a d-th coefficient having one of logic zero and one values, k represents a predetermined integer which is not less than zero, and A represents a common coefficient having the logic zero value. Each of the zeroth through the n-th input data signals A(0) to A(n) may be given by another equation: ##EQU2## where p(d)'s represent zeroth through n-th discrete integers.

52. 发明授权

US4811270A Merged CCD/MOS integrated circuit 失效
标题翻译：合并的CCD / MOS集成电路
公开(公告)号：US4811270A
公开(公告)日：1989-03-07
申请号：US788305
申请日：1985-10-17
申请人： James G. Nash
发明人： James G. Nash
IPC分类号： G06F7/52 , G06F7/00 , G06F7/16
CPC分类号： G06F7/533 , G06F7/5336 , G06F2207/4808
摘要： A digital integrated circuit that includes on a common substrate both charge-coupled device (CCD) circuitry and metal-oxide semiconductor (MOS) circuitry that combine together efficiently to implement a complex digital function such as a multi-bit multiplier or divider. The CCD circuitry includes an array of full adder cells and the MOS circuitry selectively processes and channels certain bits of a plurality of digital input bits to the individual full adder cells, such processing being based on other of the digital input bits. The introduction of MOS logic into the CCD circuit permits greater flexibility in the layout and interconnection of the individual full adder cells and permits the utilization of more efficient algorithms than otherwise could be used in circuits having CCD elements alone.
摘要翻译：一种数字集成电路，其包括在共同的基板上，电荷耦合器件（CCD）电路和金属氧化物半导体（MOS）电路组合在一起以有效地实现诸如多位乘法器或分频器之类的复数数字功能。 CCD电路包括全加器单元的阵列，并且MOS电路选择性地处理和通道多个数字输入位的某些位给各个全加器单元，这种处理基于其他数字输入位。将MOS逻辑引入CCD电路允许各个全加器单元的布局和互连中的更大的灵活性，并且允许使用比用于单独具有CCD元件的电路中更有效的算法。

53. 发明授权

US4718031A Multiplying circuit 失效
标题翻译：乘法电路
公开(公告)号：US4718031A
公开(公告)日：1988-01-05
申请号：US697652
申请日：1985-02-04
申请人： Tomoji Nukiyama
发明人： Tomoji Nukiyama
IPC分类号： G06F7/533 , G06F7/507 , G06F7/508 , G06F7/52 , G06F7/53
CPC分类号： G06F7/5336
摘要： In a multiplying operation, a first partial product corresponding to multiplication of the multiplicand by even multipliers can be produced by a shifting operation, while a second partial product corresponding to multiplication of the multiplicand by odd multipliers is produced by a shifting operation and an adding operation. In the described multiplying circuit, the first partial product is produced according to the result of a decoding operation for generating signals designating the partial product to be used in the multiplying operation. On the other hand the second partial product is independently produced regardless of the decoding result when the multiplicand is received to the multiplying circuit. Thus, a high speed multiplying operation can be achieved.
摘要翻译：在乘法运算中，通过移位运算可以产生与被乘数乘以偶数乘法运算相对应的第一部分乘积，而通过移位运算和加法运算产生与被乘数乘以奇乘数的乘法相对应的第二部分乘积。在描述的乘法电路中，根据用于产生指定要在乘法运算中使用的部分乘积的信号的解码操作的结果，产生第一部分乘积。另一方面，当乘法器被接收到乘法电路时，无论解码结果如何，独立地产生第二部分乘积。因此，可以实现高速乘法运算。

54. 发明申请

US20110040816A1 Negative two's complement processor for windowing in harmonic analysis 失效
标题翻译：负二阶补码处理器用于窗口谐波分析
公开(公告)号：US20110040816A1
公开(公告)日：2011-02-17
申请号：US12925352
申请日：2010-10-20
申请人： Earl Eugene Swartzlander, JR.
发明人： Earl Eugene Swartzlander, JR.
IPC分类号： G06F7/483 , G06F7/52 , G06F7/50 , G06F5/01
CPC分类号： G06F7/38 , G06F7/4991 , G06F7/53 , G06F7/5336 , G06F2207/3832
摘要： The present invention provides a solution to the shortcomings of the traditional two's complement system that is commonly utilized in modern computing systems and digital signal processors for calculating harmonic analysis using a discrete time-frequency transform. In the negative two's complement processor a n-bit number, A, has a sign bit, an−1, and n−1 fractional bits, an−2, an−3, . . . , a0. The value of an n-bit fractional negative two's complement number is: A = a n - 1 + ∑ i = 0 n - 2  - a i  2 i - n + 1 .
摘要翻译：本发明提供了一种常规用于现代计算系统和数字信号处理器的传统二进制补码系统的缺点的解决方案，用于计算使用离散时频变换的谐波分析。在负二进制补码处理器中，n位数字A具有符号位，1和1分数位，a-2，a-3。。。，a0。 n位分数负二进制补码的值为：A = a n - 1 +Σi = 0 n - 2 - a i 2 i - n + 1。

55. 发明授权

US07373370B2 Extendable squarer and operation method for processing digital signals 有权
标题翻译：可扩展的平方和数字信号处理操作方法
公开(公告)号：US07373370B2
公开(公告)日：2008-05-13
申请号：US10899734
申请日：2004-07-26
申请人： Shi-Ho Tien , Ching-Chun Meng , Tzu-Ying Chu , Yow-Ling Gau
发明人： Shi-Ho Tien , Ching-Chun Meng , Tzu-Ying Chu , Yow-Ling Gau
IPC分类号： G06F7/38
CPC分类号： G06F7/552 , G06F7/5336 , G06F2207/5523
摘要： An extendable squarer for processing digital signals, suitable for processing a square operation for n-bit data is disclosed. The extendable squarer comprise a bit expanding circuit and a plurality of operating units. The bit expanding circuit comprises n−1 bit expanding output terminals for outputting a plurality of bit expanding data. The operation units receive a plurality of bit codes of the n-bit data corresponding thereto according to the binary weight. In addition, except for bit code of the most-significant bit, the other operation units receive the corresponding bit expanding data output by the bit expanding circuit respectively. The present invention generates the square operation value of the n-bit data based on the corresponding bit expanding data and bit codes.
摘要翻译：公开了一种用于处理数字信号的可扩展平方，适用于处理n位数据的平方运算。可扩展平方体包括位扩展电路和多个操作单元。位扩展电路包括用于输出多个位扩展数据的n-1位扩展输出端。操作单元根据二进制权重接收对应于其的n位数据的多个位代码。此外，除了最高有效位的位代码之外，其他操作单元分别接收由位扩展电路输出的对应的位扩展数据。本发明基于相应的比特扩展数据和比特码产生n比特数据的平方运算值。

56. 发明授权

US07308470B2 Smaller and lower power static mux circuitry in generating multiplier partial product signals 有权
标题翻译：产生乘法器部分乘积信号的较小和较低功率的静态多路复用电路
公开(公告)号：US07308470B2
公开(公告)日：2007-12-11
申请号：US10728395
申请日：2003-12-05
申请人： Kenneth Y. Ng
发明人： Kenneth Y. Ng
IPC分类号： G06F7/52
CPC分类号： G06F7/5336
摘要： A multiplier circuit to receive a multiplier and a multiplicand comprises at least one Booth encoder circuit to encode a plurality of multiplier bits into four encoded outputs. The encoded outputs select Booth-multiply functions. The circuit also includes a plurality of multiplexer circuits, one multiplexer circuit for each bit of the multiplicand. The at least one of the plurality multiplexer circuits includes four pass gates coupled to receive a multiplicand bit, a complement of the multiplicand bit, multiplexed data from a next lower order multiplexer circuit and the encoded outputs of the Booth encoder circuit outputs to provide one bit of a partial product at a multiplexer output.
摘要翻译：用于接收乘法器和被乘数的乘法器电路包括至少一个布斯编码器电路，以将多个乘法器比特编码为四个编码输出。编码输出选择展位乘法功能。该电路还包括多个多路复用器电路，一个用于被乘数的每一比特的多路复用器电路。多个多路复用器电路中的至少一个包括四个通路，其耦合以接收被乘数位，被乘数位的补码，来自下一个较低阶多路复用器电路的多路复用数据和布斯编码器电路输出的编码输出，以提供一位在多路复用器输出处的部分乘积。

57. 发明申请

US20060020652A1 Extendable squarer and method of square operation 有权
标题翻译：可扩展平方和平方运算法
公开(公告)号：US20060020652A1
公开(公告)日：2006-01-26
申请号：US10899734
申请日：2004-07-26
申请人： Shi-Ho Tien , Ching-Chun Meng , Tzu-Ying Chu , Yow-Ling Gau
发明人： Shi-Ho Tien , Ching-Chun Meng , Tzu-Ying Chu , Yow-Ling Gau
IPC分类号： G06F7/38
CPC分类号： G06F7/552 , G06F7/5336 , G06F2207/5523
摘要： An extendable squarer applied for processing a square operation for n-bit data is disclosed. The extendable squarer comprise a bit expanding circuit and a plurality of operating units. The bit expanding circuit comprises n−1 bit expanding output terminals for outputting a plurality of bit expanding data. The operation units receive a plurality of bit codes of the n-bit data corresponding thereto according to the binary weight. In addition, except for bit code of the most-significant bit, the other operation units receive the corresponding bit expanding data output by the bit expanding circuit respectively. The present invention generates the square operation value of the n-bit data based on the corresponding bit expanding data and bit codes.
摘要翻译：公开了一种用于处理n位数据的平方运算的可扩展平方。可扩展平方体包括位扩展电路和多个操作单元。位扩展电路包括用于输出多个位扩展数据的n-1位扩展输出端。操作单元根据二进制权重接收对应于其的n位数据的多个位代码。此外，除了最高有效位的位代码之外，其他操作单元分别接收由位扩展电路输出的对应的位扩展数据。本发明基于相应的比特扩展数据和比特码产生n比特数据的平方运算值。

58. 发明申请

US20040199563A1 Noise invariant circuits, systems and methods 有权
标题翻译：噪声不变电路，系统和方法
公开(公告)号：US20040199563A1
公开(公告)日：2004-10-07
申请号：US10832141
申请日：2004-04-26
发明人： Edwin De Angel , Eric J. Swanson
IPC分类号： G06J001/00
CPC分类号： G06F7/5336 , G06F2207/3868
摘要： The electrical circuitry for a multiplier system includes a counter for determining proximity to sampling operation, and a switch to select between symmetrical noise invariant operation and a low-power mode of operation. A noise invariant circuit disables row skip operation in a multi-row multiplier, to enable analog sampling. Disabling of the row skip operation is accomplished at a time which is several digital cycles preceding the time of analog sampling. Power saving multiplier row skippage resumes after analog sampling is completed.
摘要翻译：用于乘法器系统的电路包括用于确定接近采样操作的计数器，以及用于在对称噪声不变操作和低功率操作模式之间进行选择的开关。噪声不变电路禁用多行乘法器中的行跳跃操作，以启用模拟采样。在模拟采样之前的几个数字周期的时间，完成禁止行跳过操作。模拟采样完成后，省电倍增器行跳转恢复。

59. 发明申请

US20040128338A1 Pipelined multiplicative division with IEEE rounding 审中-公开
标题翻译：流水线乘法除法与IEEE四舍五入
公开(公告)号：US20040128338A1
公开(公告)日：2004-07-01
申请号：US10695623
申请日：2003-10-29
发明人： Guy Even , Peter-Michael Seidel
IPC分类号： G06F007/52
CPC分类号： G06F7/535 , G06F7/483 , G06F7/49957 , G06F7/5336 , G06F2207/3884 , G06F2207/5355
摘要： Apparatus and method for performing IEEE-rounded floating-point division utilizing Goldschmidt's algorithm. The use of Newton's method in computing quotients requires two multiplication operations, which must be performed sequentially, and therefore incurs waiting delays and decreases throughput. Goldschmidt's algorithm uses two multiplication operations which are independent and therefore may be performed simultaneously via pipelining. Unfortunately, current error estimates for Goldschmidt's algorithm are imprecise, requiring high-precision multiplication operations for stability, thereby reducing the advantages of the pipelining. A new error analysis provides improved methods for estimating the error in the Goldschmidt algorithm iterations, resulting in reductions in the hardware, improved pipeline organization, reducing the number and length of clock cycles, reducing latency, and increasing throughput.
摘要翻译：使用Goldschmidt算法执行IEEE圆形浮点分割的装置和方法。在计算商中使用牛顿法需要两次相乘操作，它们必须顺序执行，因此会引起等待延迟并降低吞吐量。 Goldschmidt的算法使用两个独立的乘法运算，因此可以通过流水线同时执行。不幸的是，Goldschmidt算法的当前误差估计是不精确的，需要高精度的乘法运算来保证稳定性，从而降低流水线的优点。一个新的误差分析提供了改进的Goldschmidt算法迭代误差估计方法，从而减少了硬件，改进了流水线组织，减少了时钟周期的数量和长度，减少了延迟并提高了吞吐量。

60. 发明申请

US20020103840A1 Apparatus and method for digital multiplication using redundant binary arithmetic 失效
标题翻译：使用冗余二进制算术进行数字乘法的装置和方法
公开(公告)号：US20020103840A1
公开(公告)日：2002-08-01
申请号：US09832869
申请日：2001-04-12
发明人： Hong-June Park , Sang-Hoon Lee
IPC分类号： G06F007/52 , G06F007/00
CPC分类号： G06F7/5336 , G06F7/4824
摘要： A digital multiplication apparatus and method adopting a redundant binary arithmetic is provided. In this digital multiplication apparatus, when two numbers X and Y are multiplied using a radix-2k number system, a data converter data-converts the m-bit number Y into m/k-digit data D(nullDm,knull1Dm/knull2 . . . Di . . . DiD0). A partial product calculator converts each of the digits Di of the number Y converted by the data converter into a combination of the coefficients of a fundamental multiple, multiplies the combination by the number X, and outputs the product as a redundant binary partial product. A redundant binary adder sums the partial products for all of the digits of the converted number Y. A redundant binary (RB)-normal binary (NB) converter converts the redundant binary sum into a normal binary number and outputs the converted normal binary sum as the product of the two numbers. Therefore, even when the radix extends, the burden upon hardware can be minimized. Also, many systems having multipliers serving as important components can be more simply constructed.
摘要翻译：提供了采用冗余二进制运算的数字乘法装置和方法。在该数字乘法装置中，当使用基数-2k数乘以两个数X和Y时，数据转换器将m位数Y转换成m / k位数据D（= Dm，k-1Dm / k-2 ... Di ... DiD0）。部分乘积计算器将由数据转换器转换的数字Y的数字Di中的每一个转换为基本倍数的系数的组合，将组合乘以数X，并将该乘积作为冗余二进制部分乘积输出。冗余二进制加法器将所转换的数字Y的所有数字的部分乘积相加。冗余二进制（RB） - 正常二进制（NB）转换器将冗余二进制和转换为正常二进制数，并将转换后的正态二进制和作为这两个数字的产物。因此，即使基数延长，硬件上的负担也可以最小化。此外，可以更简单地构造具有用作重要部件的乘法器的许多系统。

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