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51. 发明授权

US4611276A Device for superimposition of the successive stages of the transfer of data among several data processing units 失效
标题翻译：用于在多个数据处理单元之间叠加数据传送的连续阶段的装置
公开(公告)号：US4611276A
公开(公告)日：1986-09-09
申请号：US591237
申请日：1984-03-20
申请人： Daniel R. Vinot
发明人： Daniel R. Vinot
IPC分类号： G06F9/46 , G06F13/362 , G06F13/378 , G06F13/42 , G06F15/16 , G06F15/177 , G06F13/36
CPC分类号： G06F13/378 , G06F13/4217
摘要： A control logic circuit (C) is provided in each unit such as processors andemories in a multiple processor data processing system. Each control logic circuit (C) is equipped with a priority circuit (P12) which at one input receives the eligible local calls (RQ.sub.i L) of the unit itself and at the other input receives external calls (RQ.sub.k) transmitted by the other units. The control logic circuit (C) enables control by its unit of a transmission but only when its priority circuit (P12) recognizes that unit as having the highest priority among the other units. The logic circuit (C) together with a T circuit (13) selects local calls as a function of the state of occupation of the data lines of the transmission bus.

52. 发明授权

US4454581A Bus contention circuit 失效
标题翻译：总线争用电路
公开(公告)号：US4454581A
公开(公告)日：1984-06-12
申请号：US383900
申请日：1982-06-01
申请人： Michael C. Nystrom
发明人： Michael C. Nystrom
IPC分类号： G06F13/378
CPC分类号： G06F13/378
摘要： A bus contention circuit, is employed for each unit of a system capable of seizing use of a bus, wherein the units are arranged in a priority order. Priority resolution is accomplished by registering a request to seize use of the bus from any unit where either (1) no other requests are so registered or (2) the requesting unit is of lower priority than a unit whose request is already registered. When the bus becomes available for use, use is allocated to the unit with highest priority whose request is already registered.
摘要翻译：总线竞争电路被用于能够占用总线的系统的每个单元，其中，单元以优先级顺序排列。通过注册从任何单位注册使用总线的请求来实现优先级分辨率，其中（1）没有其他请求如此注册，或者（2）请求单元的优先级低于其请求已经注册的单元。当总线可用时，将使用分配给具有最高优先级的单元，其请求已经被注册。

53. 发明授权

US4321669A Microcomputer network having several microcomputer modules which are coupled onto at least one system bus 失效
标题翻译：具有耦合到至少一个系统总线上的多个微型计算机模块的微机网络
公开(公告)号：US4321669A
公开(公告)日：1982-03-23
申请号：US83468
申请日：1979-10-10
申请人： Richard Macmillan
发明人： Richard Macmillan
IPC分类号： G06F13/378 , G06F9/46 , G06F15/16
CPC分类号： G06F13/378
摘要： In a microcomputer system resource and priority testing of modules is provided by first testing for readiness to exchange information via all modules, then testing for the priority assigned to the modules in which flags and registers are operated in a defined sequence to switch bus connections to the various test and data lines.
摘要翻译：在微型计算机系统中，通过首先测试通过所有模块交换信息的准备来提供模块的资源和优先级测试，然后测试分配给模块的优先级，其中标志和寄存器按照定义的顺序被操作以将总线连接切换到各种测试和数据线。

54. 发明授权

US4229791A Distributed arbitration circuitry for data processing system 失效
标题翻译：数据处理系统的分布式仲裁电路
公开(公告)号：US4229791A
公开(公告)日：1980-10-21
申请号：US954456
申请日：1978-10-25
申请人： John V. Levy , David Rodgers , Robert E. Stewart , David Potter , Richard J. Casabona
发明人： John V. Levy , David Rodgers , Robert E. Stewart , David Potter , Richard J. Casabona
IPC分类号： G06F13/26 , G06F13/378 , G06F9/46
CPC分类号： G06F13/378 , G06F13/26
摘要： A digital data processing system including an interconnection for the various elements that constitute the system. Each element that connects to the interconnection is called a nexus, and each nexus in the system can communicate with other nexuses on a priority basis. A central clocking circuit generates timing signals that control such communications by defining bus cycles on a synchronous basis and each nexus contains priority circuitry that operates in response to these signals. Each nexus that requires access to the interconnection asserts a transfer request signal at a predetermined time during each bus cycle. Priority arbitration circuitry in each nexus receives all such requests and samples them at another, later, time during each bus cycle. When a nexus is transmitting a request and no nexus with a higher priority is transmitting a request, that nexus takes control of the interconnection. A transfer during a subsequent bus cycle to another nexus can be prevented during certain types of transfers.
摘要翻译：数字数据处理系统，包括构成系统的各种元件的互连。连接到互连的每个元素称为连接，系统中的每个连接可以优先与其他连接进行通信。中央时钟电路产生通过在同步基础上定义总线周期来控制这种通信的定时信号，并且每个连接线包含响应于这些信号而操作的优先电路。需要访问互连的每个连接在每个总线周期期间的预定时间断言传送请求信号。每个连接中的优先级仲裁电路在每个总线周期的另一个时间段接收所有这些请求并对它们进行采样。当一个连接正在发送一个请求时，没有更高优先级的连接正在发送一个请求，那个连接就控制了互连。在某些类型的传输期间，可以防止在后续总线周期到另一个连接的传输。

55. 发明授权

US4176341A Information transfer apparatus 失效
标题翻译：信息传送装置
公开(公告)号：US4176341A
公开(公告)日：1979-11-27
申请号：US791186
申请日：1977-04-27
申请人： Michio Miyazaki
发明人： Michio Miyazaki
IPC分类号： G06F3/00 , G06F13/12 , G06F13/378 , H04Q9/00
CPC分类号： G06F13/378 , G06F13/122
摘要： An information transfer apparatus for connecting between plural channels and input/output control devices in a computer system, comprising a bundle of signal lines with which said channels are connected, said bundle of signal lines including plural signal lines provided respectively for said plural channels so as to effect the time-shared connection between said plural channels and input/output control devices therethrough.
摘要翻译：一种用于在计算机系统中连接多个通道和输入/输出控制装置之间的信息传送装置，包括一束与所述通道连接的信号线，所述信号线包括分别为所述多个通道提供的多条信号线，以便以实现所述多个通道与输入/输出控制装置之间的时间共享连接。

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