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51. 发明授权

US06470437B1 Updating and invalidating store data and removing stale cache lines in a prevalidated tag cache design 失效
标题翻译：更新并使存储数据无效，并在预先生效的标签缓存设计中删除过时的高速缓存行
公开(公告)号：US06470437B1
公开(公告)日：2002-10-22
申请号：US09466306
申请日：1999-12-17
申请人： Terry L Lyon
发明人： Terry L Lyon
IPC分类号： G06F1210
CPC分类号： G06F12/1054 , G06F12/0891 , G06F2212/682
摘要： In a computer architecture using a prevalidated tag cache design, logic circuits are added to enable store and invalidation operations without impacting integer load data access times and to invalidate stale cache lines. The logic circuits may include a translation lookaside buffer (TLB) architecture to handle store operations in parallel with a smaller, faster integer load TLB architecture. A store valid module is added to the TLB architecture. The store valid module sets a valid bit when a new cache line is written. The valid bit is cleared on the occurrence of an invalidation operation. The valid bit prevents multiple store updates or invalidates for cache lines that are already invalid. In addition, an invalidation will block load hits on the cache line. A control logic is added to remove stale cache lines. When a cache line fill is being processed, the control logic determines if the cache line exists in any other cache segments. If the cache line exists, the control logic directs the clearing of store valid bits associated with the cache line.
摘要翻译：在使用预验证标签高速缓存设计的计算机体系结构中，添加逻辑电路以实现存储和无效操作，而不影响整数负载数据访问时间，并使陈旧的高速缓存行无效。逻辑电路可以包括用更小，更快的整数负载TLB架构并行地处理存储操作的翻译后备缓冲器（TLB）架构。存储有效模块被添加到TLB架构。存储有效模块在写入新的高速缓存行时设置有效位。发生无效操作时，有效位被清除。有效的位可以防止多个存储更新或无效的高速缓存行已经无效。此外，无效将阻止缓存行上的加载命中。添加一个控制逻辑来删除陈旧的缓存行。当正在处理高速缓存行填充时，控制逻辑确定高速缓存行是否存在于任何其他高速缓存段中。如果存在高速缓存行，则控制逻辑指示清除与高速缓存行相关联的存储有效位。

52. 发明申请

US20020144078A1 Address translation 审中-公开
标题翻译：地址翻译
公开(公告)号：US20020144078A1
公开(公告)日：2002-10-03
申请号：US10086499
申请日：2002-03-01
申请人： SIROYAN LIMITED
发明人： Nigel Peter Topham , Seow Chuan Lim
IPC分类号： G06F012/10
CPC分类号： G06F12/1054
摘要： A processor, and a method of accessing memory in a processor, are disclosed. The processor is arranged to generate virtual addresses for conversion into physical addresses for accessing physical memory, the physical memory comprising a first memory portion (101), and a second memory portion which is part of the same memory level as the first memory portion. When a virtual address is generated, part of that virtual address is converted into a partial physical address and a memory location in the first memory portion (101) is accessed using the partial physical address. In parallel with the memory access, a check may be carried out to determine whether the partial physical address is correct.
摘要翻译：公开了处理器和访问处理器中的存储器的方法。处理器被布置成生成用于转换成用于访问物理存储器的物理地址的虚拟地址，物理存储器包括第一存储器部分（101）和与第一存储器部分相同存储器级别的一部分的第二存储器部分。当生成虚拟地址时，该虚拟地址的一部分被转换为部分物理地址，并且使用部分物理地址访问第一存储器部分（101）中的存储器位置。与存储器访问并行，可以执行检查以确定部分物理地址是否正确。

53. 发明授权

US06353879B1 Memory address translation in a data processing system 有权
标题翻译：数据处理系统中的内存地址转换
公开(公告)号：US06353879B1
公开(公告)日：2002-03-05
申请号：US09252927
申请日：1999-02-19
申请人： Peter Guy Middleton , David Michael Bull
发明人： Peter Guy Middleton , David Michael Bull
IPC分类号： G06F1200
CPC分类号： G06F12/10 , G06F12/1054 , G06F2212/654
摘要： A data processing system 2 is provided with a processor core 4 that issues virtual addresses VA that are translated to mapped addresses MA by an address translation circuit 6 based upon a predicted address mapping. The mapped address MA is used for a memory access within a memory system 8. The mapped address MA starts to be used before a mapping validity circuit 6 has determined whether or not the predicted translation was valid. Accordingly, if the predicted address translation turns out to be invalid, then the memory access is aborted. The state of the processor core is preserved either by stretching the processor clock signal or by continuing the processor clock signal and waiting the processor 4. The memory system 8 then restarts the memory access with the correct translated address.
摘要翻译：数据处理系统2具有处理器核心4，处理器核心4基于预测的地址映射，通过地址转换电路6发布被映射到映射地址MA的虚拟地址VA。映射地址MA用于存储器系统8内的存储器访问。映射地址MA开始在映射有效性电路6确定预测翻译是否有效之前被使用。因此，如果预测的地址转换是无效的，则存储器访问被中止。通过拉伸处理器时钟信号或继续处理器时钟信号并等待处理器4来保留处理器核心的状态。然后，存储器系统8以正确翻译的地址重新启动存储器访问。

54. 发明申请

US20010056517A1 Data processing device 失效
标题翻译：数据处理装置
公开(公告)号：US20010056517A1
公开(公告)日：2001-12-27
申请号：US09753563
申请日：2001-01-04
发明人： Makoto Hataida , Toshiyuki Muta
IPC分类号： G06F012/08
CPC分类号： G06F12/1054 , G06F12/0859
摘要： A calculating part performs calculation. A storing part stores data from the calculating part. An address converting part converts an address corresponding to data requested by the calculating part. A first comparing part compares an address from the address converting part and data stored in the storing part. A second comparing part compares the address corresponding to the data requested by the calculating part with an address of said storing part. A selecting part selects the data stored in the storing part to be provided to the calculating part when an address comparison result of the first comparing part is coincidence and also an address comparison result of the second comparing part is coincidence.
摘要翻译：计算部分进行计算。存储部存储来自计算部的数据。地址转换部分转换与计算部分请求的数据相对应的地址。第一比较部分比较来自地址转换部分的地址和存储在存储部分中的数据。第二比较部分将与计算部分请求的数据对应的地址与所述存储部分的地址进行比较。当第一比较部分的地址比较结果一致时，选择部分选择存储在要提供给计算部分的存储部分中的数据，并且第二比较部分的地址比较结果是一致的。

55. 发明授权

US06301648B1 Method and apparatus for processing memory accesses utilizing a TLB 有权
标题翻译：用于使用TLB处理存储器访问的方法和装置
公开(公告)号：US06301648B1
公开(公告)日：2001-10-09
申请号：US09376824
申请日：1999-08-18
申请人： Paul W. Campbell
发明人： Paul W. Campbell
IPC分类号： G06F1210
CPC分类号： G06F12/1054
摘要： A method and apparatus for processing memory access requests having enhanced functionality includes processing that begins by receiving a memory access request. The process continues by determining whether the memory access request triggers an address caching process to be performed. If so, the address caching process is performed. While performing the address caching process, a determination is made as to whether the address caching processing triggers an exception process to be performed based upon a physical address derived from the address caching process. Such address space requiring further processing includes video graphics address space, restricted memory space, read-only memory space, non-cacheable data memory space, device emulation exceptions memory space, and memory exceptions. When the exception process is triggered during the address caching process, the exception process is performed and the results are cached in an address processing cache.
摘要翻译：用于处理具有增强功能的存储器访问请求的方法和装置包括通过接收存储器访问请求开始的处理。该过程通过确定存储器访问请求是否触发要执行的地址缓存处理来继续。如果是，则执行地址缓存处理。在执行地址缓存处理的过程中，确定地址缓存处理是否基于从地址缓存处理导出的物理地址触发要执行的异常处理。需要进一步处理的这种地址空间包括视频图形地址空间，限制的存储空间，只读存储器空间，不可缓存的数据存储空间，设备仿真异常存储器空间和存储器异常。当在地址缓存过程中触发异常处理时，执行异常处理，并将结果缓存在地址处理高速缓存中。

56. 发明授权

US06286091B1 Microprocessor using TLB with tag indexes to access tag RAMs 失效
标题翻译：使用带标签索引的TLB的微处理器来访问标签RAM
公开(公告)号：US06286091B1
公开(公告)日：2001-09-04
申请号：US09280066
申请日：1999-03-29
申请人： Sung Soo Park
发明人： Sung Soo Park
IPC分类号： G06F1200
CPC分类号： G06F12/1054
摘要： A microprocessor is disclosed, which determines hit/miss by comparing four tag RAMs 5×4 times to improve economical efficiency of a device. The microprocessor includes a first latch for reserving a virtual address whose low bits are identical with a physical address and high bits are different from the physical address; a TLB including TLB indexes having bits smaller than the high bits, for determining hit/miss of the virtual address by receiving the high bits of the virtual address from the first latch; a TLB miss handler for mutually inputting/outputting data with the TLB to produce and store new data in the TLB; a multiplexer for receiving the output of the TLB or the TLB miss handler; a plurality of tag RAMs including CAM cells which stores tag RAM indexes to be compared with the TLB indexes, for selecting the tag RAM indexes corresponding to the low 12 bits of the virtual address; a first comparator for comparing the selected tag RAM indexes with the TLB indexes; a cache miss handler for storing new data in the tag RAMs by receiving the outputs of the multiplexer and the first comparator; data RAMs having the same number of the tag RAMs, for outputting data corresponding to the tag RAM indexes which are identical with the TLB indexes; and a data latch for storing the outputs of the data RAMs and outputting them outside.
摘要翻译：公开了一种微处理器，其通过比较四个标签RAM 5×4次来确定命中/错位，以提高设备的经济效率。微处理器包括第一锁存器，用于保留低位与物理地址相同的虚拟地址，高位不同于物理地址; TLB，其包括具有小于高位的位的TLB索引，用于通过从第一锁存器接收虚拟地址的高位来确定虚拟地址的命中/未命中; TLB未命中处理器，用于与TLB相互输入/输出数据，以在TLB中产生和存储新数据; 用于接收TLB或TLB未命中处理器的输出的多路复用器; 多个标签RAM，包括存储要与TLB索引进行比较的标签RAM索引的CAM单元，用于选择与虚拟地址的低12位对应的标签RAM索引; 用于将所选标签RAM索引与所述TLB索引进行比较的第一比较器; 用于通过接收多路复用器和第一比较器的输出来将新数据存储在标签RAM中的高速缓存未命中处理器; 具有相同数量的标签RAM的数据RAM，用于输出与TLB索引相同的标签RAM索引对应的数据; 以及用于存储数据RAM的输出并将其输出到外部的数据锁存器。

57. 发明授权

US06202128B1 Method and system for pre-fetch cache interrogation using snoop port 失效
标题翻译：使用snoop端口预取缓存询问的方法和系统
公开(公告)号：US06202128B1
公开(公告)日：2001-03-13
申请号：US09038422
申请日：1998-03-11
申请人： Kin Shing Chan , Dwain Alan Hicks , Peichun Peter Liu , Michael John Mayfield , Shih-Hsiung Stephen Tung
发明人： Kin Shing Chan , Dwain Alan Hicks , Peichun Peter Liu , Michael John Mayfield , Shih-Hsiung Stephen Tung
IPC分类号： G06F1208
CPC分类号： G06F12/0862 , G06F12/0831 , G06F12/1054
摘要： An interleaved data cache array which is divided into two subarrays is provided for utilization within a data processing system. Each subarray includes a plurality of cache lines wherein each cache line includes a selected block of data, a parity field, a content addressable field containing a portion of an effective address (ECAM) for the selected block of data, a second content addressable field contains a real address (RCAM) for the selected block of data and a data status field. Separate effective address ports (EA) and a real address port (RA) permit parallel access to the cache without conflict in separate subarrays and a subarray arbitration logic circuit is provided for attempted simultaneous access of a single subarray by both the effective address port (EA) and the real address port (RA). A normal word line is provided and activated by either the effective address port or the real address port through the subarray arbitration. An existing Real Address (RA) cache snoop port is used to check whether a pre-fetching stream's line access is a true cache hit or not. The snoop read access uses a (33-bit) real address to access the data cache without occupying a data port during testing of the pre-fetching stream hits. Therefore, the two Effective Address (EA) accesses and a RCAM snoop access can access the data cache simultaneously thereby increasing pre-fetching performance.
摘要翻译：提供划分为两个子阵列的交错数据高速缓存阵列用于数据处理系统内的利用。每个子阵列包括多条高速缓存线，其中每条高速缓存线包括选定的数据块，奇偶校验字段，包含所选择的数据块的有效地址（ECAM）的一部分的内容可寻址字段，第二内容可寻址字段包含用于所选数据块的实际地址（RCAM）和数据状态字段。分离的有效地址端口（EA）和实际地址端口（RA）允许并行访问高速缓存，而不会在单独的子阵列中发生冲突，并提供子阵列仲裁逻辑电路，用于通过有效地址端口（EA）同时访问单个子阵列）和实际地址端口（RA）。正常字线由有效地址端口或实地址端口通过子阵列仲裁提供和激活。现有的Real Address（RA）缓存侦听端口用于检查预取流的线路访问是否是真正的缓存命中。在测试预取流命中期间，窥探读取访问使用（33位）实地址访问数据高速缓存，而不占用数据端口。因此，两个有效地址（EA）访问和RCAM侦听访问可以同时访问数据高速缓存，从而增加预取性能。

58. 发明授权

US06138223A Absolute address history table index generation for predicting instruction and operand cache accesses 失效
标题翻译：用于预测指令和操作数缓存访问的绝对地址历史表索引生成
公开(公告)号：US06138223A
公开(公告)日：2000-10-24
申请号：US70361
申请日：1998-04-30
申请人： Mark Anthony Check , John Stephen Liptay
发明人： Mark Anthony Check , John Stephen Liptay
IPC分类号： G06F9/32 , G06F9/38 , G06F12/10
CPC分类号： G06F9/3806 , G06F12/0888 , G06F12/1054 , G06F9/322 , G06F9/3826 , G06F9/3832
摘要： A computer processor that uses an AAHT to provide a guess at the real (absolute) address bits used to access the cache and directories that is more accurate in a high-frequency design which prevents any sort of full or large partial adds of ranges of base, index, or displacement has two index values generated and two AAHT arrays, one each for instruction and operand logical requests. It handles cases in which the data is not directly from the GPR array. For designs that aim at improving performance data for some operations that update GPR's may be used for address generation prior to the execution and write to the GPR array, these include data bypass for Load Address (LA) and Load (L). The system handles instruction fetches, relative branches, other special instruction address instruction fetch requests, and those started as a result of a branch history table (BHT) predicted instruction fetch. A method for AAHT synonym resolution improves the accuracy of the index value for an Absolute Address History Table buffer.
摘要翻译：使用AAHT的计算机处理器提供用于访问高速缓存的实际（绝对）地址位和在高频设计中更精确的目录的猜测，其防止基本范围的任何类型的全部或大部分添加，索引或位移具有两个生成的索引值和两个AAHT数组，一个用于指令和操作数逻辑请求。它处理数据不直接来自GPR数组的情况。对于旨在改进性能数据的设计，更新GPR可能会在执行和写入GPR阵列之前产生地址，这些操作包括负载地址（LA）和负载（L）的数据旁路。系统处理指令提取，相对分支，其他特殊指令地址指令取出请求以及作为分支历史表（BHT）预测指令获取结果启动的指令。 AAHT同义词分辨率的方法提高了绝对地址历史记录表缓冲区的索引值的准确性。

59. 发明授权

US6079005A Microprocessor including virtual address branch prediction and current page register to provide page portion of virtual and physical fetch address 失效
标题翻译：微处理器包括虚拟地址分支预测和当前页面寄存器，以提供虚拟和物理提取地址的页面部分
公开(公告)号：US6079005A
公开(公告)日：2000-06-20
申请号：US975224
申请日：1997-11-20
申请人： David B. Witt , Thang M. Tran
发明人： David B. Witt , Thang M. Tran
IPC分类号： G06F9/32 , G06F9/38 , G06F12/10
CPC分类号： G06F9/3806 , G06F12/1054 , G06F9/30058
摘要： A microprocessor employs a branch prediction unit including a branch prediction storage which stores the index portion of branch target addresses and an instruction cache which is virtually indexed and physically tagged. The branch target index (if predicted-taken), or the sequential index (if predicted not-taken) is provided as the index to the instruction cache. The selected physical tag is provided to a reverse translation lookaside buffer (TLB) which translates the physical tag to a virtual page number. Concatenating the virtual page number to the virtual index from the instruction cache (and the offset portion, generated from the branch prediction) results in the branch target address being generated. In one embodiment, a current page register stores the most recently translated virtual page number and the corresponding real page number. The branch prediction unit predicts that each fetch address will continue to reside in the current page and uses the virtual page number from the current page to form the branch Target address. The physical tag from the fetched cache line is compared to the corresponding real page number to verify that the fetch address is actually still within the current page. When a mismatch is detected between the corresponding real page number and the physical tag from the fetched cache line, the branch target address is corrected with the linear page number provided by the reverse TLB and the current page register is updated.
摘要翻译：微处理器采用分支预测单元，该分支预测单元包括分支预测存储器，该分支预测存储器存储分支目标地址的索引部分和虚拟索引并被物理标记的指令高速缓存。提供分支目标索引（如果预测取得）或顺序索引（如果预测未被采用）作为指令高速缓存的索引。所选择的物理标签被提供给反向翻译后备缓冲器（TLB），其将物理标签转换成虚拟页码。将虚拟页号连接到来自指令高速缓存（以及从分支预测生成的偏移部分）的虚拟索引导致生成分支目标地址。在一个实施例中，当前页面寄存器存储最近翻译的虚拟页面号码和相应的真实页面号码。分支预测单元预测每个获取地址将继续驻留在当前页面中，并且使用当前页面中的虚拟页面号来形成分支目标地址。将获取的高速缓存行中的物理标记与相应的实际页码进行比较，以验证提取地址实际上仍在当前页面中。当在相应的实际页码与来自取出的高速缓存行的物理标记之间检测到不匹配时，用反向TLB提供的线性页码修正分支目标地址，并更新当前页寄存器。

60. 发明授权

US6009503A Cache memory indexing using virtual, primary and secondary color indexes 失效
标题翻译：使用虚拟，主和次颜色索引缓存内存索引
公开(公告)号：US6009503A
公开(公告)日：1999-12-28
申请号：US732352
申请日：1996-10-29
申请人： Jochen Liedtke
发明人： Jochen Liedtke
IPC分类号： G06F12/08 , G06F12/10 , G06F12/00
CPC分类号： G06F12/1054 , G06F2212/653
摘要： The memory device comprises a cache memory indexed by the cache index and group information of the virtual address. The physical address translated from the virtual address contains primary and secondary group information. If the tag of the cache entry addressed according to the above standard by indexing of the cache memory corresponds to the physical address, indexing is carried out again using the second group information associated with the physical address (and using the cache index of the virtual address). If the tag of the cache entry thus addressed still does not correspond to the physical address, a cache miss is signaled.
摘要翻译： PCT No.PCT / EP95 / 01471 Sec。 371日期1996年10月29日第 102（e）日期1996年10月29日PCT 1995年4月19日PCT PCT。公开号WO95 / 29445 日期1995年11月2日存储器件包括由缓存索引和虚拟地址的组信息索引的高速缓冲存储器。从虚拟地址转换的物理地址包含主组和辅助组信息。如果根据上述标准通过索引高速缓冲存储器寻址的缓存条目的标签对应于物理地址，则使用与物理地址相关联的第二组信息（并且使用虚拟地址的高速缓存索引）再次执行索引）。如果如此寻址的高速缓存条目的标签仍然不对应于物理地址，则发送高速缓存未命中。

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