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51. 发明申请

US20080265420A1 METHOD OF FORMING A FULLY SILICIDED SEMICONDUCTOR DEVICE WITH INDEPENDENT GATE AND SOURCE/DRAIN DOPING AND RELATED DEVICE 有权
标题翻译：形成具有独立栅极和源/漏极掺杂的完全硅化半导体器件的方法及相关器件
公开(公告)号：US20080265420A1
公开(公告)日：2008-10-30
申请号：US11741540
申请日：2007-04-27
申请人： Shaofeng Yu , Freidoon Mehrad , Jiong-Ping Lu
发明人： Shaofeng Yu , Freidoon Mehrad , Jiong-Ping Lu
IPC分类号： H01L21/3205 , H01L23/48
CPC分类号： H01L21/28097 , H01L29/66507 , H01L29/66545
摘要： A method of forming a fully silicided semiconductor device with independent gate and source/drain doping and related device. At least some of the illustrative embodiments are methods comprising forming a gate stack over a substrate (the gate stack comprising a polysilicon layer and a blocking layer), and performing an ion implantation into an active region of the substrate adjacent to the gate stack (the blocking layer substantially blocks the ion implantation from the polysilicon layer).
摘要翻译：一种形成具有独立栅极和源极/漏极掺杂及相关器件的完全硅化半导体器件的方法。示例性实施例中的至少一些是包括在衬底上形成栅极堆叠的方法（包括多晶硅层和阻挡层的栅极堆叠），以及执行离子注入到与栅极堆叠相邻的衬底的有源区域中阻挡层基本上阻挡从多晶硅层的离子注入）。

52. 发明申请

US20080233747A1 Semiconductor Device Manufactured Using an Improved Plasma Etch Process for a Fully Silicided Gate Flow Process 审中-公开
标题翻译：使用改进的等离子体蚀刻工艺制造的半导体器件用于完全硅化栅流程
公开(公告)号：US20080233747A1
公开(公告)日：2008-09-25
申请号：US11690198
申请日：2007-03-23
申请人： Jinhan Choi , Freidoon Mehrad , Frank S. Johnson
发明人： Jinhan Choi , Freidoon Mehrad , Frank S. Johnson
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/31116 , H01L21/823835
摘要： In one aspect, there us provided a method of manufacturing a semiconductor device that comprises placing an oxide layer over a gate electrode and sidewall spacers located adjacent thereto, placing a protective layer over the oxide layer, conducting a plasma etch to remove portions of the protective layer and the first oxide layer that are located over the gate electrode and expose a surface of the gate electrode, wherein the plasma etch is selective to polysilicon. A soft etch is conducted subsequent to the plasma etch. The soft etch includes an inorganic-based fluorine containing gas and an inert gas, wherein the plasma etch leaves a film on the gate electrode that inhibits silicidation of the gate electrode and wherein the soft etch removes the film. The gate electrode is silicided with a metal subsequent to conducting the soft etch.
摘要翻译：在一个方面，我们提供了一种制造半导体器件的方法，该方法包括将氧化物层放置在栅电极和位于其附近的侧壁间隔物之间，在氧化物层上方放置保护层，进行等离子体蚀刻以去除部分保护层和第一氧化物层，其位于栅电极上方并暴露出栅电极的表面，其中等离子体蚀刻对多晶硅是选择性的。在等离子体蚀刻之后进行软蚀刻。软蚀刻包括无机基含氟气体和惰性气体，其中等离子体蚀刻在栅电极上留下一层膜，其阻止栅电极的硅化，并且其中软蚀刻去除膜。在进行软蚀刻之后，栅极用金属硅化。

53. 发明授权

US07244642B2 Method to obtain fully silicided gate electrodes 有权
公开(公告)号：US07244642B2
公开(公告)日：2007-07-17
申请号：US11228902
申请日：2005-09-16
申请人： Steven A. Vitale , Hyesook Hong , Freidoon Mehrad
发明人： Steven A. Vitale , Hyesook Hong , Freidoon Mehrad
IPC分类号： H01L21/337 , H01L21/336 , H01L21/8234 , H01L21/8238 , H01L21/469 , H01L21/31
CPC分类号： H01L21/823425 , H01L21/823443 , H01L21/823835
摘要： The present invention provides a method of fabricating a microelectronics device. In one aspect, the method comprises depositing a protective layer (510) over a spacer material (415) located over gate electrodes (250) and a doped region (255) located between the gate electrodes (250), removing a portion of the spacer material (415) and the protective layer (510) located over the gate electrodes (250). A remaining portion of the spacer material (415) remains over the top surface of the gate electrodes (250) and over the doped region (255), and a portion of the protective layer (510) remains over the doped region (255). The method further comprises removing the remaining portion of the spacer material (415) to form spacer sidewalls on the gate electrodes (250), expose the top surface of the gate electrodes (250), and leave a remnant of the spacer material (415) over the doped region (255). Source/drains are formed adjacent the gate electrodes 250 and through the remnant of the spacer material (415), and a metal is incorporated into the gate electrodes (250).

54. 发明授权

US07112497B2 Multi-layer reducible sidewall process 有权
标题翻译：多层减薄侧壁工艺
公开(公告)号：US07112497B2
公开(公告)日：2006-09-26
申请号：US10877153
申请日：2004-06-25
申请人： Freidoon Mehrad , Vivian Liu , Amitava Chatterjee
发明人： Freidoon Mehrad , Vivian Liu , Amitava Chatterjee
IPC分类号： H01L21/336
CPC分类号： H01L29/6653 , H01L29/517 , H01L29/6656 , H01L29/7833
摘要： The present invention pertains to a multi-layer sidewall process (100) that facilitates forming a transistor in a manner that allows adherence to certain design rules while concurrently mitigating adverse effects associated with forming areas of transistors close to one another. First sidewall spacers having first widths are formed (124) alongside a gate structure of a transistor to facilitate implanting source/drain dopants far enough away from the gate structure so that dopant atoms are unlikely to migrate into a channel area under the gate structure. Additionally, the process provides uniform layers for dopant atoms to pass through to mitigate variations in device characteristics across a wafer. The manner of forming the sidewall spacers also allows a salicide blocking process to be simplified. The first sidewall spacers are subsequently reduced (132) to establish second sidewall spacers having second widths which are smaller than the first widths. The smaller second sidewall spacers facilitate compliance with design rules by allowing source and drain contacts to be formed closer to the gate structure.
摘要翻译：本发明涉及一种多层侧壁工艺（100），其有助于以允许遵守某些设计规则的方式形成晶体管，同时减轻与形成彼此靠近的晶体管的区域相关联的不利影响。具有第一宽度的第一侧壁间隔物与晶体管的栅极结构一起形成（124），以便于将源极/漏极掺杂剂远离栅极结构注入足够远，使得掺杂剂原子不可能迁移到栅极结构下方的沟道区域中。另外，该工艺为掺杂剂原子提供均匀的层以通过，以减轻跨晶片的器件特性的变化。形成侧壁间隔物的方式也允许简化自对准硅化物封堵过程。随后减小第一侧壁间隔物（132）以建立具有小于第一宽度的第二宽度的第二侧壁间隔物。较小的第二侧壁间隔件通过允许源极和漏极接触形成得更靠近栅极结构而促进了设计规则的符合性。

55. 发明授权

US07078347B2 Method for forming MOS transistors with improved sidewall structures 有权
标题翻译：用于形成改进的侧壁结构的MOS晶体管的方法
公开(公告)号：US07078347B2
公开(公告)日：2006-07-18
申请号：US10383090
申请日：2003-03-06
申请人： Freidoon Mehrad , Scott F. Johnson , Reji K. Koshy
发明人： Freidoon Mehrad , Scott F. Johnson , Reji K. Koshy
IPC分类号： H01L21/311
CPC分类号： H01L29/66507 , H01L21/28518 , H01L21/31116 , H01L29/665 , H01L29/6656
摘要： A gate structure (30) is formed over a semiconductor (10). Sidewall structures (200) of a first width W1 are formed adjacent to the gate structure (30) and source and drain regions (90) are formed in the semiconductor (10). An etch process is performed to reduce the width of the sidewall structure to W2 and silicide regions (110) are then formed adjacent to the sidewall structures (205).
摘要翻译：在半导体（10）上形成栅极结构（30）。形成与栅极结构（30）相邻的第一宽度W 1的侧壁结构（200），并且在半导体（10）中形成源极和漏极区（90）。执行蚀刻工艺以将侧壁结构的宽度减小到W 2 2，然后与侧壁结构（205）相邻形成硅化物区域（110）。

56. 发明授权

US07045410B2 Method to design for or modulate the CMOS transistor threshold voltage using shallow trench isolation (STI) 有权
标题翻译：使用浅沟槽隔离（STI）设计或调制CMOS晶体管阈值电压的方法
公开(公告)号：US07045410B2
公开(公告)日：2006-05-16
申请号：US10899844
申请日：2004-07-27
申请人： Freidoon Mehrad , Amitava Chatterjee
发明人： Freidoon Mehrad , Amitava Chatterjee
IPC分类号： H01L21/762 , H01L21/8238
CPC分类号： H01L21/823878 , H01L21/76237
摘要： A method (200) of forming an isolation structure is disclosed, and includes forming a patterned isolation hard mask layer (206, 212) having an isolation opening associated therewith over a semiconductor body. An implant into the isolation opening is then performed (214), followed by forming an isolation trench (216) in the semiconductor body associated with the isolation opening. The isolation trench is then filled with a dielectric material (218).
摘要翻译：公开了形成隔离结构的方法（200），并且包括在半导体本体上形成具有与其相关联的隔离开口的图案化隔离硬掩模层（206,212）。然后进行到隔离开口中的注入（214），随后在与隔离开口相关联的半导体主体中形成隔离沟槽（216）。隔离沟槽然后用电介质材料（218）填充。

57. 发明申请

US20060065946A1 Multi-doped semiconductor e-fuse 审中-公开
标题翻译：多掺杂半导体电子熔丝
公开(公告)号：US20060065946A1
公开(公告)日：2006-03-30
申请号：US10954926
申请日：2004-09-30
申请人： Freidoon Mehrad , Richard Rouse , Robert Churchill
发明人： Freidoon Mehrad , Richard Rouse , Robert Churchill
IPC分类号： H01L29/00
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a multi-doped semiconductor e-fuse for use in an integrated circuit and a method of manufacture therefore. In one aspect, the semiconductor e-fuse 200 includes a semiconductor body 205 having a neck region 220 interposed a first portion 210 of the semiconductor body 205 and a second portion 215 of the semiconductor body 205. The semiconductor body 205 is doped with opposite type dopants, and a conductive layer 230 is located over and extends across the neck region 220 to electrically connect the first portion 210 with the second portion 215.
摘要翻译：本发明提供一种用于集成电路的多掺杂半导体电子熔断器及其制造方法。在一个方面，半导体电子熔丝200包括半导体本体205，半导体本体205具有插入半导体本体205的第一部分210的颈部区域220和半导体本体205的第二部分215。半导体主体205被掺杂有相反类型的掺杂剂，并且导电层230位于颈部区域220之上并延伸穿过颈部区域220以将第一部分210与第二部分215电连接。

58. 发明申请

US20060057853A1 Thermal oxidation for improved silicide formation 审中-公开
标题翻译：改善硅化物形成的热氧化
公开(公告)号：US20060057853A1
公开(公告)日：2006-03-16
申请号：US10943086
申请日：2004-09-15
申请人： Manoj Mehrotra , Freidoon Mehrad , F. Johnson
发明人： Manoj Mehrotra , Freidoon Mehrad , F. Johnson
IPC分类号： H01L21/461 , B08B6/00 , H01L21/302
CPC分类号： H01L21/28518 , H01L29/665 , H01L29/66545 , H01L29/6656 , H01L29/66636
摘要： An embodiment of the invention is a method for improving the uniformity of silicide 190 in semiconductor wafers 10. The method may include etching source/drain sidewall spacers 150, performing an oxidation of semiconductor wafer 10, and then performing a wet clean of semiconductor wafer 10.
摘要翻译：本发明的一个实施例是一种用于改善半导体晶片10中的硅化物190的均匀性的方法。该方法可以包括蚀刻源极/漏极侧壁间隔物150，执行半导体晶片10的氧化，然后进行半导体晶片10的湿式清洁。

59. 发明申请

US20060024911A1 Method to design for or modulate the CMOS transistor inverse narrow width effect (INWE) using shallow trench isolation (STI) 有权
标题翻译：使用浅沟槽隔离（STI）设计或调制CMOS晶体管反向窄宽度效应（INWE）的方法
公开(公告)号：US20060024911A1
公开(公告)日：2006-02-02
申请号：US10899844
申请日：2004-07-27
申请人： Freidoon Mehrad , Amitava Chatterjee
发明人： Freidoon Mehrad , Amitava Chatterjee
IPC分类号： H01L21/76
CPC分类号： H01L21/823878 , H01L21/76237
摘要： A method (200) of forming an isolation structure is disclosed, and includes forming a patterned isolation hard mask layer (206, 212) having an isolation opening associated therewith over a semiconductor body. An implant into the isolation opening is then performed (214), followed by forming an isolation trench (216) in the semiconductor body associated with the isolation opening. The isolation trench is then filled with a dielectric material (218).
摘要翻译：公开了形成隔离结构的方法（200），并且包括在半导体本体上形成具有与其相关联的隔离开口的图案化隔离硬掩模层（206,212）。然后进行到隔离开口中的注入（214），随后在与隔离开口相关联的半导体主体中形成隔离沟槽（216）。隔离沟槽然后用电介质材料（218）填充。

60. 发明申请

US20050287751A1 Multi-layer reducible sidewall process 有权
标题翻译：多层减薄侧壁工艺
公开(公告)号：US20050287751A1
公开(公告)日：2005-12-29
申请号：US10877153
申请日：2004-06-25
申请人： Freidoon Mehrad , Vivian Liu , Amitava Chatterjee
发明人： Freidoon Mehrad , Vivian Liu , Amitava Chatterjee
IPC分类号： H01L21/302 , H01L21/336 , H01L21/461 , H01L29/51 , H01L29/78
CPC分类号： H01L29/6653 , H01L29/517 , H01L29/6656 , H01L29/7833
摘要： The present invention pertains to a multi-layer sidewall process (100) that facilitates forming a transistor in a manner that allows adherence to certain design rules while concurrently mitigating adverse effects associated with forming areas of transistors close to one another. First sidewall spacers having first widths are formed (124) alongside a gate structure of a transistor to facilitate implanting source/drain dopants far enough away from the gate structure so that dopant atoms are unlikely to migrate into a channel area under the gate structure. Additionally, the process provides uniform layers for dopant atoms to pass through to mitigate variations in device characteristics across a wafer. The manner of forming the sidewall spacers also allows a salicide blocking process to be simplified. The first sidewall spacers are subsequently reduced (132) to establish second sidewall spacers having second widths which are smaller than the first widths. The smaller second sidewall spacers facilitate compliance with design rules by allowing source and drain contacts to be formed closer to the gate structure.
摘要翻译：本发明涉及一种多层侧壁工艺（100），其有助于以允许遵守某些设计规则的方式形成晶体管，同时减轻与形成彼此靠近的晶体管的区域相关联的不利影响。具有第一宽度的第一侧壁间隔物与晶体管的栅极结构一起形成（124），以便于将源极/漏极掺杂剂远离栅极结构注入足够远，使得掺杂剂原子不可能迁移到栅极结构下方的沟道区域中。另外，该工艺为掺杂剂原子提供均匀的层以通过，以减轻跨晶片的器件特性的变化。形成侧壁间隔物的方式也允许简化自对准硅化物封堵过程。随后减小第一侧壁间隔物（132）以建立具有小于第一宽度的第二宽度的第二侧壁间隔物。较小的第二侧壁间隔件通过允许源极和漏极接触形成得更靠近栅极结构而促进了设计规则的符合性。

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