专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

51. 发明授权

US06646350B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US06646350B2
公开(公告)日：2003-11-11
申请号：US09922230
申请日：2001-08-03
申请人： Naotaka Tanaka , Hideo Miura , Yoshiyuki Kado , Ikuo Yoshida , Takahiro Naito
发明人： Naotaka Tanaka , Hideo Miura , Yoshiyuki Kado , Ikuo Yoshida , Takahiro Naito
IPC分类号： H01L2352
CPC分类号： H01L23/562 , H01L21/563 , H01L23/145 , H01L2224/16225 , H01L2224/32225 , H01L2224/73203 , H01L2224/73204 , H01L2924/01078 , H01L2924/01079 , H01L2924/01087 , H01L2924/12044 , H01L2924/00
摘要： In order to realize a semiconductor device and a manufacturing method thereof which can keep with a high reliability an electric connection between each of bump pads formed on LSI chips and each of electrode pads formed on an interconnection substrate, within an guaranteed temperature range, a thermal expansion coefficient of an adhesive (3) is in the range of 20 to 60 ppm, and an elastic modulus of a build-up portion (6) is in the range of 5 to 10 GPa. Further, the build-up portion (6) is constituted by a multi-layer build-up substrate in which buid-up portion a peak value (a glass transition temperature) of a loss coefficient exists within a range of 100° C. to 250° C. and does not exist within a range of 0° C. to 100° C. By setting or selecting the physical properties in the manner disclosed above, it is possible to realize a semiconductor device and a manufacturing method thereof which can keep with a high reliability an electric bonding between the bump pads (2) formed on the LSI chips (1) and the electrode pads (4) on the interconnection substrate (5) within an guaranteed temperature range.
摘要翻译：为了实现能够保持高可靠性的半导体器件及其制造方法，在形成在LSI芯片上的每个凸块焊盘和形成在互连基板上的每个电极焊盘之间的电连接在保证的温度范围内，粘合剂（3）的膨胀系数在20〜60ppm的范围内，积聚部（6）的弹性模量在5〜10GPa的范围内。此外，积存部（6）由多层积层基板构成，在该多层积层基板中，增益部分的损耗系数的峰值（玻璃化转变温度）存在于100℃〜 250℃，并且不存在于0℃至100℃的范围内。通过以上述方式设置或选择物理性质，可以实现可以保持的半导体器件及其制造方法在保证温度范围内，形成在LSI芯片（1）上的凸块焊盘（2）和互连基板（5）上的电极焊盘（4）之间的电连接具有高可靠性。

52. 发明授权

US06635945B1 Semiconductor device having element isolation structure 失效
标题翻译：具有元件隔离结构的半导体器件
公开(公告)号：US06635945B1
公开(公告)日：2003-10-21
申请号：US09580953
申请日：2000-05-30
申请人： Norio Ishitsuka , Hideo Miura , Shuji Ikeda , Yasuko Yoshida , Norio Suzuki , Kozo Watanabe , Kenji Kanamitsu
发明人： Norio Ishitsuka , Hideo Miura , Shuji Ikeda , Yasuko Yoshida , Norio Suzuki , Kozo Watanabe , Kenji Kanamitsu
IPC分类号： H01L2900
CPC分类号： H01L21/76232 , H01L29/0657
摘要： A semiconductor device and process of forming the device are described. The process includes forming a pad oxide film on the circuit-forming side of a semiconductor substrate; forming an oxidation prevention film on the pad oxide film; removing the oxidation prevention film and the pad oxide film at a desired position, thereby exposing the surface of the semiconductor substrate; horizontally recessing the pad oxide film; etching the exposed surface of the semiconductor substrate by isotropic etching; forming a trench to a desired depth, using the oxidation prevention film as a mask; horizontally recessing the pad oxide film; and oxidizing the trench formed in the semiconductor substrate. The produced device has round upper trench edges obtained by conducting isotropic etching of the exposed surface of the semiconductor substrate and horizontally recessing of the pad oxide film before the oxidation of the trench, whereby only one oxidation step is required.
摘要翻译：描述半导体器件和形成器件的工艺。该工艺包括在半导体衬底的电路形成侧上形成衬垫氧化膜; 在衬垫氧化膜上形成氧化防止膜; 在期望的位置除去氧化防止膜和焊盘氧化膜，从而暴露半导体衬底的表面; 使衬垫氧化膜水平地凹陷; 通过各向同性蚀刻蚀刻半导体衬底的暴露表面; 使用氧化防止膜作为掩模，形成期望深度的沟槽; 使衬垫氧化膜水平地凹陷; 以及氧化在半导体衬底中形成的沟槽。所制造的器件具有圆形的上沟槽边缘，其通过对半导体衬底的暴露表面进行各向同性蚀刻并在沟槽氧化之前水平凹陷焊盘氧化膜而获得，由此仅需要一个氧化步骤。

53. 发明授权

US06559027B2 Semiconductor device and process for producing the sme 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US06559027B2
公开(公告)日：2003-05-06
申请号：US09845338
申请日：2001-05-01
申请人： Norio Ishitsuka , Hideo Miura , Shuji Ikeda , Norio Suzuki , Yasushi Matsuda , Yasuko Yoshida , Hirohiko Yamamoto , Masamichi Kobayashi , Akira Takamatsu , Hirofumi Shimizu , Kazushi Fukuda , Shinichi Horibe , Toshio Nozoe
发明人： Norio Ishitsuka , Hideo Miura , Shuji Ikeda , Norio Suzuki , Yasushi Matsuda , Yasuko Yoshida , Hirohiko Yamamoto , Masamichi Kobayashi , Akira Takamatsu , Hirofumi Shimizu , Kazushi Fukuda , Shinichi Horibe , Toshio Nozoe
IPC分类号： H01L2176
CPC分类号： H01L21/76232 , H01L21/76235 , H01L29/78
摘要： A semiconductor device having a highly reliable groove isolation structure with a desired radius of curvature formed at the groove upper edge and without formation of any step, there is produced by reducing the stress generation around the groove upper edge of an element isolation groove on a semiconductor substrate, thereby optimizing the shape of an element isolation groove and making the device finer and improving the device electric characteristics.
摘要翻译：一种半导体器件，其具有高度可靠的凹槽隔离结构，其具有在凹槽上边缘处形成的所需曲率半径，并且不形成任何步骤，通过减小半导体上的元件隔离槽的沟槽上边缘周围的应力产生而产生从而优化元件隔离槽的形状并使器件更精细并提高器件的电气特性。

54. 发明授权

US06452256B1 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US06452256B1
公开(公告)日：2002-09-17
申请号：US09648454
申请日：2000-08-28
申请人： Atsushi Kazama , Akihiro Yaguchi , Hideo Miura
发明人： Atsushi Kazama , Akihiro Yaguchi , Hideo Miura
IPC分类号： H01L23495
CPC分类号： H01L23/53233 , H01L2224/05001 , H01L2224/05008 , H01L2224/05022 , H01L2224/05024 , H01L2224/05548 , H01L2224/05569 , H01L2224/16 , H01L2924/00014 , H01L2924/01079 , H01L2924/01322 , H01L2224/05599 , H01L2224/05099
摘要： A small semiconductor device close in size to a semiconductor chip which prevents warping of semiconductor chips or wafer and delamination of an interface from an interlayer insulating film, both caused by thermal stresses of a rewiring layer. The use of a Cu composite alloy containing 80 vol. % or less of Cu2O, which alloy has a smaller linear thermal expansion coefficient and a smaller elastic modulus than those of pure copper, as a main material of the rewiring layer can reduce the thermal stresses in the rewiring layer, realizing a semiconductor device in which warping of semiconductor chips or wafer and delamination of layers will not easily occur.
摘要翻译：尺寸小于半导体芯片的小半导体器件，其防止半导体芯片或晶片翘曲以及界面与层间绝缘膜的分层，这两者均由重新布线层的热应力引起。使用含有80体积％的Cu复合合金 Cu2O的百分含量以下，该合金具有比纯铜更小的线性热膨胀系数和更小的弹性模量，作为重新布线层的主要材料可以减少重新布线层中的热应力，实现其中半导体芯片或晶片的翘曲和层的分层将不容易发生。

55. 发明授权

US06376905B2 Semiconductor package 有权
标题翻译：半导体封装
公开(公告)号：US06376905B2
公开(公告)日：2002-04-23
申请号：US09767720
申请日：2001-01-24
申请人： Nae Hisano , Hideo Miura
发明人： Nae Hisano , Hideo Miura
IPC分类号： H01L23495
CPC分类号： H01L24/32 , H01L23/49537 , H01L23/49579 , H01L24/48 , H01L24/73 , H01L2224/05599 , H01L2224/29007 , H01L2224/32014 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/48465 , H01L2224/73215 , H01L2224/73265 , H01L2224/85399 , H01L2924/00014 , H01L2924/01004 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01074 , H01L2924/01082 , H01L2924/0132 , H01L2924/10253 , H01L2924/14 , H01L2924/181 , H01L2924/30107 , H01L2924/351 , H01L2924/00 , H01L2924/00012 , H01L2924/01026 , H01L2924/01028 , H01L2924/3512 , H01L2224/45015 , H01L2924/207 , H01L2224/45099
摘要： A resin encapsulated semiconductor package, which uses leads (lead frame), and enhances heat conducting properties and prevents breaking of lengths of bonding wire, reduction in service life of solder joints and crack of a resin while ensuring reliability on strength. A lead material uses a material containing as a main constituent material a composite alloy of Cu2O and Cu, which has a thermal conductivity as high as that of copper alloys having been conventionally used, and which is sintered to have a small linear expansion coefficient as compared with such copper alloys.
摘要翻译：树脂封装的半导体封装，其使用引线（引线框架），并提高导热性能，防止接合线的长度断裂，降低焊点的使用寿命和树脂裂纹，同时确保强度的可靠性。引线材料使用包含Cu2O和Cu的复合合金作为主要构成材料的材料，其具有与常规使用的铜合金相同的导热率，并且烧结成具有较小的线性膨胀系数与这种铜合金。

56. 发明授权

US06326255B1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US06326255B1
公开(公告)日：2001-12-04
申请号：US09675053
申请日：2000-09-29
申请人： Norio Ishitsuka , Hideo Miura , Shuji Ikeda , Yasuko Yoshida , Norio Suzuki , Michimasa Funabashi
发明人： Norio Ishitsuka , Hideo Miura , Shuji Ikeda , Yasuko Yoshida , Norio Suzuki , Michimasa Funabashi
IPC分类号： H01L2126
CPC分类号： H01L21/76224 , Y10S438/978
摘要： A method for manufacturing a semiconductor device includes the steps of (1) forming a pad oxide film of 5 nm or more on a circuit forming surface of a semiconductor substrate; (2) forming an oxidation inhibition film on the pad oxide film; (3) forming grooves of a given depth with the oxidation inhibition film as a mask; (4) receding the pad oxide film; (5) oxidizing the grooves formed on the semiconductor substrate in the range of 0
摘要翻译：一种制造半导体器件的方法包括以下步骤：（1）在半导体衬底的电路形成表面上形成5nm以上的衬垫氧化膜; （2）在衬垫氧化膜上形成氧化抑制膜; （3）以氧化抑制膜为掩模形成给定深度的槽; （4）后退衬垫氧化膜; （5）在氧化气氛为干燥氧化（H2 /O2≈0）的0℃<0.88t-924的范围内对形成在半导体衬底上的沟槽进行氧化，对应于空气中的氧气分压氧分压比为C％，氧化温度为t（℃）; （6）在氧化槽内埋入绝缘膜; （7）除去形成在氧化抑制膜上的埋置绝缘膜; （8）除去形成在半导体衬底的电路形成表面上的氧化抑制膜; 和（9）去除形成在所述半导体衬底的电路形成表面上的衬垫氧化膜。

57. 发明授权

US06289029B1 Solid state laser 失效
标题翻译：固体激光
公开(公告)号：US06289029B1
公开(公告)日：2001-09-11
申请号：US09160347
申请日：1998-09-25
申请人： Chiaki Goto , Hideo Miura
发明人： Chiaki Goto , Hideo Miura
IPC分类号： H01S310
CPC分类号： H01S3/042 , H01S3/025 , H01S3/0401 , H01S3/0405 , H01S3/0621 , H01S3/08031 , H01S3/09415 , H01S3/109
摘要： A solid state laser includes a solid state laser crystal, a pumping source for pumping the laser crystal, a resonator, an enclosed casing which is filled with gas and in which the resonator is contained, and a temperature controller which keeps the resonator at a predetermined temperature. The ratio of the optical length of the gas layer in the resonator to the oscillation wavelength of the solid state laser is set to be not larger than 13600.
摘要翻译：固态激光器包括固体激光晶体，用于泵浦激光晶体的泵浦源，谐振器，填充有气体并且其中包含谐振器的封闭壳体以及将谐振器保持在预定的温度控制器温度。谐振器中的气体层的光学长度与固体激光器的振荡波长的比率被设定为不大于13600。

58. 发明授权

US06284625B1 Method of forming a shallow groove isolation structure 有权
标题翻译：形成浅槽隔离结构的方法
公开(公告)号：US06284625B1
公开(公告)日：2001-09-04
申请号：US09434308
申请日：1999-11-05
申请人： Norio Ishitsuka , Hideo Miura , Shuji Ikeda , Yasuko Yoshida , Norio Suzuki , Michimasa Funabashi
发明人： Norio Ishitsuka , Hideo Miura , Shuji Ikeda , Yasuko Yoshida , Norio Suzuki , Michimasa Funabashi
IPC分类号： H01L2176
CPC分类号： H01L21/76224 , Y10S438/978
摘要： A method for manufacturing a semiconductor device includes the steps of (1) forming a pad oxide film of 5 nm or more on a circuit forming surface of a semiconductor substrate; (2) forming an oxidation inhibition film on the pad oxide film; (3) forming grooves of a given depth with the oxidation inhibition film as a mask; (4) receding the pad oxide film; (5) oxidizing the grooves formed on the semiconductor substrate in the range of 0
摘要翻译：一种制造半导体器件的方法包括以下步骤：（1）在半导体衬底的电路形成表面上形成5nm以上的衬垫氧化膜; （2）在衬垫氧化膜上形成氧化抑制膜; （3）以氧化抑制膜为掩模形成给定深度的槽; （4）后退衬垫氧化膜; （5）在氧化气氛为干燥氧化（H2 /O2≈0）的0℃<0.88t-924的范围内对形成在半导体衬底上的沟槽进行氧化，对应于空气中的氧气分压氧分压比为C％，氧化温度为t（℃）; （6）在氧化槽内埋入绝缘膜; （7）除去形成在氧化抑制膜上的埋置绝缘膜; （8）除去形成在半导体衬底的电路形成表面上的氧化抑制膜; 和（9）去除形成在所述半导体衬底的电路形成表面上的衬垫氧化膜。

59. 发明授权

US06211576B1 Semiconductor device 有权
公开(公告)号：US06211576B1
公开(公告)日：2001-04-03
申请号：US09397853
申请日：1999-09-17
申请人： Hiroya Shimizu , Asao Nishimura , Tosiho Miyamoto , Hideki Tanaka , Hideo Miura
发明人： Hiroya Shimizu , Asao Nishimura , Tosiho Miyamoto , Hideki Tanaka , Hideo Miura
IPC分类号： H01L2348
CPC分类号： H01L24/10 , H01L23/50 , H01L23/5286 , H01L23/552 , H01L23/645 , H01L23/66 , H01L24/13 , H01L2224/05001 , H01L2224/05008 , H01L2224/05022 , H01L2224/05024 , H01L2224/05569 , H01L2224/05571 , H01L2224/05572 , H01L2224/13 , H01L2224/13099 , H01L2224/16 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01077 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/12042 , H01L2924/14 , H01L2924/19041 , H01L2924/30105 , H01L2924/30107 , H01L2924/3025 , H01L2924/00 , H01L2924/00012
摘要： A semiconductor device is provided which is highly reliable and operable at fast speed and low noises. In this semiconductor device, there are provided a power wiring section 1003a, a ground wiring section 1003b and a signal wiring section 1003c are formed on one level. The power wiring section or the ground wiring section is formed adjacently on both sides of at least one part of the signal wiring section.

60. 发明授权

US06187100B1 Semiconductor device and production thereof 有权
标题翻译：半导体器件及其制造
公开(公告)号：US06187100B1
公开(公告)日：2001-02-13
申请号：US09413890
申请日：1999-10-07
申请人： Hideo Miura , Shunji Moribe , Hisayuki Kato , Atsuyoshi Koike , Shuji Ikeda , Asao Nishimura
发明人： Hideo Miura , Shunji Moribe , Hisayuki Kato , Atsuyoshi Koike , Shuji Ikeda , Asao Nishimura
IPC分类号： C23C1600
CPC分类号： H01L21/02667 , C23C16/24 , C23C16/45523 , C23C16/45561 , C23C16/52 , H01L21/02381 , H01L21/02488 , H01L21/02532 , H01L21/02576 , H01L21/02579 , H01L21/02609 , H01L21/0262 , H01L21/28035 , H01L21/28525 , H01L21/28556 , H01L29/045 , H01L29/4916 , H01L29/66757 , H01L31/182 , H01L2924/0002 , Y02E10/546 , Y02P70/521 , H01L2924/00
摘要： A semiconductor device containing a polycrystalline silicon thin film wherein crystal grains of the silicon thin film have mainly a columnar structure and a crystal orientation of individual crystal grains is almost in a uniform direction can be produced by depositing a non-impurity-doped silicon thin film or an impurity layer on an interface of underlying film, followed by deposition of impurity-doped silicon thin film, if necessary, followed by heat treatment for polycrystallization.
摘要翻译：包含多晶硅薄膜的半导体器件可以通过沉积非杂质掺杂的硅薄膜来制造，其中硅薄膜的晶粒主要具有柱状结构和单个晶粒的晶体取向几乎是均匀的方向或下层膜的界面上的杂质层，然后如果需要，沉积杂质掺杂的硅薄膜，然后进行多结晶热处理。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式