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    • 51. 发明申请
    • Coating apparatus and operating method thereof
    • 涂布装置及其操作方法
    • US20070020401A1
    • 2007-01-25
    • US11453869
    • 2006-06-16
    • Jeong ParkSeung LeeSang Jin
    • Jeong ParkSeung LeeSang Jin
    • B05D1/02B05B13/02
    • B05C5/0254B05B12/12B05B12/124B05B15/14B05B15/16B05B15/50B05C5/0208
    • A coating apparatus and an operating method thereof that prevent damage to the nozzle of a spinless coater from impurities on a substrate during resin coating of the substrate, and impurities remaining on a stage at the bottom of the substrate. The coating apparatus comprises a stage, a nozzle, a nozzle cleaner, and a stage cleaner. A substrate is placed upon the stage. The nozzle discharges resin on the substrate to perform coating. The nozzle cleaner cleans the nozzle. The stage cleaner cleans the stage. The operating method includes removing a coated first substrate from atop a stage, cleaning the stage using a stage cleaner, introducing a second substrate to be coated onto the cleaned stage, and discharging resin through a nozzle onto the second substrate and coating the second substrate.
    • 一种涂布装置及其操作方法,其防止在基材的树脂涂覆期间由基材上的杂质损坏无纺涂布机的喷嘴,以及残留在基板底部的载物台上的杂质。 涂布装置包括台,喷嘴,喷嘴清洁器和平台清洁器。 将基材放置在载物台上。 喷嘴将衬底上的树脂排出以进行涂覆。 喷嘴清洁剂清洁喷嘴。 舞台清洁剂清洁舞台。 操作方法包括从台面顶部去除涂覆的第一基板,使用平台清洁器清洁平台,将待涂覆的第二基板引入到清洁的台上,以及将树脂通过喷嘴排出到第二基板上并涂覆第二基板。
    • 57. 发明申请
    • Fin field-effect transistor and method for fabricating the same
    • 翅片场效应晶体管及其制造方法
    • US20060145259A1
    • 2006-07-06
    • US11319263
    • 2005-12-29
    • Jeong Park
    • Jeong Park
    • H01L27/12H01L21/336
    • H01L29/7854H01L29/66795
    • A fin field-effect transistor and a method of fabricating the same provide a fin structure with rounded edges that may prevent a localized thinning of a gate insulating layer formed over the fin structure and to thereby prevent the occurrence of electrical shorts between the fin and a conductive layer formed on the gate insulating layer. The fin field-effect transistor includes an insulating layer formed on an entire surface of a semiconductor substrate where a device isolation layer is formed; a fin formed on the insulating layer, the fin having rounded edges; a gate insulating layer formed on a surface of the fin; and a gate electrode formed on the gate insulating layer to be disposed on three sides of the fin.
    • 翅片场效应晶体管及其制造方法提供具有圆形边缘的鳍结构,其可以防止在鳍结构上形成的栅极绝缘层的局部变薄,从而防止鳍和a之间的电短路的发生 形成在栅极绝缘层上的导电层。 鳍状场效应晶体管包括形成在形成器件隔离层的半导体衬底的整个表面上的绝缘层; 在所述绝缘层上形成的翅片,所述翅片具有圆形边缘; 形成在所述翅片的表面上的栅极绝缘层; 以及形成在所述栅绝缘层上以设置在所述鳍的三侧的栅电极。
    • 60. 发明申请
    • Methods of fabricating MIM capacitors in semiconductor devices
    • 在半导体器件中制造MIM电容器的方法
    • US20050142737A1
    • 2005-06-30
    • US11027524
    • 2004-12-31
    • Jeong Park
    • Jeong Park
    • H01L27/04H01L21/02H01L21/768H01L21/8242H01L23/522H01L27/108H01L21/20
    • H01L21/7681H01L23/5223H01L27/1085H01L27/10897H01L28/91H01L2924/0002H01L2924/00
    • Methods of fabricating an MIM capacitor and a dual damascene structure of a semiconductor device are disclosed. According to one example, a method includes depositing a first insulating layer on a semiconductor substrate; forming a lower interconnect through the first insulating layer; sequentially depositing a second insulating layer, a third insulating layer, and a fourth insulating layer; forming a first mask pattern over the fourth insulating layer; forming a first dual damascene pattern by etching the fourth insulating layer; depositing a fifth insulating layer; forming a second mask pattern over the fifth insulating layer; forming dual damascene structure by performing an etching process; sequentially depositing a second conducting layer and a dielectric layer on the dual damascene structure; selectively removing some portion of the dielectric layer; depositing a third conducting layer over the dielectric layer; and planarizaing the top surface of the third conducting layer, the dielectric layer, and the second conducting layer by performing a CMP process.
    • 公开了制造半导体器件的MIM电容器和双镶嵌结构的方法。 根据一个示例,一种方法包括在半导体衬底上沉积第一绝缘层; 通过所述第一绝缘层形成下互连; 依次沉积第二绝缘层,第三绝缘层和第四绝缘层; 在所述第四绝缘层上形成第一掩模图案; 通过蚀刻第四绝缘层形成第一双镶嵌图案; 沉积第五绝缘层; 在所述第五绝缘层上形成第二掩模图案; 通过进行蚀刻工艺形成双镶嵌结构; 在双镶嵌结构上依次沉积第二导电层和介电层; 选择性地去除介电层的一部分; 在所述电介质层上沉积第三导电层; 并且通过执行CMP处理来平坦化第三导电层,电介质层和第二导电层的顶表面。