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51. 发明授权

US06548856B1 Vertical stacked gate flash memory device 有权
标题翻译：垂直堆叠式门闪存器件
公开(公告)号：US06548856B1
公开(公告)日：2003-04-15
申请号：US09583403
申请日：2000-05-31
申请人： Chrong-Jung Lin , Shui-Hung Chen , Mong-Song Liang
发明人： Chrong-Jung Lin , Shui-Hung Chen , Mong-Song Liang
IPC分类号： H01L29788
CPC分类号： H01L27/11556
摘要： A method of forming a vertical transistor memory device comprises the following process steps. Before forming the trenches, FOX regions are formed between the rows. Then form a set of trenches with sidewalls and a bottom in a semiconductor substrate with threshold implant regions the sidewalls. Form doped drain regions near the surface of the substrate and doped source regions in the base of the device below the trenches with oppositely doped channel regions therebetween. Form a tunnel oxide layer over the substrate including the trenches. Form a blanket thin floating gate layer of doped polysilicon over the tunnel oxide layer extending above the trenches. Etch the floating gate layer leaving upright floating gate strips of the floating gate layer along the sidewalls of the trenches. Form an interelectrode dielectric layer composed of ONO over the floating gate layer and over the tunnel oxide layer. Form a blanket thin control gate layer of doped polysilicon over the interelectrode dielectric layer. Pattern the control gate layer into control gate electrodes. Form spacers adjacent to the sidewalls of the control gate electrode.
摘要翻译：形成垂直晶体管存储器件的方法包括以下处理步骤。在形成沟槽之前，在行之间形成FOX区域。然后在半导体衬底中形成具有侧壁和底部的一组沟槽，其中侧壁具有阈值注入区域。在衬底的表面附近形成掺杂的漏极区域，并且在沟槽底部的器件的底部中的掺杂源极区域之间具有相反掺杂的沟道区域。在包括沟槽的衬底上形成隧道氧化物层。在沟槽上延伸的隧道氧化物层上形成掺杂多晶硅的覆盖薄的浮动栅极层。蚀刻漂浮栅极层，沿着沟槽的侧壁留下浮动栅极层的直立浮栅条。在浮栅层和隧道氧化物层之上形成由ONO组成的电极间电介质层。在电极间电介质层上形成掺杂多晶硅的覆盖薄的控制栅极层。将控制栅层图案化为控制栅电极。形成与控制栅电极的侧壁相邻的间隔物。

52. 发明授权

US06734055B1 Multi-level (4 state/2-bit) stacked gate flash memory cell 有权
标题翻译：多级（4态/ 2位）堆叠门闪存单元
公开(公告)号：US06734055B1
公开(公告)日：2004-05-11
申请号：US10295157
申请日：2002-11-15
申请人： Chrong Jung Lin , Shui-Hung Chen , Hsin-Ming Chen
发明人： Chrong Jung Lin , Shui-Hung Chen , Hsin-Ming Chen
IPC分类号： H01L218238
CPC分类号： H01L27/11521 , H01L21/28273 , H01L29/42324 , H01L29/66825 , H01L29/7887
摘要： A method is provided for forming a highly dense stacked gate flash memory cell with a structure having multi floating gates that can assume 4 states and, therefore, store 2 bits at the same time. This is accomplished by providing a semiconductor substrate having gate oxide formed thereon, and shallow trench isolation and a p-well formed therein. A layer of nitride is next formed over the substrate and an opening formed therein. Polysilicon floating gate spacers are formed in the opening. A dielectric layer is then formed over the floating gates followed by the forming of a control gate. The adjacent nitride layer is then removed leaving a multi-level structure comprising a control gate therebetween multi floating gates with the intervening dielectric layer.
摘要翻译：提供了一种用于形成具有多个浮动栅极的结构的高密度堆叠栅极快闪存储器单元的方法，该浮置栅极可以呈现4个状态，因此同时存储2个位。这通过提供其上形成有栅极氧化物的半导体衬底和浅沟槽隔离以及其中形成的p阱来实现。接着在衬底上形成一层氮化物，并在其中形成一个开口。在开口中形成多晶硅浮栅隔板。然后在浮动栅极上形成电介质层，随后形成控制栅极。然后去除相邻的氮化物层，留下多层结构，其中包括在具有中间介电层的多个浮动栅之间的控制栅极。

53. 发明授权

US06242314B1 Method for fabricating a on-chip temperature controller by co-implant polysilicon resistor 有权
标题翻译：通过共注入多晶硅电阻制造片上温度控制器的方法
公开(公告)号：US06242314B1
公开(公告)日：2001-06-05
申请号：US09161407
申请日：1998-09-28
申请人： Shui-Hung Chen , Chrong Jung Lin , Jiaw-Ren Shih
发明人： Shui-Hung Chen , Chrong Jung Lin , Jiaw-Ren Shih
IPC分类号： H01L2120
CPC分类号： H01L28/20
摘要： A method of manufacturing a on-chip temperature controller by co-implanting P-type and N-type ions into poly load resistors. The N and P type implant dose can be selected to create the desired cut-off temperature. First, a polysilicon layer 30 is formed on a first insulation layer 20. The polysilicon layer 30 is patterning to form a first poly-load resistor 30A and a second poly-load resistor 30B. The first and the second poly-load resistors are connected to a temperature sensor circuit 12. Both p-type and n-type impurity ions are implanted into the polysilicon layer 30. An insulating dielectric layer 40 is formed over the polysilicon layer 30 and the first insulating layer 20. The polysilicon layer is annealed. The contact openings 44 are formed through the ILD dielectric layer 40 exposing portions of the polysilicon layer 30. Contacts 50 to the polysilicon layer 30 thereby forming a first and second poly-load resistors which are used a temperature on-chip sensors. The first and second poly-load resistors can have different implant dose to get the desired cut off temperatures.
摘要翻译：通过将P型和N型离子共注入到多重负载电阻器中来制造片上温度控制器的方法。可以选择N型和P型植入剂量以产生所需的截止温度。首先，在第一绝缘层20上形成多晶硅层30.多晶硅层30被构图以形成第一多重负载电阻器30A和第二多重负载电阻器30B。第一和第二多负载电阻器连接到温度传感器电路12.P型和n型杂质离子都注入到多晶硅层30中。绝缘电介质层40形成在多晶硅层30上，并且第一绝缘层20.多晶硅层退火。接触开口44通过暴露多晶硅层30的部分的ILD电介质层40形成。触头50连接到多晶硅层30，从而形成第一和第二多负载电阻器，其使用温度片上传感器。第一和第二多负载电阻器可以具有不同的植入剂量以获得期望的截止温度。

54. 发明授权

US06225162B1 Step-shaped floating poly-si gate to improve gate coupling ratio for flash memory application 有权
标题翻译：步进形浮动多晶硅栅极，以提高闪存应用的栅极耦合比
公开(公告)号：US06225162B1
公开(公告)日：2001-05-01
申请号：US09347547
申请日：1999-07-06
申请人： Chrong-Jung Lin , Shui-Hung Chen
发明人： Chrong-Jung Lin , Shui-Hung Chen
IPC分类号： H01L21336
CPC分类号： H01L29/42324
摘要： A stacked-gate flash memory cell is provided having step-shaped poly-gates with increased overlap area between them in order to increase the coupling ratio and hence the program speed of the cell. The floating gate is first formed with a step and the intergate dielectric is conformally shaped thereon followed by the forming of the control gate thereon. The increase in the overlap area can be achieved by forming gates with multiply connected surfaces of different shapes.
摘要翻译：提供了堆叠栅极闪存单元，其具有阶梯形多晶硅栅极，它们之间具有增加的重叠面积，以便增加耦合比并因此增加单元的编程速度。浮动栅极首先形成有台阶，并且隔栅电介质保形地形成在其上，随后在其上形成控制栅极。可以通过形成具有不同形状的多重连接表面的门来实现重叠区域的增加。

55. 发明授权

US6087222A Method of manufacture of vertical split gate flash memory device 失效
公开(公告)号：US6087222A
公开(公告)日：2000-07-11
申请号：US35058
申请日：1998-03-05
申请人： Chrong Jung Lin , Shui-Hung Chen , Di-Son Kuo
发明人： Chrong Jung Lin , Shui-Hung Chen , Di-Son Kuo
IPC分类号： H01L21/28 , H01L21/8247 , H01L21/336
CPC分类号： H01L27/11556 , H01L21/28273
摘要： A method of forming a vertical transistor memory device includes the following steps. Before forming the trenches, FOX regions are formed between the rows. Form a set of trenches with sidewalls and a bottom in a semiconductor substrate with threshold implant regions the sidewalls. Form doped drain regions near the surface of the substrate and doped source regions in the base of the device below the trenches with oppositely doped channel regions therebetween. Form a tunnel oxide layer over the substrate including the trenches. Form a blanket thick floating gate layer of doped polysilicon over the tunnel oxide layer filling the trenches and extending above the trenches. Etch the floating gate layer down below the top of the trenches. Form an interelectrode dielectric layer composed of ONO over the floating gate layer and over the tunnel oxide layer. Form a blanket thick control gate layer of doped polysilicon over the interelectrode dielectric layer. Pattern the control gate layer into control gate electrodes. Form spacers adjacent to the sidewalls of the control gate electrode.

56. 发明授权

US6033963A Method of forming a metal gate for CMOS devices using a replacement gate process 有权
标题翻译：使用替代栅极工艺形成用于CMOS器件的金属栅极的方法
公开(公告)号：US6033963A
公开(公告)日：2000-03-07
申请号：US385523
申请日：1999-08-30
申请人： Jenn Ming Huang , Chi-Wen Su , Chung-Cheng Wu , Shui-Hung Chen
发明人： Jenn Ming Huang , Chi-Wen Su , Chung-Cheng Wu , Shui-Hung Chen
IPC分类号： H01L21/336 , H01L21/768 , H01L29/49
CPC分类号： H01L29/6659 , H01L21/76838 , H01L29/4966 , H01L29/66545
摘要： A method of forming a metal gate for a CMOS device using a replacement gate process wherein sidewall spacers are formed on a dummy electrode prior to forming the metal gate allowing source and drain formation prior to metal gate formation and a tungsten layer is selectively deposited to act as an each or CMP stop and to reduce source and drain resistance. The process begins by forming a dummy gate oxide layer and a polysilicon dummy gate electrode layer on a substrate structure and patterning them to form a dummy gate. Lightly doped source and drain regions are formed by ion implantation using the dummy gate as an implant mask. Spacers are formed on the sidewalls of the dummy gate. Source and drain regions are formed by implanting ions using,the dummy gate and spacers as an implant mask and performing a rapid thermal anneal. A tungsten layer is selectively deposited on the dummy gate electrode and the source and drain regions. A blanket dielectric layer is formed over the dummy gate and the substrate structure. The blanket dielectric layer is planarized using a chemical mechanical polishing process stopping on the tungsten layer. The tungsten layer overlying the dummy gate and the dummy gate are removed, thereby forming a gate opening. A gate oxide layer and a metal gate electrode layer are formed in the gate opening. The gate electrode layer is planarized to form a metal gate, stopping on the blanket dielectric layer. Alternatively, the dummy gate electrode can be composed of silicon nitride and the selectively deposited tungsten layer can be omitted.
摘要翻译：使用替代栅极工艺形成用于CMOS器件的金属栅极的方法，其中在形成金属栅极之前在虚设电极上形成侧壁间隔物，其允许在金属栅极形成之前的源极和漏极形成以及选择性地沉积钨层以起作用作为每个或CMP停止并减少源极和漏极电阻。该过程开始于在衬底结构上形成虚拟栅极氧化物层和多晶硅虚拟栅极电极层并将其图案化以形成虚拟栅极。通过使用伪栅极作为注入掩模的离子注入形成轻掺杂源极和漏极区域。隔板形成在虚拟门的侧壁上。通过使用伪栅极和间隔物作为注入掩模注入离子并执行快速热退火来形成源区和漏区。钨层被选择性地沉积在虚拟栅极电极和源极和漏极区域上。在伪栅极和衬底结构之上形成覆盖层的介电层。使用在钨层上停止的化学机械抛光工艺来平坦化覆盖绝缘层。覆盖虚拟栅极和虚拟栅极的钨层被去除，从而形成栅极开口。栅极氧化层和金属栅极电极层形成在栅极开口中。栅极电极层被平坦化以形成金属栅极，停止在覆盖电介质层上。或者，伪栅电极可以由氮化硅构成，并且可以省略选择性沉积的钨层。

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