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51. 发明授权

US6127737A Semiconductor device and manufacturing method thereof 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US6127737A
公开(公告)日：2000-10-03
申请号：US943520
申请日：1997-10-03
申请人： Takashi Kuroi , Katsuyuki Horita , Maiko Sakai , Yasuo Inoue
发明人： Takashi Kuroi , Katsuyuki Horita , Maiko Sakai , Yasuo Inoue
IPC分类号： H01L21/76 , H01L21/762 , H01L21/8242 , H01L27/108 , H01L23/544
CPC分类号： H01L21/76232 , H01L21/76229
摘要： In a semiconductor device with a trench-type element isolation structure, alignment can be performed with high accuracy without any deterioration in device performance. The surfaces of silicon oxide films (2B, 2C) embedded in trenches (10B, 10C) of an element forming region including a memory cell region (11B) and a peripheral circuit region (11C) in a semiconductor substrate (1), respectively, are almost level with the surface of the semiconductor substrate (1). On the other hand, the surface of a silicon oxide film (2A) embedded in a trench (10A) is formed lower than the surface of the semiconductor substrate (1).
摘要翻译：在具有沟槽型元件隔离结构的半导体器件中，可以高精度地进行对准，而不会使器件性能下降。分别在半导体衬底（1）中嵌入包括存储单元区域（11B）的元件形成区域和外围电路区域（11C）的沟槽（10B，10C）中的氧化硅膜（2B，2C）的表面，几乎与半导体衬底（1）的表面一致。另一方面，嵌入在沟槽（10A）中的氧化硅膜（2A）的表面形成为低于半导体衬底（1）的表面。

52. 发明授权

US5841171A SOI Semiconductor devices 失效
标题翻译： SOI半导体器件
公开(公告)号：US5841171A
公开(公告)日：1998-11-24
申请号：US746951
申请日：1996-11-18
申请人： Toshiaki Iwamatsu , Takashi Ipposhi , Yasuo Inoue
发明人： Toshiaki Iwamatsu , Takashi Ipposhi , Yasuo Inoue
IPC分类号： H01L21/316 , H01L21/76 , H01L21/762 , H01L21/84 , H01L27/12 , H01L29/786 , H01L29/00
CPC分类号： H01L21/84 , H01L27/1203 , H01L29/78609 , H01L29/78654
摘要： In forming an element isolating region in a silicon semiconductor layer of an SOI substrate, a silicon nitride film of a predetermined thickness is deposited over an oxide film formed on a SOI layer. The silicon nitride film is patterned in a design size of active regions, and side walls of a silicon nitride film are formed on the side surfaces of the patterned silicon nitride film. A first LOCOS process is carried out using the nitride film as an oxidation mask. A LOCOS film formed by the first LOCOS process is removed to form narrower concavities under the side walls. Then, another silicon nitride film is deposited, and is removed leaving portions thereof forming the concavities. Then, a second LOCOS process is carried out to form a LOCOS film as an element isolating region. The second LOCOS process uses the oxidation mask having the narrow cavities, so that stress at the boundary of the active region and the element isolation region is reduced, and the growth of bird's beaks can be suppressed.
摘要翻译：在形成SOI衬底的硅半导体层中的元件隔离区域时，在形成于SOI层上的氧化物膜上沉积预定厚度的氮化硅膜。以活性区域的设计尺寸对氮化硅膜进行构图，并且在图案化的氮化硅膜的侧表面上形成氮化硅膜的侧壁。使用氮化物膜作为氧化掩模进行第一LOCOS工艺。去除由第一LOCOS工艺形成的LOCOS膜，以在侧壁下形成更窄的凹面。然后，沉积另一个氮化硅膜，并除去形成凹部的部分。然后，进行第二LOCOS工艺以形成LOCOS膜作为元件隔离区。第二LOCOS工艺使用具有窄腔的氧化掩模，使得有源区域和元件隔离区域的边界处的应力减小，并且可以抑制鸟喙的生长。

53. 发明授权

US5641980A Device having a high concentration region under the channel 失效
标题翻译：在通道下具有高浓度区域的奇偶装置
公开(公告)号：US5641980A
公开(公告)日：1997-06-24
申请号：US557558
申请日：1995-11-14
申请人： Yasuo Yamaguchi , Hans-Oliver Joachim , Yasuo Inoue
发明人： Yasuo Yamaguchi , Hans-Oliver Joachim , Yasuo Inoue
IPC分类号： H01L29/40 , H01L21/336 , H01L27/12 , H01L29/417 , H01L29/78 , H01L29/786
CPC分类号： H01L29/66757 , H01L27/1203 , H01L29/78606 , H01L29/78609 , H01L29/78621
摘要： It is an object to obtain a semiconductor device with the LDD structure having both operational stability and high speed and a manufacturing method thereof. A high concentration region (11) with boron of about 1.times.10.sup.18 /cm.sup.3 introduced therein is formed extending from under a channel formation region (4) to under a drain region (6) and a source region (6') in a silicon substrate (1). The high concentration region (11) is formed in the surface of the silicon substrate (1) under the channel formation region (4), and is formed at a predetermined depth from the surface of the silicon substrate (1) under the drain region (6) and the source region (6'). A low concentration region (10) is formed in the surface of the silicon substrate (1) under the drain region (6) and the source region (6'). The formation of the high concentration region only in the surface of the semiconductor substrate under the channel formation region surely suppresses an increase in the leakage current and an increase in the drain capacitance.
摘要翻译：本发明的目的是获得具有操作稳定性和高速度的LDD结构的半导体器件及其制造方法。导入其中引入了约1×10 18 / cm 3的硼的高浓度区域（11）形成在沟道形成区域（4）下方延伸到漏极区域（6）下方的硅衬底（1）中的源极区域（6'））。在硅衬底（1）的沟道形成区域（4）的表面上形成高浓度区域（11），并且形成在与硅衬底（1）的漏极区域 6）和源极区（6'）。在漏极区域（6）和源极区域（6'）的下方的硅衬底（1）的表面中形成低浓度区域（10）。仅在沟道形成区域的半导体衬底的表面形成高浓度区域确实地抑制了漏电流的增加和漏极电容的增加。

54. 发明授权

US5640600A Storage controller and bus control method for use therewith 失效
标题翻译：存储控制器和总线控制方法
公开(公告)号：US5640600A
公开(公告)日：1997-06-17
申请号：US381560
申请日：1995-01-31
申请人： Takao Satoh , Hisaharu Takeuchi , Yasuo Inoue , Akira Yamamoto
发明人： Takao Satoh , Hisaharu Takeuchi , Yasuo Inoue , Akira Yamamoto
IPC分类号： G06F13/16 , G06F3/06 , G06F11/34 , G06F13/12 , G06F13/36 , H01J3/00
CPC分类号： G06F13/124 , G06F11/349 , G06F11/3409 , G06F2201/88 , G06F2201/885
摘要： A storage controller comprising a storage device adapter, a channel adapter, a cache memory, a control memory, and a plurality of buses connecting therebetween. The channel adapter communicates with a processor and processes input/output requests issued by the processor. The storage device adapter controls a storage device and data transfer between the storage device and the cache memory. The channel adapter and the storage device adapter exchanges control information via the control memory. The buses are used to transfer the data and the control information between the cache memory and the control memory, and the channel adapter and the storage device adapter. The controller also comprises bus load estimating means and bus mode selecting means. The bus load estimating means estimates bus load characteristics as an index based on the amount of data transfer during sequential access to the storage device. The bus mode selecting means determines a bus mode of bus utilization based on the index. Each of the channel adapter and the storage device adapter has bus access means for accessing the buses in accordance with the bus mode selected by the bus mode selecting means.
摘要翻译：存储控制器，包括存储设备适配器，信道适配器，高速缓冲存储器，控制存储器以及连接在它们之间的多个总线。信道适配器与处理器通信并处理由处理器发出的输入/输出请求。存储设备适配器控制存储设备和存储设备与高速缓冲存储器之间的数据传输。通道适配器和存储设备适配器通过控制存储器交换控制信息。总线用于将数据和控制信息传输到缓存存储器和控制存储器之间，以及通道适配器和存储设备适配器。控制器还包括总线负载估计装置和总线模式选择装置。总线负载估计装置基于在顺序访问存储设备期间的数据传输量来估计总线负载特性作为索引。总线模式选择装置根据该索引确定总线利用的总线模式。每个通道适配器和存储设备适配器具有总线访问装置，用于根据由总线模式选择装置选择的总线模式访问总线。

55. 发明授权

US5459856A System having independent access paths for permitting independent access from the host and storage device to respective cache memories 失效
标题翻译：具有用于允许从主机和存储设备到相应高速缓冲存储器的独立访问的独立访问路径的系统
公开(公告)号：US5459856A
公开(公告)日：1995-10-17
申请号：US984763
申请日：1992-12-03
申请人： Yasuo Inoue
发明人： Yasuo Inoue
IPC分类号： G06F3/06 , G06F3/00 , G06F12/08 , G06F13/12 , G06F13/14 , G06F13/38 , G11C29/00 , G06F11/20
CPC分类号： G06F3/0601 , G06F12/0866 , G06F3/061 , G06F3/0656 , G06F3/0658 , G06F3/0689 , G11C29/006 , H04L67/1097 , G06F2003/0692
摘要： A plurality of independent cache units and nonvolatile memory units are provided in a disk controller located between a host (central processing unit) and a magnetic disk drive. A plurality of channel units for controlling the data transfer to and from the central processing unit and a plurality of control units for controlling the data transfer to and from the magnetic disk drive are independently connected to the cache units and the nonvolatile memory units through data buses and access lines.
摘要翻译：在位于主机（中央处理单元）和磁盘驱动器之间的盘控制器中提供多个独立高速缓存单元和非易失性存储器单元。用于控制来自中央处理单元的数据传送的多个通道单元和用于控制与磁盘驱动器的数据传送的多个控制单元通过数据总线独立地连接到高速缓存单元和非易失性存储器单元和接入线路。

56. 发明授权

US5340645A Potassium hexatitanate fibers having tunnel structure, process for producing the same, and composite material containing said fibers 失效
标题翻译：具有隧道结构的六钛酸钾纤维，其制造方法和含有所述纤维的复合材料
公开(公告)号：US5340645A
公开(公告)日：1994-08-23
申请号：US24832
申请日：1993-03-02
申请人： Hidefumi Harada , Yasuo Inoue
发明人： Hidefumi Harada , Yasuo Inoue
IPC分类号： C01G23/00 , C08K7/00 , C08K7/08 , C08L101/00 , C22C47/00 , C22C49/00 , C22C49/04 , C22C49/06 , D01F9/08 , B32B5/02 , C04B35/02
CPC分类号： D01F9/08 , C01G23/005 , C01P2004/10 , C01P2004/61 , C01P2006/60 , Y10T428/24994 , Y10T428/249948 , Y10T428/294 , Y10T428/2975 , Y10T428/31507 , Y10T428/31678
摘要： Potassium hexatitanate fibers having a tunnel structure and a free potassium content of 5 ppm or less can be produced by mixing together a titanium containing compound and a potassium containing compound in a ratio represented by the formula K.sub.2 O.nTiO.sub.2 (wherein n=from 2 to 4); firing the mixture at 900.degree. to 1,200.degree. C. to produce mass of potassium titanate fibers; dipping the mass of product in either cold or hot water to disintegrate the mass of potassium titanate fibers into individual single fibers; adding an acid to the slurry to adjust the pH value to 9.3-9.7, thereby changing the composition of the potassium titanate fibers so that the molar ratio of TiO.sub.2 /K.sub.2 O is in the range of from 5.95 to 6.00; heating the fibers at 950.degree. to 1,150.degree. C. for 1 hour or more; and washing the fibers with an acid. The potassium hexatitanate fibers, which have a minimal free potassium content, i.e., 5 ppm or less, can be suitably used as a reinforcing material for polyester thermoplastic resins, polyphenylene sulfide resins, liquid crystal polymers, aluminum alloys, magnesium alloys and so forth, all of which are easily affected by free potassium.
摘要翻译：通过将含钛化合物和含钾化合物以通式K 2 O·nTiO 2（其中n = 2〜4）表示的比例混合在一起，可以制备具有隧道结构和游离钾含量为5ppm以下的六钛酸钾纤维）; 在900〜1200℃下烧成混合物，生成钛酸钾纤维; 将产品的质量浸入冷或热水中以将钛酸钾纤维的质量分解成单个单根纤维; 向浆料中加入酸以将pH值调节至9.3-9.7，从而改变钛酸钾纤维的组成，使得TiO 2 / K 2 O的摩尔比在5.95至6.00的范围内; 在950〜1150℃下加热纤维1小时以上; 并用酸洗涤纤维。具有最小游离钾含量（即5ppm以下）的六钛酸钾纤维可以适合用作聚酯热塑性树脂，聚苯硫醚树脂，液晶聚合物，铝合金，镁合金等的增强材料，所有这些都容易受到游离钾的影响。

57. 发明授权

US5283455A Thin film field effect element having an LDD structure 失效
标题翻译：具有LDD结构的薄膜场效应元件
公开(公告)号：US5283455A
公开(公告)日：1994-02-01
申请号：US911582
申请日：1992-07-10
申请人： Yasuo Inoue , Tadashi Nishimura , Motoi Ashida
发明人： Yasuo Inoue , Tadashi Nishimura , Motoi Ashida
IPC分类号： H01L29/78 , H01L21/336 , H01L29/786 , H01L29/76 , H01L27/01 , H01L29/94 , H01L31/062
CPC分类号： H01L29/6675 , H01L29/66765 , H01L29/78624 , H01L29/78642
摘要： An upper insulating layer is formed on an upper surface of a gate electrode formed on an insulating substrate. A gate insulating layer is formed on sidewalls of the gate electrode and the surfaces of the upper insulating layer. A semiconductor layer is formed on the surfaces of the gate insulating layer. Three source/drain regions are formed in the semiconductor layer. Two independent channel regions are formed in the semiconductor layer along both side surfaces of the gate electrode. Source/drain regions are arranged on both ends of two channel regions. Each source/drain region has an LDD structure formed in a self alignment manner by an oblique ion implantation method and a vertical ion implantation method using sidewall insulating layers formed on the channel regions as masks.
摘要翻译：在绝缘基板上形成的栅电极的上表面上形成上绝缘层。栅极绝缘层形成在栅电极的侧壁和上绝缘层的表面上。在栅极绝缘层的表面上形成半导体层。在半导体层中形成三个源/漏区。沿着栅电极的两个侧表面在半导体层中形成两个独立的沟道区。源极/漏极区域布置在两个沟道区域的两端。每个源极/漏极区域具有通过倾斜离子注入方法以自对准方式形成的LDD结构和使用在沟道区上形成的侧壁绝缘层作为掩模的垂直离子注入方法。

58. 发明授权

US5128732A Stacked semiconductor device 失效
标题翻译：堆叠半导体器件
公开(公告)号：US5128732A
公开(公告)日：1992-07-07
申请号：US199439
申请日：1988-05-27
申请人： Kazuyuki Sugahara , Tadashi Nishimura , Shigeru Kusunoki , Yasuo Inoue , Yasuo Yamaguchi
发明人： Kazuyuki Sugahara , Tadashi Nishimura , Shigeru Kusunoki , Yasuo Inoue , Yasuo Yamaguchi
IPC分类号： H01L27/06
CPC分类号： H01L27/0688
摘要： A stacked semiconductor device has three-dimensional alternate layers of iconductor elements and insulating layers each electrically insulating the adjacent upper and lower layers of semiconductor elements, formed on a single crystal semiconductor substrate. A semiconductor is deposited in openings formed respectively in the insulating layers to form single crystal semiconductor layers each having the same crystal axis as the single crystal semiconductor substrate respectively over the insulating layers, and semiconductor elements are formed respectively in a plurality of layers. The opening formed through the upper insulating layer reaches the lower layer of the semiconductor element immediately below the same upper insulating layer, and is formed at a position spaced apart horizontally from the opening formed through the lower insulating layer immediately below the same upper insulating layer. A semiconductor for forming the upper layer of a semiconductor having the same crystal axis as the lower layer of a semiconductor is deposited in the opening of the upper insulating layer so that satisfactory lateral epitaxial growth will occur over the insulating layer.
摘要翻译：叠层半导体器件具有三维交替层的半导体元件和绝缘层，每个绝缘层将形成在单晶半导体衬底上的相邻的半导体元件的上层和下层电绝缘。分别在绝缘层中形成的开口中沉积半导体，以形成分别在绝缘层上分别与单晶半导体衬底相同的晶轴的单晶半导体层，并分别形成多个半导体元件。通过上绝缘层形成的开口到达同一上绝缘层正下方的半导体元件的下层，并形成在与通过同一上绝缘层正下方的下绝缘层形成的开口水平间隔开的位置处。用于形成具有与半导体的下层相同的晶轴的半导体的上层的半导体被沉积在上绝缘层的开口中，使得在绝缘层上将发生令人满意的横向外延生长。

59. 发明授权

US5083225A Digital signal recording and playback apparatus 失效
标题翻译：数字信号记录和播放装置
公开(公告)号：US5083225A
公开(公告)日：1992-01-21
申请号：US310530
申请日：1989-02-15
申请人： Kazuhiko Morisaki , Yasuo Inoue
发明人： Kazuhiko Morisaki , Yasuo Inoue
IPC分类号： G11B5/09 , G11B5/008 , G11B5/53 , G11B15/12 , G11B15/18 , G11B15/467 , G11B27/032
CPC分类号： G11B5/0086 , G11B15/125 , G11B15/1875 , G11B15/4671 , G11B27/032 , G11B5/534 , G11B2220/90 , G11B2220/913
摘要： A digital signal recording and playback apparatus having a rotary heads mounted on a rotary drum capable of recording/reproducing a digital signal onto/from a magnetic tape at a tape speed which is N times as much as the standard speed while conforming to the standard track angle and length. The number of the rotary heads are increased from the standard two heads whereas the drum speed is made one half of N times standard speed and the drum diameter is made slightly larger from the standard so that the relative speed between the running tape and the rotating heads becomes equal to the standard in the double tape speed mode, and becomes twice that in the quadruple tape speed mode. Alternatively, the tape is wound around the drum having two heads, over the angular range of 180 degrees instead of the standard 90 degrees, the drum diameter is made smaller than the standard, and the drum speed is N times the standard so that the relative speed of the heads becomes equal to the standard in the double tape speed mode.
摘要翻译：一种数字信号记录和重放装置，其具有安装在旋转磁鼓上的旋转磁头，其能够以符合标准磁道的标准速度的N倍的磁带速度将数字信号记录到磁带上/从磁带重放数字信号角度和长度。旋转头的数量从标准的两个头增加，而鼓速度是标准速度的N倍的一半，并且鼓的直径从标准形成为稍大，使得行走带和旋转头之间的相对速度变为双带速度模式中的标准，并且变为四倍速带速度模式下的两倍。或者，磁带卷绕在具有两个磁头的磁鼓上，角度范围为180度，而不是标准90度，磁鼓直径小于标准，鼓速度是标准的N倍，使得相对磁头速度等于双磁带速度模式下的标准。

60. 发明授权

US5001539A Multiple layer static random access memory device 失效
标题翻译：多层静态随机存取存储器件
公开(公告)号：US5001539A
公开(公告)日：1991-03-19
申请号：US337702
申请日：1989-04-13
申请人： Yasuo Inoue , Tadashi Nishimura
发明人： Yasuo Inoue , Tadashi Nishimura
IPC分类号： G11C11/412 , H01L21/8244 , H01L27/00 , H01L27/06 , H01L27/11
CPC分类号： H01L27/1104 , H01L27/0688 , H01L27/1108 , Y10S257/903
摘要： A stacked static random access memory SRAM having a plurality of memory cells is disclosed. Individual memory cell has a portion formed in an upper active element layer in the device structure and a portion formed in a lower active element layer in the device structure separated from the upper layer by an intermediate insulating layer. A word line, a bit line and access transistors are formed in the same upper active element layer, eliminating the need for interconnecting them through the insulating layer. The elimination of the inter-layer connections helps to reduce the number of through-holes required to be made in the insulating layer. This in turn reduces the area to be occupied by the memory cell and leads to a simplified manufacturing process of the SRAM.
摘要翻译：公开了一种具有多个存储单元的堆叠静态随机存取存储器SRAM。单个存储单元具有形成在器件结构中的上有源元件层中的部分，以及通过中间绝缘层与器件结构中的下有源元件层中形成的部分形成在上层中的部分。在相同的上部有源元件层中形成字线，位线和存取晶体管，消除了通过绝缘层将它们互连的需要。层间连接的消除有助于减少在绝缘层中制造的通孔的数量。这又减少了由存储器单元占用的面积，并导致了SRAM的简化制造过程。

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