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51. 发明申请

US20100039869A1 MULTI-STATE MEMORY CELL WITH ASYMMETRIC CHARGE TRAPPING 有权
标题翻译：具有不对称电荷捕获的多状态存储单元
公开(公告)号：US20100039869A1
公开(公告)日：2010-02-18
申请号：US12581674
申请日：2009-10-19
申请人： Kirk Prall
发明人： Kirk Prall
IPC分类号： G11C16/04
CPC分类号： H01L29/7887 , H01L29/7923
摘要： A multi-state NAND memory cell is comprised of two drain/source areas in a substrate. An oxide-nitride-oxide structure is formed above the substrate between the drain/source areas. The nitride layer acting as an asymmetric charge trapping layer. A control gate is located above the oxide-nitride-oxide structure. An asymmetrical bias on the drain/source areas causes the drain/source area with the higher voltage to inject an asymmetric distribution hole by gate induced drain leakage injection into the trapping layer substantially adjacent that drain/source area.
摘要翻译：多态NAND存储单元由衬底中的两个漏极/源极区域组成。在漏极/源极区域之间的衬底上方形成氧化物 - 氮化物 - 氧化物结构。用作不对称电荷捕获层的氮化物层。控制栅极位于氧化物 - 氮化物 - 氧化物结构之上。在漏极/源极区域上的不对称偏置导致具有较高电压的漏极/源极区域通过栅极感应漏极漏极注入到基本上邻近该漏极/源极区域的俘获层而注入不对称分布孔。

52. 发明授权

US07517749B2 Method for forming an array with polysilicon local interconnects 有权
标题翻译：用多晶硅局部互连形成阵列的方法
公开(公告)号：US07517749B2
公开(公告)日：2009-04-14
申请号：US11217946
申请日：2005-09-01
申请人： Chun Chen , Guy Blalock , Graham Wolstenholme , Kirk Prall
发明人： Chun Chen , Guy Blalock , Graham Wolstenholme , Kirk Prall
IPC分类号： H01L21/8238
CPC分类号： H01L27/11521 , H01L21/76895 , H01L27/115
摘要： Methods and apparatus are described to facilitate forming memory devices with low resistance polysilicon local interconnects that allow a smaller array feature size and therefore facilitate forming arrays of a denser array format. Embodiments of the present invention are formed utilizing a wet etch process that has a high selectivity, allowing the deposition and etching of polysilicon local interconnects to source regions of array transistors. By providing for a local interconnect of polysilicon, a smaller source region and/or drain region can also be utilized, further decreasing the required word line spacing. Low resistance polysilicon local source interconnects can also couple to an increased number of memory cells, thereby reducing the number of contacts made to an array ground.
摘要翻译：描述了方法和装置以便于形成具有低电阻多晶硅局部互连的存储器件，其允许更小的阵列特征尺寸，并因此促进形成更密集阵列格式的阵列。使用具有高选择性的湿蚀刻工艺形成本发明的实施例，允许将多晶硅局部互连件沉积和蚀刻到阵列晶体管的源极区域。通过提供多晶硅的局部互连，还可以利用更小的源极区和/或漏极区，进一步减少所需的字线间隔。低电阻多晶硅本地源极互连还可以耦合到增加数量的存储器单元，从而减少对阵列地阵进行的触点的数量。

53. 发明申请

US20090072303A9 NROM MEMORY CELL, MEMORY ARRAY, RELATED DEVICES AND METHODS 有权
标题翻译： NROM存储单元，存储阵列，相关设备和方法
公开(公告)号：US20090072303A9
公开(公告)日：2009-03-19
申请号：US11346049
申请日：2006-02-02
申请人： Kirk Prall , Leonard Forbes
发明人： Kirk Prall , Leonard Forbes
IPC分类号： H01L29/94
CPC分类号： H01L29/7926 , G11C11/5692 , G11C16/0466 , G11C16/0475 , H01L27/11556 , H01L27/11582 , H01L29/7889 , H01L29/7923
摘要： An array of memory cells configured to store at least one bit per one F2 includes substantially vertical structures providing an electronic memory function spaced apart a distance equal to one half of a minimum pitch of the array. The structures providing the electronic memory function are configured to store more than one bit per gate. The array also includes electrical contacts to the memory cells including the substantially vertical structures. The cells can be programmed to have one of a number of charge levels trapped in the gate insulator adjacent to the first source/drain region such that the channel region has a first voltage threshold region (Vt1) and a second voltage threshold region (Vt2) and such that the programmed cell operates at reduced drain source current.
摘要翻译：配置为存储每个F2的至少一个位的存储器单元的阵列包括基本上垂直的结构，提供间隔距离等于阵列的最小间距的一半的距离的电子存储器功能。提供电子存储器功能的结构被配置为存储每个门多于一个位。阵列还包括到存储器单元的电接触，包括基本垂直的结构。电池可以被编程为具有与栅极绝缘体相邻的多个电荷水平中的一个，其邻近于第一源极/漏极区域，使得沟道区域具有第一电压阈值区域（Vt1）和第二电压阈值区域（Vt2）并且使得编程单元以降低的漏极源电流工作。

54. 发明申请

US20070049030A1 Pitch multiplication spacers and methods of forming the same 有权
标题翻译：间距倍增器及其形成方法
公开(公告)号：US20070049030A1
公开(公告)日：2007-03-01
申请号：US11219346
申请日：2005-09-01
申请人： Gurtej Sandhu , Kirk Prall
发明人： Gurtej Sandhu , Kirk Prall
IPC分类号： H01L21/302
CPC分类号： H01L21/67063 , H01L21/0337 , H01L21/0338 , H01L21/3086 , H01L21/3088 , H01L21/32053 , H01L21/32134
摘要： Spacers in a pitch multiplication process are formed without performing a spacer etch. Rather, the mandrels are formed over a substrate and then the sides of the mandrels are reacted, e.g., in an oxidization, nitridation, or silicidation step, to form a material that can be selectively removed relative to the unreacted portions of the mandrel. The unreacted portions are selectively removed to leave a pattern of free-standing spacers. The free-standing spacers can serve as a mask for subsequent processing steps, such as etching the substrate.
摘要翻译：在不执行间隔物蚀刻的情况下形成间距倍增过程中的间隔物。相反，心轴形成在衬底上，然后心轴的侧面例如在氧化，氮化或硅化步骤中反应，以形成相对于心轴的未反应部分可以选择性去除的材料。选择性地去除未反应部分以留下独立间隔物的图案。独立的间隔物可以用作后续处理步骤的掩模，例如蚀刻基底。

55. 发明申请

US20060203555A1 Multi-state memory cell with asymmetric charge trapping 失效
公开(公告)号：US20060203555A1
公开(公告)日：2006-09-14
申请号：US11432020
申请日：2006-05-11
申请人： Kirk Prall
发明人： Kirk Prall
IPC分类号： G11C16/04
CPC分类号： H01L29/7887 , H01L29/7923
摘要： A multi-state NAND memory cell is comprised of two drain/source areas in a substrate. An oxide-nitride-oxide structure is formed above the substrate between the drain/source areas. The nitride layer acting as an asymmetric charge trapping layer. A control gate is located above the oxide-nitride-oxide structure. An asymmetrical bias on the drain/source areas causes the drain/source area with the higher voltage to inject an asymmetric distribution hole by gate induced drain leakage injection into the trapping layer substantially adjacent that drain/source area.

56. 发明申请

US20060163614A1 Multi-layer memory arrays 审中-公开
公开(公告)号：US20060163614A1
公开(公告)日：2006-07-27
申请号：US11392343
申请日：2006-03-29
申请人： Kirk Prall
发明人： Kirk Prall
IPC分类号： H01L27/10
CPC分类号： G11C16/04
摘要： Multi-layer memory arrays and methods are provided. A memory array has two or more layers of memory material, each layer of memory material having an array of memory cells. A first contact penetrates through each layer of memory material in a first plane and is electrically connected to each layer of memory material so as to electrically interconnect the layers of memory material in the first plane. A second contact penetrates through at least one of the layers of memory material in a second plane substantially perpendicular to the first plane.

57. 发明申请

US20060128104A1 NROM memory cell, memory array, related devices and methods 有权
公开(公告)号：US20060128104A1
公开(公告)日：2006-06-15
申请号：US11346131
申请日：2006-02-02
申请人： Kirk Prall , Leonard Forbes
发明人： Kirk Prall , Leonard Forbes
IPC分类号： H01L21/336
CPC分类号： H01L27/11568 , G11C11/5692 , G11C16/0475 , H01L27/115
摘要： An array of memory cells configured to store at least one bit per one F2 includes substantially vertical structures providing an electronic memory function spaced apart a distance equal to one half of a minimum pitch of the array. The structures providing the electronic memory function are configured to store more than one bit per gate. The array also includes electrical contacts to the memory cells including the substantially vertical structures. The cells can be programmed to have one of a number of charge levels trapped in the gate insulator adjacent to the first source/drain region such that the channel region has a first voltage threshold region (Vt1) and a second voltage threshold region (Vt2) and such that the programmed cell operates at reduced drain source current.

58. 发明申请

US20060128103A1 NROM memory cell, memory array, related devices and methods 有权
公开(公告)号：US20060128103A1
公开(公告)日：2006-06-15
申请号：US11345982
申请日：2006-02-02
申请人： Kirk Prall , Leonard Forbes
发明人： Kirk Prall , Leonard Forbes
IPC分类号： H01L21/336
CPC分类号： H01L27/11568 , G11C11/5692 , G11C16/0475 , H01L27/115
摘要： An array of memory cells configured to store at least one bit per one F2 includes substantially vertical structures providing an electronic memory function spaced apart a distance equal to one half of a minimum pitch of the array. The structures providing the electronic memory function are configured to store more than one bit per gate. The array also includes electrical contacts to the memory cells including the substantially vertical structures. The cells can be programmed to have one of a number of charge levels trapped in the gate insulator adjacent to the first source/drain region such that the channel region has a first voltage threshold region (Vt1) and a second voltage threshold region (Vt2) and such that the programmed cell operates at reduced drain source current.

59. 发明申请

US20060124967A1 NROM memory cell, memory array, related devices and methods 有权
公开(公告)号：US20060124967A1
公开(公告)日：2006-06-15
申请号：US11346421
申请日：2006-02-02
申请人： Kirk Prall , Leonard Forbes
发明人： Kirk Prall , Leonard Forbes
IPC分类号： H01L27/10
CPC分类号： H01L27/11568 , G11C11/5692 , G11C16/0475 , H01L27/115
摘要： An array of memory cells configured to store at least one bit per one F2 includes substantially vertical structures providing an electronic memory function spaced apart a distance equal to one half of a minimum pitch of the array. The structures providing the electronic memory function are configured to store more than one bit per gate. The array also includes electrical contacts to the memory cells including the substantially vertical structures. The cells can be programmed to have one of a number of charge levels trapped in the gate insulator adjacent to the first source/drain region such that the channel region has a first voltage threshold region (Vt1) and a second voltage threshold region (Vt2) and such that the programmed cell operates at reduced drain source current.

60. 发明申请

US20060008988A1 Method of forming a memory cell 审中-公开
标题翻译：形成存储单元的方法
公开(公告)号：US20060008988A1
公开(公告)日：2006-01-12
申请号：US11217944
申请日：2005-09-01
申请人： Chun Chen , Guy Blalock , Graham Wolstenholme , Kirk Prall
发明人： Chun Chen , Guy Blalock , Graham Wolstenholme , Kirk Prall
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , H01L21/76895 , H01L27/115
摘要： Methods and apparatus are described to facilitate forming memory devices with low resistance polysilicon local interconnects that allow a smaller array feature size and therefore facilitate forming arrays of a denser array format. Embodiments of the present invention are formed utilizing a wet etch process that has a high selectivity, allowing the deposition and etching of polysilicon local interconnects to source regions of array transistors. By providing for a local interconnect of polysilicon, a smaller source region and/or drain region can also be utilized, further decreasing the required word line spacing. Low resistance polysilicon local source interconnects can also couple to an increased number of memory cells, thereby reducing the number of contacts made to an array ground.
摘要翻译：描述了方法和装置以便于形成具有低电阻多晶硅局部互连的存储器件，其允许更小的阵列特征尺寸，并因此促进形成更密集阵列格式的阵列。使用具有高选择性的湿蚀刻工艺形成本发明的实施例，允许将多晶硅局部互连件沉积和蚀刻到阵列晶体管的源极区域。通过提供多晶硅的局部互连，还可以利用更小的源极区和/或漏极区，进一步减少所需的字线间隔。低电阻多晶硅本地源极互连还可以耦合到增加数量的存储器单元，从而减少对阵列地阵进行的触点的数量。

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