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51. 发明申请

US20060031279A1 Highly parallel structure for fast multi cycle binary and decimal adder unit 审中-公开
标题翻译：用于快速多周期二进制和十进制加法器单元的高度并行结构
公开(公告)号：US20060031279A1
公开(公告)日：2006-02-09
申请号：US11175489
申请日：2005-07-06
申请人： Wilhelm Haller , Wen Li , Michael Kelly , Holger Wetter
发明人： Wilhelm Haller , Wen Li , Michael Kelly , Holger Wetter
IPC分类号： G06F7/50
CPC分类号： G06F7/494 , G06F7/508 , G06F7/575 , G06F2207/4924
摘要： An adder circuit for adding two binary or two decimal operands A and B in which the carries are calculated directly from the input operands A and B without including the plus 6 or minus 6 operations into the carry calculation. For all timing critical functions the reduced input data set, i.e., valid decimal data can be used and the non-existing decimal numbers (10 to 15) need not be excluded by separate check logic any more. This reduces the complexity of the logic functions.
摘要翻译：一个加法器电路，用于将两个二进制或两个十进制操作数A和B相加，其中运算由输入操作数A和B直接计算而不加加6或减6运算到进位计算中。对于所有时序关键功能，可以使用简化的输入数据集，即有效的十进制数据，并且不需要单独的检查逻辑排除不存在的十进制数（10至15）。这降低了逻辑功能的复杂性。

52. 发明申请

US20050233284A1 Optical sight system for use with weapon simulation system 审中-公开
标题翻译：用于武器模拟系统的光学瞄准系统
公开(公告)号：US20050233284A1
公开(公告)日：2005-10-20
申请号：US10974543
申请日：2004-10-27
申请人： Pando Traykov , Zhilie Li , Yang Shen , Wen Li , Jay Luo
发明人： Pando Traykov , Zhilie Li , Yang Shen , Wen Li , Jay Luo
IPC分类号： G09B19/00
CPC分类号： F41G3/2611 , F41G3/26
摘要： An optical sight system is used in conjunction with such a weapon simulation system to immerse a user in the interactive simulation by employing an actual weapon sight with a simulated weapon, such that the view through the weapon sight is a clear view of an image on a primary image display. The system includes a secondary image display electrically connected to an image generator to receive the target corresponding to a magnified version of the scenario displayed on the primary image display. To view the image on the secondary image display with the weapon sight, the optical sight system includes an optical lens to correct the long focal distance of the scope and enable it to focus on the secondary image display. Through the use of a laser on the simulated weapon, the system is able to generate the desired magnified view on the secondary image display. Using a system of interpolation and extrapolation, the optical sight system is able to further create a clear magnified view of the primary image display. The system further provides a method for correcting the angle displayed on the secondary image display to compensate for rotation of the weapon simulator as handled by the user.
摘要翻译：光学瞄准系统与这样的武器模拟系统结合使用，以将用户通过使用具有模拟武器的实际武器瞄准器来将用户浸入到交互式模拟中，使得通过武器瞄准镜的视野是清晰的视野主图像显示。该系统包括电连接到图像发生器以接收对应于在主图像显示器上显示的场景的放大版本的目标的次要图像显示。要使用武器瞄准镜观看二次图像显示器上的图像，光学瞄准器系统包括一个光学透镜，用于校正示波器的长焦距并使其能够聚焦在二次图像显示上。通过在模拟武器上使用激光，系统能够在次要图像显示器上产生期望的放大视图。使用插值和外推系统，光学瞄准系统能够进一步创建主要图像显示的清晰放大视图。该系统还提供了一种用于校正显示在次级图像显示器上的角度以补偿由用户处理的武器模拟器的旋转的方法。

53. 发明申请

US20050054850A1 Pyridine, pyrimidine, quinoline, quinazoline, and naphthalene urotensin-II receptor antagonists 失效
标题翻译：吡啶，嘧啶，喹啉，喹唑啉和萘脲素受体拮抗剂
公开(公告)号：US20050054850A1
公开(公告)日：2005-03-10
申请号：US10924181
申请日：2004-08-23
申请人： Chengde Wu , C. Anderson , Huong Bui , Brian Dupre , Daxin Gao , George Holland , Jamal Kassir , Wen Li , Junmei Wang
发明人： Chengde Wu , C. Anderson , Huong Bui , Brian Dupre , Daxin Gao , George Holland , Jamal Kassir , Wen Li , Junmei Wang
IPC分类号： A61K31/503 , A61K31/513 , A61K31/5377 , C07D413/14 , C07D43/14 , C07D41/14
CPC分类号： A61K31/503 , A61K31/513 , A61K31/5377 , C07D413/14
摘要： The present invention relates to urotensin II receptor antagonists, pharmaceutical compositions containing them and their use.
摘要翻译：本发明涉及尿素调节素II受体拮抗剂，含有它们的药物组合物及其应用。

54. 发明申请

US20050049286A1 Phenylenediamine urotensin-II receptor antagonists and CCR-9 antagonists 失效
标题翻译：苯二胺尿激肽素受体拮抗剂和CCR-9拮抗剂
公开(公告)号：US20050049286A1
公开(公告)日：2005-03-03
申请号：US10924180
申请日：2004-08-23
申请人： Chengde Wu , C. Anderson , Huong Bui , Daxin Gao , Jamal Kassir , Wen Li , Junmei Wang , Ronald Biediger , Jie Chen , Robert Market
发明人： Chengde Wu , C. Anderson , Huong Bui , Daxin Gao , Jamal Kassir , Wen Li , Junmei Wang , Ronald Biediger , Jie Chen , Robert Market
IPC分类号： A61K31/40 , A61K31/44 , A61K31/445 , A61K31/495 , A61K31/537 , A61K31/55 , C07D211/26 , C07D265/30
CPC分类号： C07D207/16 , A61K31/16 , A61K31/40 , A61K31/445 , A61K31/497 , C07D209/08 , C07D209/44 , C07D213/74 , C07D237/08 , C07D239/26 , C07D241/42 , C07D295/135 , C07D333/38 , C07D401/12 , C07D403/12 , C07D409/12
摘要： The present invention relates to urotensin II receptor antagonists, CCR-9 antagonists, pharmaceutical compositions containing them and their use.
摘要翻译：本发明涉及尿素调节素II受体拮抗剂，CCR-9拮抗剂，含有它们的药物组合物及其应用。

55. 发明授权

US06723711B2 Propanoic acid derivatives that inhibit the binding of integrins to their receptors 失效
标题翻译：抑制整联蛋白与其受体结合的丙酸衍生物
公开(公告)号：US06723711B2
公开(公告)日：2004-04-20
申请号：US09973414
申请日：2001-10-09
申请人： Ronald J. Biediger , Brian Dupre , Linda K. Hamaker , George W. Holland , Jamal M. Kassir , Wen Li , Robert V. Market , Noel Nguyen , Ian L. Scott , Chengde Wu , E. Radford Decker
发明人： Ronald J. Biediger , Brian Dupre , Linda K. Hamaker , George W. Holland , Jamal M. Kassir , Wen Li , Robert V. Market , Noel Nguyen , Ian L. Scott , Chengde Wu , E. Radford Decker
IPC分类号： C07D21364
CPC分类号： C07D213/64 , C07D317/60 , C07D405/12 , C07D409/14
摘要： A compound of the structure A method for the inhibition of the binding of &agr;4&bgr;1 integrin to its receptors, for example VCAM-1(vascular cell adhesion molecule-1) and fibronectin; pharmaceutically active compositions comprising these compounds; and the use of these compounds for the control or prevention of diseases states in which &agr;4&bgr;1 is involved are also disclosed.
摘要翻译：用于抑制α4β1整联蛋白与其受体结合的方法的化合物，例如VCAM-1（血管细胞粘附分子-1）和纤连蛋白; 包含这些化合物的药物活性组合物; 并且还公开了这些化合物用于控制或预防其中涉及α4β1的疾病状态的用途。

56. 发明授权

US06691214B1 DDR II write data capture calibration 失效
公开(公告)号：US06691214B1
公开(公告)日：2004-02-10
申请号：US09650079
申请日：2000-08-29
申请人： Wen Li , Christopher K. Morzano
发明人： Wen Li , Christopher K. Morzano
IPC分类号： G06F1200
CPC分类号： G11C7/1078 , G11C7/02 , G11C7/1006 , G11C7/1066 , G11C7/1087 , G11C7/1093 , G11C7/1096 , G11C7/22 , G11C7/222 , G11C11/4076 , G11C11/4096 , G11C2207/107 , G11C2207/2254
摘要： A calibration circuit for calibrating the input data path of a digital circuit is disclosed. A simple string of a repeating data pattern such as, e.g., “1100,” is sent on the data path. The digital circuit captures the data using a clock signal, examines the data signal for the predetermined pattern and adjusts a delay applied to the data signal until the predetermined pattern is recognized. Then the delay is further adjusted until the predetermined pattern is no longer recognized indicating that an edge of the eye of the data is near a clocking edge of the clocking signal. The delay applied to the data signal is then further adjusted by a predetermined amount to position the clock edge near the center of the data eye.

57. 发明授权

US06320781B1 Apparatus for minimization of data line coupling in a semiconductor memory device 有权
标题翻译：用于使半导体存储器件中的数据线耦合最小化的装置
公开(公告)号：US06320781B1
公开(公告)日：2001-11-20
申请号：US09824363
申请日：2001-04-02
申请人： Wen Li , Manny K. Ma
发明人： Wen Li , Manny K. Ma
IPC分类号： G11C506
CPC分类号： G11C7/18 , G11C5/063 , G11C7/1048
摘要： The present disclosure includes a twist architecture useful for the data lines in a memory device. The architecture involves the twisting of four data lines to create four portions such that each data line occupies a different position in each of the four portions. Specifically, in the first portion, the first data line is adjacent to the second data line, the second data line is adjacent to the third data line, and the third data line is adjacent to the fourth data line; in the second portion, the third data line is adjacent to the first data line, the first data line is adjacent to the fourth data line, and the fourth data line is adjacent to the second data line; in the third portion, the fourth data line is adjacent to the third data line, the third data line is adjacent to the second data line, and the second data line is adjacent to the first data line; and in the fourth portion, the second data line is adjacent to the fourth data line, the fourth data line is adjacent to the first data line, and the first data line is adjacent to the third data line. Such an architecture reduces unwanted parasitic capacitive coupling between the data lines and hence improves speed.
摘要翻译：本公开包括对存储器设备中的数据线有用的扭曲架构。该体系结构涉及四条数据线的扭转以产生四个部分，使得每个数据线在四个部分的每一个中占据不同的位置。具体地说，在第一部分中，第一数据线与第二数据线相邻，第二数据线与第三数据线相邻，第三数据线与第四数据线相邻; 在第二部分中，第三数据线与第一数据线相邻，第一数据线与第四数据线相邻，第四数据线与第二数据线相邻; 在第三部分中，第四数据线与第三数据线相邻，第三数据线与第二数据线相邻，第二数据线与第一数据线相邻; 并且在第四部分中，第二数据线与第四数据线相邻，第四数据线与第一数据线相邻，并且第一数据线与第三数据线相邻。这种架构减少了数据线之间的不必要的寄生电容耦合，从而提高了速度。

58. 发明授权

US06259621B1 Method and apparatus for minimization of data line coupling in a semiconductor memory device 有权
标题翻译：用于最小化半导体存储器件中的数据线耦合的方法和装置
公开(公告)号：US06259621B1
公开(公告)日：2001-07-10
申请号：US09610760
申请日：2000-07-06
申请人： Wen Li , Manny K. Ma
发明人： Wen Li , Manny K. Ma
IPC分类号： G11C506
CPC分类号： G11C7/18 , G11C5/063 , G11C7/1048
摘要： The present disclosure includes a twist architecture useful for the data lines in a memory device. The architecture involves the twisting of four data lines to create four portions such that each data line occupies a different position in each of the four portions. Specifically, in the first portion, the first data line is adjacent to the second data line, the second data line is adjacent to the third data line, and the third data line is adjacent to the fourth data line; in the second portion, the third data line is adjacent to the first data line, the first data line is adjacent to the fourth data line, and the fourth data line is adjacent to the second data line; in the third portion, the fourth data line is adjacent to the third data line, the third data line is adjacent to the second data line, and the second data line is adjacent to the first data line; and in the fourth portion, the second data line is adjacent to the fourth data line, the fourth data line is adjacent to the first data line, and the first data line is adjacent to the third data line. Such an architecture reduces unwanted parasitic capacitive coupling between the data lines and hence improves speed.
摘要翻译：本公开包括对存储器设备中的数据线有用的扭曲架构。该体系结构涉及四条数据线的扭转以产生四个部分，使得每个数据线在四个部分的每一个中占据不同的位置。具体地说，在第一部分中，第一数据线与第二数据线相邻，第二数据线与第三数据线相邻，第三数据线与第四数据线相邻; 在第二部分中，第三数据线与第一数据线相邻，第一数据线与第四数据线相邻，第四数据线与第二数据线相邻; 在第三部分中，第四数据线与第三数据线相邻，第三数据线与第二数据线相邻，第二数据线与第一数据线相邻; 并且在第四部分中，第二数据线与第四数据线相邻，第四数据线与第一数据线相邻，并且第一数据线与第三数据线相邻。这种架构减少了数据线之间的不必要的寄生电容耦合，从而提高了速度。

59. 发明授权

US06240042B1 Output circuit for a double data rate dynamic random access memory, double data rate dynamic random access memory, method of clocking data out from a double data rate dynamic random access memory and method of providing a data strobe signal 有权
公开(公告)号：US06240042B1
公开(公告)日：2001-05-29
申请号：US09389531
申请日：1999-09-02
申请人： Wen Li
发明人： Wen Li
IPC分类号： G11C800
CPC分类号： G11C7/1057 , G11C7/1051 , G11C7/106 , G11C7/1066 , G11C7/1072 , G11C2207/107
摘要： A method and apparatus for synchronizing output data and data strobe signals uses internal interleaved clock signals in a double data rate (DDR) DRAM that are synchronized with an external clock. A delay-locked loop internal to the DDR DRAM is locked to an external clock signal and generates the internal interleaved clock signals. The internal interleaved clock signals are delay matched with the external clock signal as they propagate through timing circuitry coupled to latency and burst length selection signals. A data strobe signal is generated using clock signals from the delay-locked loop and is synchronized with the internal interleaved clock signals. The data strobe signal and the data are coupled via paths having comparable numbers and types of delay elements to provide output data and data strobe signals having predetermined delay relationships with the external clock signal.

60. 发明授权

US12026912B2 Apparatus and methodology for aiming point and aiming device 6DOF detection using image registration 有权
公开(公告)号：US12026912B2
公开(公告)日：2024-07-02
申请号：US17473297
申请日：2021-09-13
申请人： Wen Li , Ming Yang
发明人： Wen Li , Ming Yang
IPC分类号： G06T7/80 , G03B17/56 , G06N3/045 , G06T7/73
CPC分类号： G06T7/80 , G03B17/561 , G06T7/74 , G06N3/045 , G06T2207/10028 , G06T2207/20084 , G06T2207/30244
摘要： A system and a method for determining aiming point and/or six degrees of freedom of an aiming device. The system include the aiming device, a camera mounted thereon, and a computing device. The aiming point is an intersection between a line of interest (LOI) of the aiming device and surface of an aimed object. A parallel auxiliary line (PAL) is a line starting from the camera and parallel to the LOI. The PAL is a point (PAL-T) in a template image captured by the first camera. The computing device is configured to: provide a reference image; map the template image to the reference image; project the PAL-T to the reference image using the mapping relation to obtain a reference point (PAL-R); determine 3D coordinates PAL-3D of the PAL-R; and determine 3D coordinates of the aiming point based on the PAL-3D and a relationship between the LOI and the PAL.

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