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51. 发明授权

US06701426B1 Switching between a plurality of branch prediction processes based on which instruction set is operational wherein branch history data structures are the same for the plurality of instruction sets 有权
标题翻译：基于哪个指令集可操作的多个分支预测处理之间切换，其中分支历史数据结构对于多个指令集是相同的
公开(公告)号：US06701426B1
公开(公告)日：2004-03-02
申请号：US09425037
申请日：1999-10-19
申请人： Greg L. Ries , Ronak S. Patel , Korbin S. Van Dyke , Niteen Patkar , T. R. Ramesh
发明人： Greg L. Ries , Ronak S. Patel , Korbin S. Van Dyke , Niteen Patkar , T. R. Ramesh
IPC分类号： G06F938
CPC分类号： G06F9/3806 , G06F9/30174 , G06F9/3848
摘要： A multiple instruction set processor and method dynamically activates one of a plurality of branch prediction processes depending upon which one of a multiple instruction set is operational. Shared branch history table structures are used and are indexed differently depending upon which instruction set is operational. The apparatus and method also allows switching between instruction set index generators for each of the plurality of instruction sets. Accordingly, different indexes to branch prediction data are used depending upon which of the plurality of instruction sets is operational. Shared memory may be used to contain branch prediction table data for instructions from each of the plurality of instruction sets in response to selection of an instruction set. Shared memory is also used to contain branch target buffer data for instructions from each of the plurality of instruction sets in response to selection of one of the instruction sets.
摘要翻译：多指令集处理器和方法根据多指令集中的哪一个可操作地动态地激活多个分支预测处理中的一个。使用共享分支历史表结构，并根据哪个指令集可操作而进行索引。该装置和方法还允许在指令集索引生成器之间切换多个指令集中的每一个。因此，取决于多个指令集中的哪一个是可操作的，使用不同的分支预测数据索引。响应于指令集的选择，可以使用共享存储器来包含来自多个指令集中的每一个的指令的分支预测表数据。响应于选择一个指令集，共享存储器还用于包含来自多个指令集中的每一个的指令的转移目标缓冲器数据。

52. 发明授权

US06671798B1 Configurable branch prediction for a processor performing speculative execution 失效
标题翻译：执行推测执行的处理器的可配置分支预测
公开(公告)号：US06671798B1
公开(公告)日：2003-12-30
申请号：US09992822
申请日：2001-11-16
申请人： David L. Puziol , Korbin S. Van Dyke , Larry Widigen , Len Shar , Walstein Bennett Smith, III
发明人： David L. Puziol , Korbin S. Van Dyke , Larry Widigen , Len Shar , Walstein Bennett Smith, III
IPC分类号： G06F938
CPC分类号： G06F9/3851 , G06F9/3806 , G06F9/3848
摘要： In a first aspect of the invention, branch prediction hardware, comprising logic and interconnect, is configurable via a control line to alter the manner in which the branch prediction is generated. The configuration can be done programmatically in software. Or, the configuration can be done by hardware in response to processor events. Such processor events include the loading of the CS register and changes in the instruction workload. In a second aspect of the invention, related to speculative execution, the directions of a plurality of branches are predicted based partly on resolved branch history information. Tentative branch history information is then stored for each of the predicted branches. When a predicted branch is resolved, the resolved branch history information is updated based on the stored tentative branch history information for the branch most recently resolved. Additionally, the predictions may be partly based on preceding unresolved branch predictions if any are outstanding. In a third aspect of the invention, Hit/Miss information from a Branch Prediction Cache (BPC) can optionally be used in formulating the next state value of an addressed two-bit counter stored in a correlation-based branch history table. Since a Miss in the BPC may indicate that this branch has not been encountered recently, whatever state currently exists can be optionally forced to a state that is based solely on whether the branch is resolved taken or not. This feature may be enabled and disabled under software control. In a fourth aspect of the invention, information from the instruction decoder is optionally used to override the correlation-based branch history table based prediction for select branch instructions. This feature may be enabled and disabled under software or hardware control.
摘要翻译：在本发明的第一方面中，包括逻辑和互连的分支预测硬件可经由控制线进行配置，以改变生成分支预测的方式。该配置可以通过软件进行编程。或者，可以通过硬件来响应处理器事件来进行配置。这样的处理器事件包括CS寄存器的加载和指令工作量的变化。在本发明的第二方面中，与推测执行相关，部分地基于解决的分支历史信息来预测多个分支的方向。然后针对每个预测分支存储暂定分支历史信息。当解决预测分支时，根据所存储的用于最近解决的分支的临时分支历史信息来更新所解析的分支历史信息。此外，预测可能部分基于前述未解决的分支预测（如果有）是未完成的。在本发明的第三方面中，来自分支预测高速缓存（BPC）的命中/错误信息可以可选地用于制定存储在基于相关的分支历史表中的寻址的两位计数器的下一个状态值。由于BPC中的小姐可能会指出最近没有遇到这个分支，所以无论目前存在什么状态，都可以强制执行到仅基于分支是否被解决的状态。可以在软件控制下启用和禁用此功能。在本发明的第四方面中，可选地使用来自指令解码器的信息来覆盖用于选择分支指令的基于相关性的基于分支历史表的预测。可以在软件或硬件控制下启用和禁用此功能。

53. 发明授权

US06449671B1 Method and apparatus for busing data elements 失效
标题翻译：调用数据元素的方法和装置
公开(公告)号：US06449671B1
公开(公告)日：2002-09-10
申请号：US09328971
申请日：1999-06-09
申请人： Niteen A. Patkar , Stephen C. Purcell , Shalesh Thusoo , Korbin S. Van Dyke
发明人： Niteen A. Patkar , Stephen C. Purcell , Shalesh Thusoo , Korbin S. Van Dyke
IPC分类号： G06F1300
CPC分类号： G06F12/0806
摘要： A method and apparatus for busing data elements within a computing system includes processing that begins by providing, on a shared bus, a first control signal relating to a first transaction during a first bus cycle. The processing continues by providing a second control signal relating to a second transaction and a first address signal relating to the first transaction during a second bus cycle. The processing continues by providing a third control signal relating to a third transaction and a second address signal relating to a second transaction during a third bus cycle. The processing then continues by providing a first status relating to the first transaction and a third addressing signal relating to the third transaction during a fourth bus cycle. The processing then continues by providing a second status relating to the second transaction during a fifth bus cycle. The processing then continues by providing first data relating to the first transaction when the first status is a hit and providing third status relating to the third transaction during a sixth bus cycle.
摘要翻译：用于在计算系统内传送数据元素的方法和装置包括开始于在共享总线上提供在第一总线周期期间与第一事务相关的第一控制信号的处理。通过在第二总线周期期间提供与第二事务相关的第二控制信号和与第一事务相关的第一地址信号来继续处理。通过在第三总线周期期间提供与第三事务相关的第三控制信号和与第二事务相关的第二地址信号来继续处理。然后通过在第四总线周期期间提供与第一事务相关的第一状态和与第三事务相关的第三寻址信号来继续处理。然后通过在第五总线周期期间提供与第二事务相关的第二状态来继续处理。然后，当第一状态是命中时，通过提供与第一事务有关的第一数据继续处理，并在第六总线周期期间提供与第三事务有关的第三状态。

54. 发明授权

US06397379B1 Recording in a program execution profile references to a memory-mapped active device 有权
标题翻译：在程序执行配置文件中记录引用存储器映射的活动设备
公开(公告)号：US06397379B1
公开(公告)日：2002-05-28
申请号：US09428850
申请日：1999-10-28
申请人： John S. Yates, Jr. , David L. Reese , Korbin S. Van Dyke
发明人： John S. Yates, Jr. , David L. Reese , Korbin S. Van Dyke
IPC分类号： G06F944
CPC分类号： G06F9/45554 , G06F9/45558 , G06F2009/45579 , G06F2009/45583
摘要： A method and a computer for execution of the method. As part of executing a stream of instructions, a series of memory loads is issued from a computer CPU to a bus, some directed to well-behaved memory and some directed to non-well-behaved devices in I/O space. Computer addresses are stored of instructions of the stream that issued memory loads to the non-well-behaved memory, the storage form of the recording allowing determination of whether the memory load was to well-behaved memory or not-well-behaved memory without resolution of any memory address stored in the recording.
摘要翻译：用于执行该方法的方法和计算机。作为执行指令流的一部分，从计算机CPU向总线发出一系列内存负载，一些针对良好的内存，一些定向到I / O空间中不良的设备。计算机地址存储了将内存负载发送到不良行为的存储器的流的指令，记录的存储形式允许确定存储器负载是否表现良好的存储器还是不具有良好的存储器而没有解决存储在记录中的任何存储器地址。

55. 发明授权

US06360318B1 Configurable branch prediction for a processor performing speculative execution 失效
标题翻译：执行推测执行的处理器的可配置分支预测
公开(公告)号：US06360318B1
公开(公告)日：2002-03-19
申请号：US09608451
申请日：2000-06-29
申请人： David L. Puziol , Korbin S. Van Dyke , Larry Widigen , Len Shar , Walstein Bennett Smith, III
发明人： David L. Puziol , Korbin S. Van Dyke , Larry Widigen , Len Shar , Walstein Bennett Smith, III
IPC分类号： G06F938
CPC分类号： G06F9/3851 , G06F9/3806 , G06F9/3848
摘要： In a first aspect of the invention, branch prediction hardware, comprising logic and interconnect, is configurable via a control line to alter the manner in which the branch prediction is generated. The configuration can be done programmatically In software. Or, the configuration can be done by hardware in response to processor events. Such processor events include the loading of the CS register and changes in the instruction workload. In a second aspect of the invention, related to speculative execution, the directions of a plurality of branches are predicted based partly on resolved branch history information. Tentative branch history information is then stored for each of the predicted branches. When a predicted branch is resolved, the resolved branch history information is updated based on the stored tentative branch history information for the branch most recently resolved. Additionally, the predictions may be partly based on preceding unresolved branch predictions if any are outstanding. In a third aspect of the invention, Hit/Miss information from a Branch Prediction Cache (BPC) can optionally be used in formulating the next state value of an addressed two-bit counter stored in a correlation-based branch history table. Since a Miss in the BPC may indicate that this branch has not been encountered recently, whatever state currently exists can be optionally forced to a state that is based solely on whether the branch is resolved taken or not. This feature may be enabled and disabled under software control. In a fourth aspect of the invention, information from the instruction decoder is optionally used to override the correlation-based branch history table based prediction for select branch instructions. This feature may be enabled and disabled under software or hardware control.
摘要翻译：在本发明的第一方面中，包括逻辑和互连的分支预测硬件可经由控制线进行配置，以改变生成分支预测的方式。可以通过编程方式在软件中完成配置。或者，可以通过硬件来响应处理器事件来进行配置。这样的处理器事件包括CS寄存器的加载和指令工作量的变化。在本发明的第二方面中，与推测执行相关，部分地基于解决的分支历史信息来预测多个分支的方向。然后针对每个预测分支存储暂定分支历史信息。当解决预测分支时，根据所存储的用于最近解决的分支的临时分支历史信息来更新所解析的分支历史信息。此外，预测可能部分基于前述未解决的分支预测（如果有）是未完成的。在本发明的第三方面中，来自分支预测高速缓存（BPC）的命中/错误信息可以可选地用于制定存储在基于相关的分支历史表中的寻址的两位计数器的下一个状态值。由于BPC中的小姐可能会指出最近没有遇到这个分支，所以无论目前存在什么状态，都可以强制执行到仅基于分支是否被解决的状态。可以在软件控制下启用和禁用此功能。在本发明的第四方面中，可选地使用来自指令解码器的信息来覆盖用于选择分支指令的基于相关性的基于分支历史表的预测。可以在软件或硬件控制下启用和禁用此功能。

56. 发明授权

US06282639B1 Configurable branch prediction for a processor performing speculative execution 有权
标题翻译：执行推测执行的处理器的可配置分支预测
公开(公告)号：US06282639B1
公开(公告)日：2001-08-28
申请号：US09608448
申请日：2000-06-29
申请人： David L. Puziol , Korbin S. Van Dyke , Larry Widigen , Len Shar , Walstein Bennett Smith, III
发明人： David L. Puziol , Korbin S. Van Dyke , Larry Widigen , Len Shar , Walstein Bennett Smith, III
IPC分类号： G06F900
CPC分类号： G06F9/3851 , G06F9/3806 , G06F9/3848
摘要： In a first aspect of the invention, branch prediction hardware, comprising logic and interconnect, is configurable via a control line to alter the manner in which the branch prediction is generated. The configuration can be done programmatically in software. Or, the configuration can be done by hardware in response to processor events. Such processor events include the loading of the CS register and changes in the instruction workload. In a second aspect of the invention, related to speculative execution, the directions of a plurality of branches are predicted based partly on resolved branch history information. Tentative branch history information is then stored for each of the predicted branches. When a predicted branch is resolved, the resolved branch history information is updated based on the stored tentative branch history information for the branch most recently resolved. Additionally, the predictions may be partly based on preceding unresolved branch predictions if any are outstanding. In a third aspect of the invention, Hit/Miss Information from a Branch Prediction Cache (BPC) can optionally be used in formulating the next state value of an addressed two-bit counter stored in a correlation-based branch history table. Since a Miss in the BPC may indicate that this branch has not been encountered recently, whatever state currently exists can be optionally forced to a state that is based solely on whether the branch is resolved taken or not. This feature may be enabled and disabled under software control. In a fourth aspect of the invention, information from the instruction decoder is optionally used to override the correlation-based branch history table based prediction for select branch instructions. This feature may be enabled and disabled under software or hardware control.
摘要翻译：在本发明的第一方面中，包括逻辑和互连的分支预测硬件可经由控制线进行配置，以改变生成分支预测的方式。该配置可以通过软件进行编程。或者，可以通过硬件来响应处理器事件来进行配置。这样的处理器事件包括CS寄存器的加载和指令工作量的变化。在本发明的第二方面中，与推测执行相关，部分地基于解决的分支历史信息来预测多个分支的方向。然后针对每个预测分支存储暂定分支历史信息。当解决预测分支时，根据所存储的用于最近解决的分支的临时分支历史信息来更新所解析的分支历史信息。此外，预测可能部分基于前述未解决的分支预测（如果有）是未完成的。在本发明的第三方面中，来自分支预测高速缓存（BPC）的命中/错误信息可以可选地用于制定存储在基于相关的分支历史表中的寻址的两位计数器的下一状态值。由于BPC中的小姐可能会指出最近没有遇到这个分支，所以无论目前存在什么状态，都可以强制执行到仅基于分支是否被解决的状态。可以在软件控制下启用和禁用此功能。在本发明的第四方面中，可选地使用来自指令解码器的信息来覆盖用于选择分支指令的基于相关性的基于分支历史表的预测。可以在软件或硬件控制下启用和禁用此功能。

57. 发明授权

US06212629B1 Method and apparatus for executing string instructions 失效
标题翻译：执行字符串指令的方法和装置
公开(公告)号：US06212629B1
公开(公告)日：2001-04-03
申请号：US09115165
申请日：1998-07-14
申请人： Harold L. McFarland , David R. Stiles , Korbin S. Van Dyke , Shrenik Mehta , John Gregory Favor , Dale R. Greenley , Robert A. Cargnoni
发明人： Harold L. McFarland , David R. Stiles , Korbin S. Van Dyke , Shrenik Mehta , John Gregory Favor , Dale R. Greenley , Robert A. Cargnoni
IPC分类号： G06F930
CPC分类号： G06F9/34 , G06F9/30003 , G06F9/30018 , G06F9/3005 , G06F9/30167 , G06F9/30174 , G06F9/30185 , G06F9/30189 , G06F9/3555 , G06F9/38 , G06F9/3804 , G06F9/3812 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3842 , G06F9/3855 , G06F9/3859 , G06F9/3863 , G06F9/3869 , G06F9/3885 , G06F11/364 , G06F11/3648 , G06F12/1027 , G06F12/145 , G06F15/8053
摘要： A pipeline control system for implementing a virtual architecture having a complex instruction set is distributed over RISC-like semi-autonomous functional units in a processor. Decoder logic fetches instructions of the target architecture and translates them into simpler RISC-like operations. These operations, each having an associated tag, are issued to the functional units. Address processing unit computes addresses of the instructions and operands, performs segment relocation, and manages the processor's memory. Operations are executed by the units in a manner that is generally independent of operation processing by the other units. The units report termination information back to the decoder logic, but do not irrevocably change the state of the machine. Based on the termination information, the decoder logic retires normally terminated operations in order. Thus, the functional units enable multiple operations to be executed in a speculative and out-of-order manner to fully utilize the resources of the processor.
摘要翻译：用于实现具有复杂指令集的虚拟架构的流水线控制系统在处理器中的RISC状半自主功能单元上分布。解码器逻辑获取目标架构的指令，并将其转换为更简单的类似RISC的操作。每个具有关联标签的这些操作被发布到功能单元。地址处理单元计算指令和操作数的地址，执行段重定位，并管理处理器的存储器。操作由单元以通常独立于其他单元的操作处理的方式执行。这些单元将终止信息报告回解码器逻辑，但不能不可逆转地更改机器的状态。基于终止信息，解码器逻辑依次退出正常终止的操作。因此，功能单元能够以推测和无序的方式执行多个操作，以充分利用处理器的资源。

58. 发明授权

US6108777A Configurable branch prediction for a processor performing speculative execution 失效
公开(公告)号：US6108777A
公开(公告)日：2000-08-22
申请号：US73499
申请日：1998-05-06
申请人： David L. Puziol , Korbin S. Van Dyke , Larry Widigen , Len Shar , Walstein Bennett Smith, III
发明人： David L. Puziol , Korbin S. Van Dyke , Larry Widigen , Len Shar , Walstein Bennett Smith, III
IPC分类号： G06F9/38
CPC分类号： G06F9/3851 , G06F9/3806 , G06F9/3848
摘要： In a first aspect of the invention, branch prediction hardware, comprising logic and interconnect, is configurable via a control line to alter the manner in which the branch prediction is generated. The configuration can be done programmatically in software. Or, the configuration can be done by hardware in response to processor events. Such processor events include the loading of the CS register and changes in the instruction workload. In a second aspect of the invention, related to speculative execution, the directions of a plurality of branches are predicted based partly on resolved branch history information. Tentative branch history information is then stored for each of the predicted branches. When a predicted branch is resolved, the resolved branch history information is updated based on the stored tentative branch history information for the branch most recently resolved. Additionally, the predictions may be partly based on preceding unresolved branch predictions if any are outstanding. In a third aspect of the invention, Hit/Miss information from a Branch Prediction Cache (BPC) can optionally be used in formulating the next state value of an addressed two-bit counter stored in a correlation-based branch history table. Since a Miss in the BPC may indicate that this branch has not been encountered recently, whatever state currently exists can be optionally forced to a state that is based solely on whether the branch is resolved taken or not. This feature may be enabled and disabled under software control. In a fourth aspect of the invention, information from the instruction decoder is optionally used to override the correlation-based branch history table based prediction for select branch instructions. This feature may be enabled and disabled under software or hardware control.

59. 发明授权

US5802339A Pipeline throughput via parallel out-of-order execution of adds and moves in a supplemental integer execution unit 失效
标题翻译：通过并行无序执行添加和移动的补充整数执行单元中的管道吞吐量
公开(公告)号：US5802339A
公开(公告)日：1998-09-01
申请号：US801709
申请日：1997-02-14
申请人： Elliot A. Sowadsky , Larry Widigen , David L. Puziol , Korbin S. Van Dyke
发明人： Elliot A. Sowadsky , Larry Widigen , David L. Puziol , Korbin S. Van Dyke
IPC分类号： G06F9/315 , G06F9/32 , G06F9/34 , G06F9/38 , G06F9/30
CPC分类号： G06F9/3885 , G06F9/30032 , G06F9/30094 , G06F9/30167 , G06F9/34 , G06F9/3836 , G06F9/384 , G06F9/3857 , G06F9/3893
摘要： The existing execution units of a high-performance processor are augmented by the addition of a supplemental integer execution unit, termed the Add/Move Unit (AMU), which performs select adds and moves in parallel and out-of-order with respect to the other execution units. At small incremental cost, AMU enables better use of the expensive limited resources of an existing Address Preparation unit (AP), which handles linear and physical address generation for memory operand references, control transfers, and page crosses. AMU removes data dependencies and thereby increases the available instruction level parallelism. The increased instruction level parallelism is readily exploited by the processor's ability to perform out-of-order and speculative execution, and performance is enhanced as a result.
摘要翻译：通过添加称为添加/移动单元（AMU）的补充整数执行单元来增加高性能处理器的现有执行单元，该单元执行选择添加并且相对于其他执行单位。以较小的增量成本，AMU可以更好地利用现有的地址准备单元（AP）的昂贵的有限资源，处理线性和物理地址生成用于存储器操作数引用，控制传输和页面交叉。 AMU删除数据依赖关系，从而增加可用的指令级并行性。处理器执行无序和推测执行的能力易于利用增加的指令级并行性，结果提高了性能。

60. 发明授权

US5682492A Computer processor with distributed pipeline control that allows functional units to complete operations out of order while maintaining precise interrupts 失效
标题翻译：具有分布式管道控制的计算机处理器，允许功能单元在保持精确中断的同时完成操作
公开(公告)号：US5682492A
公开(公告)日：1997-10-28
申请号：US380736
申请日：1995-01-30
申请人： Harold L. McFarland , David R. Stiles , Korbin S. Van Dyke , Shrenik Mehta , John Gregory Favor , Dale R. Greenley , Robert A. Cargnoni
发明人： Harold L. McFarland , David R. Stiles , Korbin S. Van Dyke , Shrenik Mehta , John Gregory Favor , Dale R. Greenley , Robert A. Cargnoni
IPC分类号： G06F9/30 , G06F9/308 , G06F9/318 , G06F9/34 , G06F9/355 , G06F9/38 , G06F11/36 , G06F15/78
CPC分类号： G06F11/3648 , G06F15/8053 , G06F9/30003 , G06F9/30018 , G06F9/30167 , G06F9/3017 , G06F9/30185 , G06F9/30189 , G06F9/34 , G06F9/3555 , G06F9/38 , G06F9/3804 , G06F9/3812 , G06F9/3836 , G06F9/384 , G06F9/3842 , G06F9/3855 , G06F9/3857 , G06F9/3863 , G06F9/3869 , G06F9/3885
摘要： A pipeline control system is distributed over the functional units (15, 17, 20, 25) in a processor (10). Decoder logic (12) issues operations, each with an associated tag, to the functional units, with up to n operations allowed to be outstanding. The units execute the operations and report termination information back to the decoder logic, but do not irrevocably change the state of the machine. Based on the termination information, the decoder logic retires normally terminated operations in order. If an operation terminates abnormally, the decoder logic instructs the units to back out of those operations that include and are later than the operation that terminated abnormally.
摘要翻译：流水线控制系统分布在处理器（10）中的功能单元（15,17,20,25）上。解码器逻辑（12）向功能单元发出每个具有关联标签的操作，最多允许n个操作被显示。单元执行操作并将终止信息报告回解码器逻辑，但不能不可逆转地改变机器的状态。基于终止信息，解码器逻辑依次退出正常终止的操作。如果操作异常终止，则解码器逻辑指示单元退出包括并晚于异常终止的操作的那些操作。

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