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51. 发明申请

US20090072302A1 Gate metal routing for transistor with checkerboarded layout 有权
标题翻译：晶体管的栅极金属布线，具有棋盘布局
公开(公告)号：US20090072302A1
公开(公告)日：2009-03-19
申请号：US12291569
申请日：2008-11-12
申请人： Vijay Parthasarathy
发明人： Vijay Parthasarathy
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L21/77 , H01L29/0696 , H01L29/0878 , H01L29/407 , H01L29/41741 , H01L29/4236 , H01L29/42372 , H01L29/4238
摘要： In one embodiment, a transistor fabricated on a semiconductor die is arranged into sections of elongated transistor segments. The sections are arranged in rows and columns substantially across the semiconductor die. Adjacent sections in a row or a column are oriented such that the length of the transistor segments in a first one of the adjacent sections extends in a first direction, and the length of the transistor segments in a second one of the adjacent sections extends in a second direction, the first direction being substantially orthogonal to the second direction. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure.
摘要翻译：在一个实施例中，制造在半导体管芯上的晶体管被布置成细长晶体管段的部分。这些部分基本上跨越半导体管芯排列成行和列。一行或一列的相邻部分定向成使得相邻部分中的第一个部分中的晶体管段的长度在第一方向上延伸，并且相邻部分中的第二个中的晶体管段的长度在第二方向，第一方向基本上与第二方向正交。要强调的是，该摘要被提供以符合要求抽象的规则，允许搜索者或其他读者快速确定技术公开内容的主题。

52. 发明申请

US20080197396A1 Gate metal routing for transistor with checkerboarded layout 有权
标题翻译：晶体管的栅极金属布线，具有棋盘布局
公开(公告)号：US20080197396A1
公开(公告)日：2008-08-21
申请号：US11707403
申请日：2007-02-16
申请人： Vijay Parthasarathy
发明人： Vijay Parthasarathy
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L21/77 , H01L29/0696 , H01L29/0878 , H01L29/407 , H01L29/41741 , H01L29/4236 , H01L29/42372 , H01L29/4238
摘要： In one embodiment, a transistor fabricated on a semiconductor die is arranged into sections of elongated transistor segments. The sections are arranged in rows and columns substantially across the semiconductor die. Adjacent sections in a row or a column are oriented such that the length of the transistor segments in a first one of the adjacent sections extends in a first direction, and the length of the transistor segments in a second one of the adjacent sections extends in a second direction, the first direction being substantially orthogonal to the second direction. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure.
摘要翻译：在一个实施例中，制造在半导体管芯上的晶体管被布置成细长晶体管段的部分。这些部分基本上跨越半导体管芯排列成行和列。一行或一列的相邻部分定向成使得相邻部分中的第一个部分中的晶体管段的长度在第一方向上延伸，并且相邻部分中的第二个中的晶体管段的长度在第二方向，第一方向基本上与第二方向正交。要强调的是，该摘要被提供以符合要求抽象的规则，允许搜索者或其他读者快速确定技术公开内容的主题。

53. 发明授权

US07368786B2 Process insensitive ESD protection device 有权
标题翻译：过程不敏感的ESD保护装置
公开(公告)号：US07368786B2
公开(公告)日：2008-05-06
申请号：US11078026
申请日：2005-03-11
申请人： Hongzhong Xu , Richard T. Ida , Vijay Parthasarathy
发明人： Hongzhong Xu , Richard T. Ida , Vijay Parthasarathy
IPC分类号： H01L23/58 , H01L29/78
CPC分类号： H01L29/0847 , H01L27/0266 , H01L29/1045 , H01L29/1083 , H01L29/7835
摘要： Methods and apparatus for ESD protection of LDMOS devices are provided. The apparatus comprises two LDMOS devices, with source, drain and gate contacts parallel coupled. One is the protected device and the other is the protecting device. Each has source region, drain region, gate, first body well region containing the source, second body well region containing the drain and separated from the first body well region by a drift region, an isolation region separated from the first and second body well regions and a buried layer contacting the isolation region. The protecting device has a further region of the same type as the drain, coupling the drain to the isolation region. Its drain connection is made via a contact to its isolation region rather than its drain region. The drift region of the protecting device is desirably smaller and the isolation-body well separation larger than for the protected device.
摘要翻译：提供了LDMOS器件的ESD保护方法和设备。该装置包括两个LDMOS器件，源极，漏极和栅极触点并联耦合。一个是受保护的设备，另一个是保护设备。每个具有源极区，漏极区，栅极，包含源极的第一体阱区域，含有漏极的第二体阱区域和通过漂移区域与第一体阱区域分离的隔离区域，与第一和第二体阱区域分离的隔离区域以及与隔离区域接触的掩埋层。保护装置具有与漏极相同类型的另一区域，将漏极耦合到隔离区域。其漏极连接通过与其隔离区而不是漏极区的接触进行。保护装置的漂移区域希望更小，并且隔离体阱分离比对于受保护的装置大。

54. 发明授权

US07355260B2 Schottky device and method of forming 有权
标题翻译：肖特基器件和成型方法
公开(公告)号：US07355260B2
公开(公告)日：2008-04-08
申请号：US10881678
申请日：2004-06-30
申请人： Vishnu K. Khemka , Vijay Parthasarathy , Ronghua Zhu , Amitava Bose
发明人： Vishnu K. Khemka , Vijay Parthasarathy , Ronghua Zhu , Amitava Bose
IPC分类号： H01L27/095 , H01L29/47
CPC分类号： H01L29/66143 , H01L29/812 , H01L29/872
摘要： A conductive layer includes a first portion that forms a Schottky region with an underlying first region having a first conductivity type. A second region of a second conductivity type underlies the first region, where the second conductivity type is opposite the first conductivity type. A third region of the first conductivity type immediately underlies the second region and is electrically coupled to a cathode of the device.
摘要翻译：导电层包括形成具有第一导电类型的下面的第一区域的肖特基区域的第一部分。第二导电类型的第二区域位于第一区域的正下方，其中第二导电类型与第一导电类型相反。第一导电类型的第三区域刚好在第二区域的下面，并且电耦合到器件的阴极。

55. 发明申请

US20060246670A1 Schottky device and method of forming 有权
标题翻译：肖特基器件和成型方法
公开(公告)号：US20060246670A1
公开(公告)日：2006-11-02
申请号：US11117996
申请日：2005-04-29
申请人： Vishnu Khemka , Vijay Parthasarathy , Ronghua Zhu , Amitava Bose
发明人： Vishnu Khemka , Vijay Parthasarathy , Ronghua Zhu , Amitava Bose
IPC分类号： H01L21/336
CPC分类号： H01L29/872 , H01L29/063 , H01L29/0692 , H01L29/66136 , H01L29/66143 , H01L29/8611
摘要： A Schottky device having a plurality of unit cells, each having a Schottky contact portion, surrounded by a termination structure that causes depletion regions to form in a vertical and horizontal direction, relative to a surface of the device, during a reverse bias voltage condition.
摘要翻译：肖特基器件具有多个单元电池，每个单元电池具有肖特基接触部分，由反向偏置电压条件期间相对于器件的表面在垂直和水平方向上形成耗尽区域的终端结构包围。

56. 发明申请

US20050245020A1 Semiconductor device and method of forming the same 有权
标题翻译：半导体器件及其形成方法
公开(公告)号：US20050245020A1
公开(公告)日：2005-11-03
申请号：US10836170
申请日：2004-04-30
申请人： Ronghua Zhu , Amitava Bose , Vishnu Khemka , Vijay Parthasarathy
发明人： Ronghua Zhu , Amitava Bose , Vishnu Khemka , Vijay Parthasarathy
IPC分类号： G06F13/00 , H01L21/20 , H01L29/739 , H01L29/861
CPC分类号： H01L29/7391 , H01L29/861
摘要： In one embodiment, semiconductor device 10 comprises a diode which uses isolation regions (34, 16, and 13) and a plurality of dopant concentrations (30, 20, 24, and 26) which may be used to limit the parasitic current that is injected into the semiconductor substrate (12). Various biases on the isolation regions (34, 16, and 13) may be used to affect the behavior of semiconductor device (10). In addition, a conductive layer (28) may be formed overlying the junction between anode (42) and cathode (40). This conductive layer (28) may decrease the electric field in selected regions in order to increase the maximum voltage that may be applied to cathode (40).
摘要翻译：在一个实施例中，半导体器件10包括使用隔离区域（34,16和13）和多个掺杂剂浓度（30,20,24和26）的二极管，其可用于限制注入的寄生电流进入半导体基板（12）。可以使用隔离区域（34,16和13）上的各种偏压来影响半导体器件（10）的行为。此外，可以形成覆盖在阳极（42）和阴极（40）之间的连接处的导电层（28）。为了增加施加到阴极（40）的最大电压，该导电层（28）可以减小选定区域中的电场。

57. 发明授权

US08866201B2 High-voltage transistor device with integrated resistor 有权
标题翻译：具有集成电阻的高压晶体管器件
公开(公告)号：US08866201B2
公开(公告)日：2014-10-21
申请号：US13385264
申请日：2012-02-10
申请人： Sujit Banerjee , Vijay Parthasarathy
发明人： Sujit Banerjee , Vijay Parthasarathy
IPC分类号： H01L29/66 , H01L29/808 , H01L27/06 , H01L49/02 , H01L29/06 , H01L29/10
CPC分类号： H01L29/808 , H01L27/0629 , H01L28/20 , H01L29/0634 , H01L29/1058 , H01L29/1066
摘要： A high-voltage device structure comprises a resistor coupled to a tap transistor that includes a JFET in a configuration wherein a voltage provided at a terminal of the JFET is substantially proportional to an external voltage when the external voltage is less than a pinch-off voltage of the JFET. The voltage provided at the terminal being substantially constant when the external voltage is greater than the pinch-off voltage. One end of the resistor is substantially at the external voltage when the external voltage is greater than the pinch-off voltage. When the external voltage is negative, the resistor limits current injected into the substrate. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure.
摘要翻译：高压器件结构包括耦合到抽头晶体管的电阻器，其包括JFET，其中当外部电压小于钳位电压时，JFET端子处的电压基本上与外部电压成比例的JFET。当外部电压大于夹断电压时，端子处提供的电压基本上恒定。当外部电压大于夹断电压时，电阻器的一端基本上处于外部电压。当外部电压为负时，电阻限制注入基板的电流。要强调的是，该摘要被提供以符合要求抽象的规则，允许搜索者或其他读者快速确定技术公开的主题。

58. 发明申请

US20140187919A1 MPR SLICE SELECTION FOR VISUALIZATION OF CATHETER IN THREE-DIMENSIONAL ULTRASOUND 审中-公开
标题翻译：三维超声波导管可视化MPR选择
公开(公告)号：US20140187919A1
公开(公告)日：2014-07-03
申请号：US14113035
申请日：2012-04-19
申请人： Vijay Parthasarathy , Ameet Kumar Jain , Charles Ray Hatt, III , Amish N. Raval
发明人： Vijay Parthasarathy , Ameet Kumar Jain , Charles Ray Hatt, III , Amish N. Raval
IPC分类号： A61B8/08 , A61B6/12 , A61B5/06 , A61M25/01
CPC分类号： A61B5/062 , A61B6/12 , A61B6/503 , A61B6/5247 , A61B8/0841 , A61B8/0883 , A61B8/4254 , A61B8/466 , A61B8/483 , A61B8/523 , A61B8/5261 , A61B34/20 , A61B2017/00243 , A61B2017/00703 , A61B2034/2051 , A61B2034/2061 , A61B2034/2065 , A61B2090/367 , A61B2090/376 , A61B2090/378 , A61M25/0108 , A61M25/0127 , G06T15/08 , G06T2210/41
摘要： A system employs an interventional tool (30), ultrasound imaging system and a multi-planar reformatting module (40). The interventional tool (30) has one or more image tracking points (31). The ultrasound imaging system includes an ultrasound probe (20) operable for generating an ultrasound volume image (22) of a portion or an entirety of the interventional tool (30) within an anatomical region. The multi-planar reformatting imaging module (40) generates two or more multi- planar reformatting images (41) of the interventional tool (30) within the anatomical region. A generation of the two multi-planar reformatting images (41) includes an identification of each image tracking point (31) within the ultrasound volume image (22), and a utilization of each identified image tracking point (31) as an origin of the multi-planar reformatting images (41).
摘要翻译：系统采用介入工具（30），超声成像系统和多平面重新格式化模块（40）。介入工具（30）具有一个或多个图像跟踪点（31）。超声成像系统包括可操作以在解剖区域内产生介入工具（30）的一部分或全部的超声体积图像（22）的超声探头（20）。多平面重新格式化成像模块（40）在解剖区域内生成介入工具（30）的两个或多个多平面重新格式化图像（41）。两个多平面重新格式化图像（41）的生成包括超声波体积图像（22）内的每个图像跟踪点（31）的识别，以及每个识别的图像跟踪点（31）的利用作为多平面重新格式化图像（41）。

59. 发明授权

US08653583B2 Sensing FET integrated with a high-voltage transistor 有权
标题翻译：感应FET与高压晶体管集成
公开(公告)号：US08653583B2
公开(公告)日：2014-02-18
申请号：US11707586
申请日：2007-02-16
申请人： Vijay Parthasarathy , Sujit Banerjee , Martin H. Manley
发明人： Vijay Parthasarathy , Sujit Banerjee , Martin H. Manley
IPC分类号： H01L29/76
CPC分类号： H01L29/7815 , H01L29/0696 , H01L29/407 , H01L29/7813
摘要： In one embodiment, a semiconductor device includes a main vertical field-effect transistor (FET) and a sensing FET. The main vertical FET and the sense FET are both formed on a pillar of semiconductor material. Both share an extended drain region formed in the pillar above the substrate, and first and second gate members formed in a dielectric on opposite sides of the pillar. The source regions of the main vertical FET and the sensing FET are separated and electrically isolated in a first lateral direction. In operation, the sensing FET samples a small portion of a current that flows in the main vertical FET. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure.
摘要翻译：在一个实施例中，半导体器件包括主垂直场效应晶体管（FET）和感测FET。主垂直FET和感测FET都形成在半导体材料的柱上。两者共同地形成在衬底上方的柱中的延伸漏极区域，以及形成在柱的相对侧上的电介质中的第一和第二栅极构件。主垂直FET和感测FET的源极区域在第一横向方向上分离并电隔离。在操作中，感测FET对在主垂直FET中流动的电流的一小部分进行采样。要强调的是，该摘要被提供以符合要求抽象的规则，允许搜索者或其他读者快速确定技术公开内容的主题。

60. 发明申请

US20120280314A1 Gate Pullback at Ends of High-Voltage Vertical Transistor Structure 审中-公开
标题翻译：高压垂直晶体管结构末端的栅极反馈
公开(公告)号：US20120280314A1
公开(公告)日：2012-11-08
申请号：US13541965
申请日：2012-07-05
申请人： Vijay Parthasarathy , Martin H. Manley
发明人： Vijay Parthasarathy , Martin H. Manley
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L21/77 , H01L29/0696 , H01L29/0878 , H01L29/407 , H01L29/41741 , H01L29/4236 , H01L29/42368 , H01L29/42372 , H01L29/4238 , H01L29/7811 , H01L2924/13055 , H01L2924/19043
摘要： In one embodiment, a transistor includes a pillar of semiconductor material arranged in a racetrack-shaped layout having a substantially linear section that extends in a first lateral direction and rounded sections at each end of the substantially linear section. First and second dielectric regions are disposed on opposite sides of the pillar. First and second field plates are respectively disposed in the first and second dielectric regions. First and second gate members respectively disposed in the first and second dielectric regions are separated from the pillar by a gate oxide having a first thickness in the substantially linear section. The gate oxide being substantially thicker at the rounded sections. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure.
摘要翻译：在一个实施例中，晶体管包括以跑道形布置布置的半导体材料柱，其具有在第一横向方向上延伸的基本上线性的部分，并且在基本线性部分的每个端部处具有圆形部分。第一和第二电介质区域设置在柱的相对侧上。第一和第二场板分别设置在第一和第二电介质区域中。分别设置在第一和第二电介质区域中的第一和第二栅极部件通过在基本线性部分中具有第一厚度的栅极氧化物与柱分离。栅极氧化物在圆形部分处基本上更厚。要强调的是，该摘要被提供以符合要求抽象的规则，允许搜索者或其他读者快速确定技术公开内容的主题。

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