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    • 51. 发明授权
    • Semiconductor nanowires charge sensor
    • 半导体纳米线充电传感器
    • US08039909B2
    • 2011-10-18
    • US12324219
    • 2008-11-26
    • Ali Afzali-ArdakaniLidija SekaricGeorge S. Tulevski
    • Ali Afzali-ArdakaniLidija SekaricGeorge S. Tulevski
    • H01L27/14
    • H01L29/0665B82Y10/00B82Y15/00G01N27/041H01L29/0673
    • A semiconductor nanowire is coated with a chemical coating layer that comprises a functional material which modulates the quantity of free charge carriers within the semiconductor nanowire. The outer surface of the chemical coating layer includes a chemical group that facilitates bonding with molecules to be detected through electrostatic forces. The bonding between the chemical coating layer and the molecules alters the electrical charge distribution in the chemical coating layer, which alters the amount of the free charge carriers and the conductivity in the semiconductor nanowire. The coated semiconductor nanowire may be employed as a chemical sensor for the type of chemicals that bonds with the functional material in the chemical coating layer. Detection of such chemicals may indicate pH of a solution, a vapor pressure of a reactive material in gas phase, and/or a concentration of a molecule in a solution.
    • 半导体纳米线涂覆有化学涂层,其包含调节半导体纳米线内的自由电荷载体的量的功能材料。 化学被膜层的外表面包括有助于通过静电力与要检测的分子结合的化学基团。 化学涂层和分子之间的结合改变化学涂层中的电荷分布,其改变半导体纳米线中游离载流子的量和导电性。 涂覆的半导体纳米线可以用作化学传感器,用于与化学涂层中的功能材料结合的化学品类型。 这种化学物质的检测可以指示溶液的pH,气相中的反应物质的蒸汽压和/或溶液中分子的浓度。
    • 52. 发明申请
    • SEMICONDUCTOR NANOWIRE WITH BUILT-IN STRESS
    • 半导体纳米管与内置应力
    • US20110104860A1
    • 2011-05-05
    • US13004340
    • 2011-01-11
    • Lidija SekaricDureseti ChidambarraoXiao H. Liu
    • Lidija SekaricDureseti ChidambarraoXiao H. Liu
    • H01L21/336
    • H01L29/775B82Y10/00H01L29/0673H01L29/42392H01L29/517H01L29/66439H01L29/7843H01L29/78696Y10S977/762Y10S977/938
    • A semiconductor nanowire having two semiconductor pads on both ends is suspended over a substrate. Stress-generating liner portions are formed over the two semiconductor pads, while a middle portion of the semiconductor nanowire is exposed. A gate dielectric and a gate electrode are formed over the middle portion of the semiconductor nanowire while the semiconductor nanowire is under longitudinal stress due to the stress-generating liner portions. The middle portion of the semiconductor nanowire is under a built-in inherent longitudinal stress after removal of the stress-generating liners because the formation of the gate dielectric and the gate electrode locks in the strained state of the semiconductor nanowire. Source and drain regions are formed in the semiconductor pads to provide a semiconductor nanowire transistor. A middle-of-line (MOL) dielectric layer may be formed directly on the source and drain pads.
    • 将两端具有两个半导体焊盘的半导体纳米线悬置在衬底上。 在半导体衬底的两个半导体衬底上形成有应力产生衬垫部分,同时露出半导体纳米线的中间部分。 在半导体纳米线的中间部分形成栅极电介质和栅电极,同时半导体纳米线由于应力产生衬垫部分而处于纵向应力之下。 由于栅极电介质和栅电极的形成锁定在半导体纳米线的应变状态,半导体纳米线的中间部分在移除应力产生衬里之后处于内置的固有纵向应力。 源极和漏极区域形成在半导体焊盘中以提供半导体纳米线晶体管。 中间线(MOL)电介质层可以直接形成在源极和漏极焊盘上。
    • 53. 发明授权
    • Semiconductor nanowire with built-in stress
    • 半导体纳米线内置应力
    • US07902541B2
    • 2011-03-08
    • US12417819
    • 2009-04-03
    • Lidija SekaricDureseti ChidambarraoXiao H. Liu
    • Lidija SekaricDureseti ChidambarraoXiao H. Liu
    • H01L29/06
    • H01L29/775B82Y10/00H01L29/0673H01L29/42392H01L29/517H01L29/66439H01L29/7843H01L29/78696Y10S977/762Y10S977/938
    • A semiconductor nanowire having two semiconductor pads on both ends is suspended over a substrate. Stress-generating liner portions are formed over the two semiconductor pads, while a middle portion of the semiconductor nanowire is exposed. A gate dielectric and a gate electrode are formed over the middle portion of the semiconductor nanowire while the semiconductor nanowire is under longitudinal stress due to the stress-generating liner portions. The middle portion of the semiconductor nanowire is under a built-in inherent longitudinal stress after removal of the stress-generating liners because the formation of the gate dielectric and the gate electrode locks in the strained state of the semiconductor nanowire. Source and drain regions are formed in the semiconductor pads to provide a semiconductor nanowire transistor. A middle-of-line (MOL) dielectric layer may be formed directly on the source and drain pads.
    • 将两端具有两个半导体焊盘的半导体纳米线悬置在衬底上。 在半导体衬底的两个半导体衬底上形成有应力产生衬垫部分,同时露出半导体纳米线的中间部分。 在半导体纳米线的中间部分形成栅极电介质和栅电极,同时半导体纳米线由于应力产生衬垫部分而处于纵向应力之下。 由于栅极电介质和栅电极的形成锁定在半导体纳米线的应变状态,半导体纳米线的中间部分在移除应力产生衬里之后处于内置的固有纵向应力。 源极和漏极区域形成在半导体焊盘中以提供半导体纳米线晶体管。 中间线(MOL)电介质层可以直接形成在源极和漏极焊盘上。