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51. 发明申请

US20110108915A1 SEMICONDUCTOR DEVICE 失效
标题翻译：半导体器件
公开(公告)号：US20110108915A1
公开(公告)日：2011-05-12
申请号：US12886461
申请日：2010-09-20
申请人： Kazutoshi NAKAMURA , Norio Yasuhara
发明人： Kazutoshi NAKAMURA , Norio Yasuhara
IPC分类号： H01L27/088
CPC分类号： H01L21/823857 , H01L21/823878 , H01L29/0619 , H01L29/1087 , H01L29/66659 , H01L29/7835
摘要： According to one embodiment, a semiconductor device includes a semiconductor substrate of a first conductivity type, an element isolation insulator, a source layer of a second conductivity type, a drain layer of the second conductivity type, a contact layer of the first conductivity type and a gate electrode. The element isolation insulator is formed on the semiconductor substrate. The source layer is formed on the semiconductor substrate and is in contact with a side surface of the element isolation insulator. The drain layer is formed on the semiconductor substrate, is in contact with the side surface, and is spaced from the source layer. The contact layer is formed between the source layer and the drain layer. The gate electrode is provided on the element isolation insulator along the side surface.
摘要翻译：根据一个实施例，半导体器件包括第一导电类型的半导体衬底，元件隔离绝缘体，第二导电类型的源极层，第二导电类型的漏极层，第一导电类型的接触层和栅电极。元件隔离绝缘体形成在半导体衬底上。源极层形成在半导体衬底上并与元件隔离绝缘体的侧表面接触。漏极层形成在半导体基板上，与侧面接触，与源极层隔开。接触层形成在源极层和漏极层之间。栅电极沿着侧面设置在元件隔离绝缘体上。

52. 发明授权

US07663186B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US07663186B2
公开(公告)日：2010-02-16
申请号：US12118159
申请日：2008-05-09
申请人： Syotaro Ono , Yoshihiro Yamaguchi , Yusuke Kawaguchi , Kazutoshi Nakamura , Norio Yasuhara , Kenichi Matsushita , Shinichi Hodama , Akio Nakagawa
发明人： Syotaro Ono , Yoshihiro Yamaguchi , Yusuke Kawaguchi , Kazutoshi Nakamura , Norio Yasuhara , Kenichi Matsushita , Shinichi Hodama , Akio Nakagawa
IPC分类号： H01L29/76 , H01L29/94
CPC分类号： H01L29/7802 , H01L21/26586 , H01L29/0653 , H01L29/0696 , H01L29/0847 , H01L29/0878 , H01L29/1095 , H01L29/402 , H01L29/407 , H01L29/42368 , H01L29/42376 , H01L29/4238 , H01L29/66712 , H01L29/7809
摘要： A semiconductor device includes: a substrate, a surface portion thereof serving as a drain layer; a first main electrode connected to the drain layer; an epitaxial layer formed on the drain layer; a base layer formed on the epitaxial layer; a source layer formed in a base layer surface portion; an insulated trench sandwiched by base layers; a JFET layer formed on trench side walls; an LDD layer formed in a base layer surface portion and connected to the JFET layer around a top face of the trench; a control electrode formed on a gate insulating film formed on an LDD layer surface part, on surfaces of source layer end parts facing each other across the trench, and on a base layer region sandwiched by the LDD and source layers; and a second main electrode connected to the source and base layers sandwiching the control electrode.
摘要翻译：半导体器件包括：衬底，用作漏极层的表面部分; 连接到漏极层的第一主电极; 形成在漏极层上的外延层; 形成在外延层上的基底层; 形成在基层表面部分中的源极层; 由基层夹住的绝缘沟槽; 形成在沟槽侧壁上的JFET层; LDD层，其形成在基底表面部分中并且围绕所述沟槽的顶面连接到所述JFET层; 形成在形成在LDD层表面部分上的栅极绝缘膜上的控制电极，在沟槽之间彼此面对的源极层部分的表面上以及由LDD和源极层夹持的基极层区域; 以及连接到夹持控制电极的源极和基极层的第二主电极。

53. 发明申请

US20100013451A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20100013451A1
公开(公告)日：2010-01-21
申请号：US12500015
申请日：2009-07-09
申请人： Kazutoshi Nakamura , Norio Yasuhara
发明人： Kazutoshi Nakamura , Norio Yasuhara
IPC分类号： G05F1/10
CPC分类号： H02M3/1588 , H02M1/32 , H02M3/158 , Y02B70/1466
摘要： A semiconductor device includes: a high-side switching element having a first switching element connected between an input voltage line and an inductive load; and a low-side switching element having a second switching element and a third switching element that are connected in parallel between the inductive load and a reference voltage line. A surge current is discharged through the third switching element to the reference voltage line when a surge is applied to a terminal connected to the inductive load in the low-side switching element.
摘要翻译：一种半导体器件包括：高侧开关元件，其具有连接在输入电压线和感性负载之间的第一开关元件; 以及具有第二开关元件和第三开关元件的低侧开关元件，其并联连接在感性负载和参考电压线之间。当浪涌被施加到连接到低侧开关元件中的感性负载的端子时，浪涌电流通过第三开关元件放电到参考电压线。

54. 发明授权

US07061060B2 Offset-gate-type semiconductor device 失效
公开(公告)号：US07061060B2
公开(公告)日：2006-06-13
申请号：US10388509
申请日：2003-03-17
申请人： Norio Yasuhara , Syotaro Ono , Kazutoshi Nakamura , Yusuke Kawaguchi , Shinichi Hodama , Akio Nakagawa
发明人： Norio Yasuhara , Syotaro Ono , Kazutoshi Nakamura , Yusuke Kawaguchi , Shinichi Hodama , Akio Nakagawa
IPC分类号： H01L29/76
CPC分类号： H01L29/402 , H01L21/26586 , H01L29/1045 , H01L29/1079 , H01L29/1083 , H01L29/41725 , H01L29/4175 , H01L29/41758 , H01L29/41766 , H01L29/41775 , H01L29/456 , H01L29/66636 , H01L29/66659 , H01L29/78 , H01L29/7835
摘要： A semiconductor device includes a first semiconductor region having a first conductivity type, a second semiconductor region formed on the first semiconductor region and having the first conductivity type, a third semiconductor region formed in a surface of the second semiconductor region and having a second conductivity type, a fourth semiconductor region formed in the surface of the second semiconductor region and having the second conductivity type, and a gate structure formed on the second and fourth semiconductor region. The semiconductor device further includes a conductive member arranged in the trench extending from a surface of the fourth semiconductor region to the first semiconductor region, the trench having one sidewall surface flush with a sidewall surface of the gate structure.

55. 发明申请

US20050127440A1 MOS field effect transistor with reduced on-resistance 审中-公开
标题翻译：具有降低导通电阻的MOS场效应晶体管
公开(公告)号：US20050127440A1
公开(公告)日：2005-06-16
申请号：US11033391
申请日：2005-01-12
申请人： Norio Yasuhara , Akio Nakagawa , Yusuke Kawaguchi , Kazutoshi Nakamura
发明人： Norio Yasuhara , Akio Nakagawa , Yusuke Kawaguchi , Kazutoshi Nakamura
IPC分类号： H01L29/06 , H01L29/08 , H01L29/10 , H01L29/417 , H01L29/78 , H01L31/119
CPC分类号： H01L29/7816 , H01L29/0692 , H01L29/0696 , H01L29/0847 , H01L29/0878 , H01L29/0886 , H01L29/1045 , H01L29/4175 , H01L29/41766 , H01L29/7801 , H01L29/7818 , H01L29/7824 , H01L29/7833 , H01L29/7835
摘要： A semiconductor substrate includes a first principal plane and a second principal plane opposite this first principal plane. A first semiconductor region is formed on the first principal plane of the semiconductor substrate. Second and third semiconductor regions are formed separately from each other on the first semiconductor region. A gate electrode is formed, via a gate insulator, on the first semiconductor region between the second semiconductor region and the third semiconductor region. An electric conductor is formed up to the semiconductor substrate from the second semiconductor region and electrically connects the second semiconductor region with the semiconductor substrate. A first main electrode is formed on the second principal plane of the semiconductor substrate and is electrically connected to the semiconductor substrate. A second main electrode is formed on the first semiconductor region via insulators and is electrically connected to the third semiconductor region.
摘要翻译：半导体衬底包括第一主平面和与该第一主平面相对的第二主平面。第一半导体区域形成在半导体衬底的第一主平面上。第二半导体区域和第三半导体区域在第一半导体区域上彼此分开地形成。栅电极经由栅极绝缘体形成在第二半导体区域和第三半导体区域之间的第一半导体区域上。从第二半导体区域形成直到半导体衬底的电导体，并且将第二半导体区域与半导体衬底电连接。第一主电极形成在半导体衬底的第二主平面上，并与半导体衬底电连接。第二主电极通过绝缘体形成在第一半导体区上，并与第三半导体区电连接。

56. 发明授权

US06552389B2 Offset-gate-type semiconductor device 有权
公开(公告)号：US06552389B2
公开(公告)日：2003-04-22
申请号：US10013874
申请日：2001-12-13
申请人： Norio Yasuhara , Syotaro Ono , Kazutoshi Nakamura , Yusuke Kawaguchi , Shinichi Hodama , Akio Nakagawa
发明人： Norio Yasuhara , Syotaro Ono , Kazutoshi Nakamura , Yusuke Kawaguchi , Shinichi Hodama , Akio Nakagawa
IPC分类号： H01L2976
CPC分类号： H01L29/402 , H01L21/26586 , H01L29/1045 , H01L29/1079 , H01L29/1083 , H01L29/41725 , H01L29/4175 , H01L29/41758 , H01L29/41766 , H01L29/41775 , H01L29/456 , H01L29/66636 , H01L29/66659 , H01L29/78 , H01L29/7835
摘要： A semiconductor device includes a first semiconductor region having a first conductivity type, a second semiconductor region formed on the first semiconductor region and having the first conductivity type, a third semiconductor region formed in a surface of the second semiconductor region and having a second conductivity type, a fourth semiconductor region formed in the surface of the second semiconductor region and having the second conductivity type, and a gate structure formed on the second and fourth semiconductor region. The semiconductor device further includes a conductive member arranged in the trench extending from a surface of the fourth semiconductor region to the first semiconductor region, the trench having one sidewall surface flush with a sidewall surface of the gate structure.

57. 发明授权

US06878992B2 Vertical-type power MOSFET with a gate formed in a trench 有权
标题翻译：垂直型功率MOSFET，其栅极形成在沟槽中
公开(公告)号：US06878992B2
公开(公告)日：2005-04-12
申请号：US10091423
申请日：2002-03-07
申请人： Yusuke Kawaguchi , Norio Yasuhara , Kazutoshi Nakamura , Akio Nakagawa , Syotaro Ono
发明人： Yusuke Kawaguchi , Norio Yasuhara , Kazutoshi Nakamura , Akio Nakagawa , Syotaro Ono
IPC分类号： H01L21/28 , H01L21/336 , H01L29/41 , H01L29/423 , H01L29/78 , H01L29/76 , H01L29/94 , H01L31/062
CPC分类号： H01L29/66666 , H01L29/42368 , H01L29/7828
摘要： A power MOSFET comprises, between source and drain electrodes, a low resistive semiconductor substrate of a first conductivity type, a drift layer of the first conductivity type formed on the semiconductor substrate, a high resistive epitaxial layer of the first conductivity type formed on the drift layer, trenches formed to extend from a surface of the epitaxial layer into the drift layer, gate electrodes buried in the trenches with gate insulating films interposed between the gate electrodes and walls of the trenches, low resistive source layers of the first conductivity type formed in a surface region of the epitaxial layer adjacent to the gate insulating films, and a base layer of a second conductivity type formed in the surface region of the epitaxial layer, wherein the epitaxial layer intervening between the trenches is depleted in a case where 0 volt is applied between the source electrode and the gate electrodes.
摘要翻译：功率MOSFET在源极和漏极之间包括第一导电类型的低电阻半导体衬底，形成在半导体衬底上的第一导电类型的漂移层，形成在漂移上的第一导电类型的高电阻外延层形成为从外延层的表面延伸到漂移层中的沟槽，埋入沟槽中的栅电极，栅极绝缘膜插入在栅电极和沟槽的壁之间，形成在第一导电类型的低电阻源层与栅极绝缘膜相邻的外延层的表面区域和形成在外延层的表面区域中的第二导电类型的基极层，其中在0伏特的情况下，介于沟槽之间的外延层被耗尽施加在源电极和栅电极之间。

58. 发明授权

US08466516B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US08466516B2
公开(公告)日：2013-06-18
申请号：US12886461
申请日：2010-09-20
申请人： Kazutoshi Nakamura , Norio Yasuhara
发明人： Kazutoshi Nakamura , Norio Yasuhara
IPC分类号： H01L29/66
CPC分类号： H01L21/823857 , H01L21/823878 , H01L29/0619 , H01L29/1087 , H01L29/66659 , H01L29/7835
摘要： According to one embodiment, a semiconductor device includes a semiconductor substrate of a first conductivity type, an element isolation insulator, a source layer of a second conductivity type, a drain layer of the second conductivity type, a contact layer of the first conductivity type and a gate electrode. The element isolation insulator is formed on the semiconductor substrate. The source layer is formed on the semiconductor substrate and is in contact with a side surface of the element isolation insulator. The drain layer is formed on the semiconductor substrate, is in contact with the side surface, and is spaced from the source layer. The contact layer is formed between the source layer and the drain layer. The gate electrode is provided on the element isolation insulator along the side surface.
摘要翻译：根据一个实施例，半导体器件包括第一导电类型的半导体衬底，元件隔离绝缘体，第二导电类型的源极层，第二导电类型的漏极层，第一导电类型的接触层和栅电极。元件隔离绝缘体形成在半导体衬底上。源极层形成在半导体衬底上并与元件隔离绝缘体的侧表面接触。漏极层形成在半导体基板上，与侧面接触，与源极层隔开。接触层形成在源极层和漏极层之间。栅电极沿着侧面设置在元件隔离绝缘体上。

59. 发明申请

US20100140715A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20100140715A1
公开(公告)日：2010-06-10
申请号：US12630018
申请日：2009-12-03
申请人： Kazutoshi Nakamura , Norio Yasuhara
发明人： Kazutoshi Nakamura , Norio Yasuhara
IPC分类号： H01L27/06
CPC分类号： H01L29/0692 , H01L29/0653 , H01L29/0847 , H01L29/402 , H01L29/404 , H01L29/405 , H01L29/41725 , H01L29/41758 , H01L29/41775 , H01L29/42376 , H01L29/7835 , H02M3/1588 , Y02B70/1466
摘要： A semiconductor device includes: a semiconductor region of first conductivity type provided in a semiconductor layer of first conductivity type; a first semiconductor region of second conductivity type; a second semiconductor region of second conductivity type; a third semiconductor region of second conductivity type having a lower impurity concentration than the second semiconductor region of second conductivity type; a first insulating layer provided in the third semiconductor region of second conductivity type; a control electrode provided on the semiconductor region of first conductivity type via a second insulating layer; a first auxiliary electrode provided on the first insulating layer; a first main electrode electrically connected to the first semiconductor region of second conductivity type; and a second main electrode electrically connected to the second semiconductor region of second conductivity type.
摘要翻译：半导体器件包括：设置在第一导电类型的半导体层中的第一导电类型的半导体区域; 第二导电类型的第一半导体区域; 第二导电类型的第二半导体区域; 具有比第二导电类型的第二半导体区域低的杂质浓度的第二导电类型的第三半导体区域; 设置在第二导电类型的第三半导体区域中的第一绝缘层; 经由第二绝缘层设置在第一导电类型的半导体区上的控制电极; 设置在所述第一绝缘层上的第一辅助电极; 电连接到第二导电类型的第一半导体区域的第一主电极; 以及电连接到第二导电类型的第二半导体区域的第二主电极。

60. 发明申请

US20050056890A1 Offset-gate-type semiconductor device 失效
标题翻译：偏移栅型半导体器件
公开(公告)号：US20050056890A1
公开(公告)日：2005-03-17
申请号：US10957692
申请日：2004-10-05
申请人： Norio Yasuhara , Syotaro Ono , Kazutoshi Nakamura , Yusuke Kawaguchi , Shinichi Hodama , Akio Nakagawa
发明人： Norio Yasuhara , Syotaro Ono , Kazutoshi Nakamura , Yusuke Kawaguchi , Shinichi Hodama , Akio Nakagawa
IPC分类号： H01L21/265 , H01L21/336 , H01L29/06 , H01L29/10 , H01L29/40 , H01L29/417 , H01L29/45 , H01L29/78 , H01L29/76
CPC分类号： H01L29/402 , H01L21/26586 , H01L29/1045 , H01L29/1079 , H01L29/1083 , H01L29/41725 , H01L29/4175 , H01L29/41758 , H01L29/41766 , H01L29/41775 , H01L29/456 , H01L29/66636 , H01L29/66659 , H01L29/78 , H01L29/7835
摘要： A semiconductor device includes a first semiconductor region having a first conductivity type, a second semiconductor region formed on the first semiconductor region and having the first conductivity type, a third semiconductor region formed in a surface of the second semiconductor region and having a second conductivity type, a fourth semiconductor region formed in the surface of the second semiconductor region and having the second conductivity type, and a gate structure formed on the second and fourth semiconductor region. The semiconductor device further includes a conductive member arranged in the trench extending from a surface of the fourth semiconductor region to the first semiconductor region, the trench having one sidewall surface flush with a sidewall surface of the gate structure.
摘要翻译：半导体器件包括具有第一导电类型的第一半导体区域，形成在第一半导体区域上并且具有第一导电类型的第二半导体区域，形成在第二半导体区域的表面中并具有第二导电类型的第三半导体区域形成在第二半导体区域的表面上并具有第二导电类型的第四半导体区域以及形成在第二和第四半导体区域上的栅极结构。半导体器件还包括布置在从第四半导体区域的表面延伸到第一半导体区域的沟槽中的导电构件，沟槽具有与栅极结构的侧壁表面齐平的一个侧壁表面。

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